TLE 4269
Semiconductor Group
1
1998-11-01
Functional Description
This device is a voltage regulator with a fixed 5-V
output, e.g. in a P-DSO-8-1 package. The maximum
operating voltage is 45 V. The output is able to drive a
150 mA load. It is short circuit protected and the
thermal shutdown switches the output off if the junction
temperature is in excess of 150
C. A reset signal is
generated for an output voltage of
V
Q
< 4.6 V. The
reset threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time
can be set by an external capacitor. Reset and sense
output have integrated pull up resistors. If the
integrated resistors are not desired TLE 4279 can be
used. It is also possible to supervise the input voltage
by using an integrated comparator to give a low voltage
warning.
5-V Low-Drop Fixed Voltage Regulator
TLE 4269
P-DIP-8-4
P-DSO-8-1
P-DSO-20-6
P-DSO-14-4
Features
q
Output voltage tolerance
2 %
q
Very low current consumption
q
Early warning
q
Reset output low doown to
V
Q
= 1 V
q
Overtemperature protection
q
Reverse polarity proof
q
Settable reset threshold
q
Very low drop voltage
q
Wide temperature range
q
Integrated pull up resistor at logic outputs
w
New type
Type
Ordering Code
Package
TLE 4269 A
Q67000-A9190
P-DIP-8-4
TLE 4269 G
Q67006-A9173
P-DSO-8-1 (SMD)
w
TLE 4269 GM Q67006-A9288
P-DSO-14-4 (SMD)
TLE 4269 GL
Q67006-A9192
P-DSO-20-6 (SMD)
TLE 4269
Semiconductor Group
2
1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 A and TLE 4269 G)
Pin No.
Symbol
Function
1
I
Input; block directly to GND on the IC with a ceramic capacitor.
2
SI
Sense Input; if not needed connect to Q.
3
RE
Reset Threshold; if not needed connect to ground.
4
D
Reset Delay; to select delay time, connect to GND via external
capacitor.
5
GND
Ground
6
R
Reset Output; the open-collector output is internally linked to Q
via a 20 k
pull-up resistor.
7
SO
Sense Output; the open-collector output is internally linked to the
output via a 20 k
pull-up resistor.
8
Q
5-V Output; connect to GND with a 10
F capacitor, ESR < 10
.
GND
R
SO
D
5
6
7
RE
8
4
3
2
1
AEP01668
Q
S
P-DIP-8-4
P-DSO-8-1
S
AEP01813
1
8
SO
7
2
R
6
3
GND
D
5
4
RE
Q
TLE 4269
Semiconductor Group
3
1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 GM)
Pin No.
Symbol
Function
1
RE
Reset Threshold; if not needed connect to GND.
2
D
Reset Delay; connect to GND via external delay capacitor for
setting delay time.
3, 4, 5, 6
GND
Ground
7
R
Reset Output; open-collector output, internally connected to Q
via a pull-up resistor of 20 k
.
8
SO
Sense Output; open-collector output, internally connected to Q
via a 20 k
pull-up resistor.
9
Q
5-V Output; connect to GND with a 10
F capacitor, ESR < 10
.
10, 11, 12 GND
Ground
13
I
Input; block to GND directly at the IC by a ceramic capacitor.
14
SI
Sense Input; if not needed connect to Q.
P-DSO-14-4
AEP02248
Q
GND
SI
GND
R
GND
10
9
GND
GND
1
2
3
4
5
GND
6
7
SO
14
13
12
11
D
GND
8
RE
TLE 4269
Semiconductor Group
4
1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 GL)
Pin No.
Symbol
Function
1
RE
Reset Threshold; if not needed connect to GND.
2
D
Reset Delay; to select delay time connect to GND via external
capacitor.
4-7, 14-17
GND
Ground
10
R
Reset Output; the open-collector output is internally linked to
Q via 20 k
pull-up resistor.
11
SO
Sense Output; the open-collector output is internally linked to
Q via 20 k
pull-up resistor.
12
Q
Output; connect to GND with a 10
F capacitor, ESR < 10
.
19
I
Input; block directly to GND at the IC by a ceramic capacitor.
20
SI
Sense Input; if not needed connect to Q.
P-DSO-20-6
N.C.
12
11
N.C.
N.C.
GND
1
2
3
4
20
5
19
6
18
7
N.C.
17
8
Q
16
9
15
10
14
13
RE
D
GND
AEP01802
N.C.
GND
GND
R
S
GND
SO
GND
GND
GND
TLE 4269
Semiconductor Group
5
1998-11-01
Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output voltage and drives the base of the
series PNP transistor via a buffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is set to low. This low is
guaranteed down to an output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the
capacitor voltage reaches the upper switching threshold
V
dT
, the reset returns to high. By
choosing the value of this capacitor, the reset delay time can be selected over a wide
range. With the reset threshold input RE it is possible to lower the reset threshold
V
rt
. If
pin RE is connected to pin Q via a voltage divider, for example, the reset condition is
reached when this voltage is decreased below the switching threshold
V
re
of 1.35 V.
Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.
Application Description
The input capacitor
C
I
is necessary for compensating line influences. Using a resistor of
approx. 1
in series with
C
I
, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor
C
Q
is necessary for the stability of the
regulating circuit. Stability is guaranteed at values
10
F and an ESR
10
within the
operating temperature range. For small tolerances of the reset delay the spread of the
capacitance of the delay capacitor and its temperature coefficient should be noted.
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