2-9750-D1-5.2-1003

STAC9750/51

Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output

1. TABLE OF CONTENTS

1. TABLE OF CONTENTS ............................................................................................................. 2

1.1. List of Figures ....................................................................................................................................5
1.2. List of Tables ......................................................................................................................................5

2. PRODUCT BRIEF ...................................................................................................................... 7

2.1. Features .............................................................................................................................................7
2.2. Description .........................................................................................................................................7
2.3. Ordering Information ..........................................................................................................................8
2.4. STAC9750/51 Block Diagram ...........................................................................................................9
2.5. Key Specifications ..............................................................................................................................9
2.6. Related Materials ...............................................................................................................................9
2.7. Additional Support ..............................................................................................................................9

3. CHARACTERISTICS/SPECIFICATIONS ................................................................................ 10

3.1. Electrical Specifications ...................................................................................................................10

3.1.1. Absolute Maximum Ratings: ..............................................................................................10
3.1.2. Recommended Operating Conditions ...............................................................................10
3.1.3. Power Consumption . .........................................................................................................10
3.1.4. Revision Comparision ........................................................................................................11
3.1.5. AC-Link Static Digital Specifications ..................................................................................12
3.1.6. STAC9750 Analog Performance Characteristics ...............................................................12
3.1.7. STAC9751 Analog Performance Characteristics ...............................................................13

3.2. AC Timing Characteristics ...............................................................................................................15

3.2.1. Cold Reset .........................................................................................................................15
3.2.2. Warm Reset .......................................................................................................................15
3.2.3. Clocks ................................................................................................................................16
3.2.4. Data Setup and Hold ..........................................................................................................17
3.2.5. Signal Rise and Fall Times ................................................................................................17
3.2.6. AC-Link Low Power Mode Timing ......................................................................................18
3.2.7. ATE Test Mode ..................................................................................................................18

4. TYPICAL CONNECTION DIAGRAM ....................................................................................... 19
5. AC-LINK ................................................................................................................................... 20

5.1. Clocking ...........................................................................................................................................20
5.2. Reset ................................................................................................................................................20

6. DIGITAL INTERFACE .............................................................................................................. 21

6.1. AC-Link Digital Serial Interface Protocol ..........................................................................................21

6.1.1. AC-Link Audio Output Frame (SDATA_OUT) ....................................................................22

6.1.1.1. Slot 1: Command Address Port ........................................................................23
6.1.1.2. Slot 2: Command Data Port ..............................................................................23
6.1.1.3. Slot 3: PCM Playback Left Channel ..................................................................23
6.1.1.4. Slot 4: PCM Playback Right Channel ...............................................................23
6.1.1.5. Slot 5: Reserved ...............................................................................................24
6.1.1.6. Slot 6: PCM Center Channel ............................................................................24
6.1.1.7. Slot 7: PCM Left Surround Channel .................................................................24
6.1.1.8. Slot 8: PCM Right Surround Channel ...............................................................24
6.1.1.9. Slot 9: PCM Low Frequency Channel ...............................................................24

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Inc.

SigmaTel, the SigmaTel logo, and combinations thereof are trademarks of SigmaTel, Inc. Other product names used in this publication
are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this
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pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes
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any and all liability, including without limitation special, consequential, or incidental damages.

2-9750-D1-5.2-1003

STAC9750/51

Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output

6.1.1.10. Slot 10: PCM Alternate Left ............................................................................24
6.1.1.11. Slot 11: PCM Alternate Right ..........................................................................24
6.1.1.12. Slot 12: Reserved ...........................................................................................24

6.1.2. AC-Link Audio Input Frame (SDATA_IN) ...........................................................................25

6.1.2.1. Slot 1: Status Address Port ...............................................................................26
6.1.2.2. Slot 2: Status Data Port ....................................................................................26
6.1.2.3. Slot 3: PCM Record Left Channel .....................................................................26
6.1.2.4. Slot 4: PCM Record Right Channel ..................................................................27
6.1.2.5. Slot 5: Reserved ...............................................................................................27
6.1.2.6. Slot 6: PCM Left Record Channel ....................................................................27
6.1.2.7. Slot 7: PCM Left Record Channel ....................................................................27
6.1.2.8. Slot 8: PCM Right Record Channel .................................................................27
6.1.2.9. Slot 9: PCM Right Record Channel .................................................................27
6.1.2.10. Slot 10: PCM Left Record Channel ................................................................28
6.1.2.11. Slot 11: PCM Right Record Channel .............................................................28
6.1.2.12. Slot 12: Reserved ..........................................................................................28

6.2. AC-Link Low Power Mode ...............................................................................................................28
6.3. Waking up the AC-Link ....................................................................................................................29

7. STAC9750/51 MIXER .............................................................................................................. 30

7.1. Analog Mixer Input ...........................................................................................................................32
7.2. Analog Mixer Output ........................................................................................................................32
7.3. SPDIF Digital Mux ............................................................................................................................32
7.4. PC Beep Implementation .................................................................................................................32
7.5. Programming Registers ...................................................................................................................33

7.5.1. Reset (00h) ........................................................................................................................34
7.5.2. Play Master Volume Registers (Index 02h, 04h, and 06h) .................................................34

7.5.2.1. Master Volume (02h) ........................................................................................34
7.5.2.2. Headphone Out Volume (04h) ..........................................................................34
7.5.2.3. Master Volume MONO (06h) ............................................................................35

7.5.3. PC Beep Mixer Volume (Index 0Ah) ..................................................................................35
7.5.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h) .......................................................36

7.5.4.1. Phone Mixer Volume (0Ch) ..............................................................................36
7.5.4.2. Mic Mixer Volume (0Eh) ...................................................................................36
7.5.4.3. Line In Mixer Volume (10h) ...............................................................................36
7.5.4.4. CD Mixer Volume (12h) ....................................................................................36
7.5.4.5. Video Mixer Volume (14h) ................................................................................37
7.5.4.6. AUX Mixer Volume (16h) ..................................................................................37
7.5.4.7. PCM Out Mixer Volume (18h) ...........................................................................37

7.5.5. Record Select (1Ah) ...........................................................................................................37
7.5.6. Record Gain (1Ch) .............................................................................................................38
7.5.7. General Purpose (20h) .......................................................................................................38
7.5.8. 3D Control (22h) .................................................................................................................39
7.5.9. Audio Interrupt (24h) ..........................................................................................................39
7.5.10. Powerdown Ctrl/Stat (26h) ...............................................................................................40

7.5.10.1. Ready Status ..................................................................................................40
7.5.10.2. Powerdown Controls .......................................................................................41
7.5.10.3. External Amplifier Power Down Control ..........................................................41

7.5.11. Extended Audio ID (28h) ..................................................................................................41
7.5.12. Extended Audio Control/Status (2Ah) ..............................................................................42

7.5.12.1. Variable Rate Sampling Enable ......................................................................42
7.5.12.2. SPDIF .............................................................................................................43
7.5.12.3. SPCV (SPDIF Configuration Valid) .................................................................43
7.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment) ......................................................43

7.5.13. PCM DAC Rate Registers (2Ch and 32h) ........................................................................44
7.5.14. PCM DAC Rate (2Ch) ......................................................................................................44
7.5.15. PCM LR ADC Rate (32h) .................................................................................................44
7.5.16. SPDIF Control (3Ah) ........................................................................................................45

2-9750-D1-5.2-1003

STAC9750/51

Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output

7.5.17. Extended Modem Status and Control Register (3Eh)

(Used in Revision CC1 and beyond)

7.5.18. GPIO Pin Configuration Register (4Ch)

(Used in Revision CC1 and beyond) .................46

7.5.19. GPIO Pin Polarity/Type Register (4Eh)

(Used in Revision CC1 and beyond) ...................46

7.5.20. GPIO Pin Sticky Register (50h)

(Used in Revision CC1 and beyond) .............................47

7.5.21. GPIO Pin Mask Register (52h)

(Used in Revision CC1 and beyond) ...............................47

7.5.22. GPIO Pin Status Register (54h)

(Used in Revision CC1 and beyond) .............................48

7.5.23. Digital Audio Control (6Ah) ...............................................................................................48
7.5.24. Revision Code (6Ch) ........................................................................................................49
7.5.25. Analog Special (6Eh) .......................................................................................................49

7.5.25.1. ALL MIX ..........................................................................................................49
7.5.25.2. ADC Data on AC LINK ....................................................................................50
7.5.25.3. MuteFix Disable

(Used in Revision CC1 and beyond) ....................................50

7.5.25.4. Mic Boost Select .............................................................................................50
7.5.25.5. Supply Override Select ...................................................................................50
7.5.25.6. 72h Enable (70h) ............................................................................................50
7.5.25.7. Analog Current Adjust (72h) ...........................................................................51
7.5.25.8. Internal Power-On/Off Anti-Pop Circuit ...........................................................51

7.5.26. GPIO Access Register (74h)

(Used only in CA3 revision for GPIO) ................................52

7.5.27. High Pass Filter Bypass (Index 76h and 78h) ..................................................................52

7.5.27.1. 78h Enable (76h) ............................................................................................52
7.5.27.2. ADC High Pass FIlter Bypass(78h) ................................................................53

7.5.28. Vendor ID1 and ID2 (Index 7Ch and 7Eh) .......................................................................53

7.5.28.1. Vendor ID1 (7Ch) ............................................................................................53
7.5.28.2. Vendor ID2 76xx (7Eh) ...................................................................................53

8. LOW POWER MODES ............................................................................................................54
9. MULTIPLE CODEC SUPPORT ...............................................................................................56

9.1. Primary/Secondary Codec Selection ...............................................................................................56

9.1.1. Primary Codec Operation ...................................................................................................56
9.1.2. Secondary Codec Operation ..............................................................................................56

9.2. Secondary Codec Register Access Definitions ................................................................................57

10. TESTABILITY ........................................................................................................................ 58
11. PIN DESCRIPTION ................................................................................................................ 59

11.1. Digital I/O .......................................................................................................................................60
11.2. Analog I/O ......................................................................................................................................61
11.3. Filter/References/GPIO ..................................................................................................................62
11.4. Power and Ground Signals ............................................................................................................62

12. PACKAGE DRAWING .......................................................................................................... 63
13. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION .............................. 64
14. APPENDIX B: PROGRAMMING REGISTERS .....................................................................66
15. DOCUMENT HISTORY ..........................................................................................................67

2-9750-D1-5.2-1003

STAC9750/51

Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output

1.1.

List of Figures

Figure 1. STAC9750/51 Block Diagram ...........................................................................................................9
Figure 2. Cold Reset Timing ..........................................................................................................................15
Figure 3. Warm Reset Timing ........................................................................................................................15
Figure 4. Clocks Timing .................................................................................................................................16
Figure 5. Data Setup and Hold Timing ...........................................................................................................17
Figure 6. Signal Rise and Fall Times Timing ..................................................................................................17
Figure 7. AC-Link Low Power Mode Timing ...................................................................................................18
Figure 8. ATE Test Mode Timing ...................................................................................................................18
Figure 9. STAC9751 Typical Connection Diagram ........................................................................................19
Figure 10. AC-Link to its Companion Controller .............................................................................................20
Figure 11. AC'97 Standard Bi-directional Audio Frame .................................................................................21
Figure 12. AC-Link Audio Output Frame ........................................................................................................22
Figure 13. Start of an Audio Output Frame ....................................................................................................22
Figure 14. STAC9750/51 Audio Input Frame .................................................................................................25
Figure 15. Start of an Audio Input Frame .......................................................................................................26
Figure 16. STAC9750/51 Powerdown Timing ................................................................................................28
Figure 17. STAC9750 2-Channel Mixer Functional Diagram .........................................................................31
Figure 18. STAC9751 2-Channel Mixer Functional Diagram .........................................................................31
Figure 19. Example of STAC9750/51 Powerdown/Powerup flow ..................................................................54
Figure 20. STAC9750/51 Powerdown/Powerup flow with analog still alive ...................................................55
Figure 21. STAC9750/51 Pin Description Drawing ........................................................................................59
Figure 22. 48-Pin TQFP Package Drawing ....................................................................................................63
Figure 23. STAC9750/51 Split Independent Power Supply Operation Typical Connection Diagram ............65

1.2.

List of Tables

Table 1. Recommended Operating Conditions. .............................................................................................10
Table 2. Power Consumption .........................................................................................................................10
Table 3. AC-Link Static Specifications ...........................................................................................................12
Table 4. STAC9750 Analog Performance Characteristics .............................................................................12
Table 5. STAC9751 Analog Performance Characteristics .............................................................................13
Table 6. Cold Reset Specifications ................................................................................................................15
Table 7. Warm Reset Specifications ..............................................................................................................15
Table 8. Clocks Specifications .......................................................................................................................16
Table 9. Clock mode configuration .................................................................................................................16
Table 10. Data Setup and Hold Specifications ...............................................................................................17
Table 11. Signal Rise and Fall Times Specifications .....................................................................................17
Table 12. AC-Link Low Power Mode Timing Specifications ...........................................................................18
Table 13. ATE Test Mode Specifications .......................................................................................................18
Table 14. STAC9750/51 Available Data Streams ..........................................................................................21
Table 15. Command Address Port Bit Assignments ......................................................................................23
Table 16. Command Data Port Bit Assignments ............................................................................................23
Table 17. Status Address Port Bit Assignments .............................................................................................26
Table 18. Status Data Port Bit Assignments ..................................................................................................26
Table 19. Programming Registers ..................................................................................................................33
Table 20. Play Master Volume Register .........................................................................................................34
Table 21. PC_BEEP Register ........................................................................................................................35
Table 22. Analog Mixer Input Gain Register ..................................................................................................36
Table 23. Record Select Control Registers ....................................................................................................37
Table 24. Record Gain Registers ..................................................................................................................38
Table 25. General Purpose Register ..............................................................................................................38
Table 26. 3D Control Registers .....................................................................................................................39
Table 27. Powerdown Status Registers .........................................................................................................40

Электронный компонент: STAC9750T

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