Integrated Mixed-Signal Solutions
STAC9752/53
Two-Channel, 20-Bit, AC'97 2.3 Codecs
with Microphone and Jack Sensing
Data Sheet Revision 3.2
Two-Channel, 20-Bit, AC'97 2.3 Codecs with Microphone and Jack Sensing
2-9752-D1-3.2-1003
2
2-9752-D1-3.2-1003
STAC9752/53
Two-Channel, 20-Bit, AC'97 2.3 Codecs with Microphone and Jack Sensing
1. TABLE OF CONTENTS
1. TABLE OF CONTENTS ............................................................................................................. 2
1.1. List of Figures ....................................................................................................................................5
1.2. List of Tables ......................................................................................................................................6
2. PRODUCT BRIEF ...................................................................................................................... 7
2.1. Features .............................................................................................................................................7
2.2. Description .........................................................................................................................................7
2.3. STAC9752/53 Block Diagram ...........................................................................................................9
2.4. Key Specifications ..............................................................................................................................9
2.5. Related Materials .............................................................................................................................10
2.6. Additional Support ............................................................................................................................10
3. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 11
3.1. Electrical Specifications ...................................................................................................................11
3.1.1. Absolute Maximum Ratings: ..............................................................................................11
3.1.2. Recommended Operating Conditions ..............................................................................11
3.1.3. Power Consumption .........................................................................................................12
3.1.4. AC-Link Static Digital Specifications .................................................................................13
3.1.5. STAC9752 5V Analog Performance Characteristics .........................................................13
3.1.6. STAC9753 3.3V Analog Performance Characteristics ......................................................15
3.2. AC Timing Characteristics ...............................................................................................................17
3.2.1. Cold Reset .........................................................................................................................17
3.2.2. Warm Reset .....................................................................................................................17
3.2.3. Clocks ..............................................................................................................................18
3.2.4. STAC9752/53 Crystal Elimination Circuit and Clock Frequencies .....................................18
3.2.5. Data Setup and Hold ........................................................................................................19
3.2.6. Signal Rise and Fall Times ...............................................................................................19
3.2.7. AC-Link Low Power Mode Timing .....................................................................................20
3.2.8. ATE Test Mode .................................................................................................................20
4. TYPICAL CONNECTION DIAGRAM ....................................................................................... 21
4.1. Slit Independent Power Supply Operation .......................................................................................22
5. CONTROLLER, CODEC, AND AC-LINK ................................................................................ 23
5.1. AC-link Physical interface ................................................................................................................23
5.2. Controller to Single Codec ...............................................................................................................23
5.3. Controller to Multiple Codecs ...........................................................................................................25
5.3.1. Primary Codec Addressing ................................................................................................25
5.3.2. Secondary Codec Addressing ............................................................................................26
5.3.3. Codec ID Strapping ............................................................................................................26
5.4. Clocking for Multiple Codec Implementations ..................................................................................26
5.5. STAC9752/53 as a Primary Codec ..................................................................................................27
5.5.1. STAC9752/53 as a Secondary Codec ...............................................................................27
5.6. AC-link Power Management ............................................................................................................27
5.6.1. Powering down the AC-link ................................................................................................27
5.6.2. Waking up the AC-link ........................................................................................................28
5.6.2.1. Controller Initiates Wake-up .............................................................................28
5.6.2.2. Codec Initiates Wake-up ...................................................................................28
5.6.3. Codec Reset ......................................................................................................................28
Copyright 2002 SigmaTel, Inc. All rights reserved.
All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel,
Inc.
SigmaTel, the SigmaTel logo, and combinations thereof are trademarks of SigmaTel, Inc. Other product names used in this publication
are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this
document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information
contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or com-
pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes
to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without
notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation special, consequential, or incidental damages.
2-9752-D1-3.2-1003
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STAC9752/53
Two-Channel, 20-Bit, AC'97 2.3 Codecs with Microphone and Jack Sensing
5.6.4. Cold AC `97 Reset ..............................................................................................................29
5.6.5. Warm AC `97 Reset ...........................................................................................................29
5.6.6. Register AC `97 Reset ........................................................................................................29
6. AC-LINK DIGITAL INTERFACE .............................................................................................. 30
6.1. Overview ..........................................................................................................................................30
6.2. AC-link Serial Interface Protocol ......................................................................................................31
6.2.1. AC-link Variable Sample Rate Operation ...........................................................................31
6.2.2. Variable Sample Rate Signaling Protocol ..........................................................................32
6.2.2.1. SLOTREQ Behavior and Power Management .................................................33
6.2.3. Primary and Secondary Codec Register Addressing .........................................................33
6.3. AC-link Output Frame (SDATA_OUT) ...........................................................................................34
6.3.1. Slot 0: TAG / Codec ID ......................................................................................................35
6.3.2. Slot 1: Command Address Port .........................................................................................36
6.3.3. Slot 2: Command Data Port ..............................................................................................36
6.3.4. Slot 3: PCM Playback Left Channel ..................................................................................36
6.3.5. Slot 4: PCM Playback Right Channel ................................................................................37
6.3.6. Slot 5: Modem Line 1 Output Channel ..............................................................................37
6.3.7. Slot 6 -11: DAC ................................................................................................................37
6.3.8. Slot 12: Audio GPIO Control Channel ...............................................................................37
6.4. AC-link Input Frame (SDATA_IN) .................................................................................................37
6.4.1. Slot 0: TAG .........................................................................................................................38
6.4.2. Slot 1: Status Address Port / SLOTREQ signaling bits .....................................................38
6.4.2.1. Status Address Port ..........................................................................................38
6.4.2.2. SLOTREQ signaling bits ...................................................................................39
6.4.3. Slot 2: Status Data Port .....................................................................................................39
6.4.4. Slot 3: PCM Record Left Channel .....................................................................................40
6.4.5. Slot 4: PCM Record Right Channel ...................................................................................40
6.4.6. Slot 5: Modem Line 1 ADC .................................................................................................40
6.4.7. Slot 6-9: ADC .....................................................................................................................40
6.4.8. Slots 7-8: Vendor Reserved ..............................................................................................40
6.4.9. Slot 10 & 11: ADC ..............................................................................................................40
6.4.10. Slot 12: Reserved .............................................................................................................40
6.5. AC-link Interoperability Requirements and Recommendations ........................................................41
6.5.1. "Atomic slot" Treatment of Slot 1 Address and Slot 2 Data ................................................41
6.6. Slot Assignments for Audio .............................................................................................................42
7. STAC9752/53 MIXER ............................................................................................................. 43
8. MIXER FUNCTIONAL DIAGRAMS ........................................................................................ 44
8.1. Analog Mixer Input .........................................................................................................................45
8.2. Mixer Analog Output .......................................................................................................................45
8.3. SPDIF Digital Mux ............................................................................................................................45
8.4. PC Beep Implementation .................................................................................................................46
8.4.1. Analog PC Beep .................................................................................................................46
8.4.2. Digital PC Beep ..................................................................................................................46
9. PROGRAMMING REGISTERS .............................................................................................. 47
9.1. Register Descriptions .......................................................................................................................48
9.1.1. Reset (00h) ......................................................................................................................48
9.1.2. Master Volume Registers (02h) ..............................................................................49
9.1.3. Headphone Volume Registers (04h) ..................................................................................50
9.1.4. Master Volume MONO (06h) ...........................................................................................50
9.1.5. PC BEEP Volume (0Ah) ....................................................................................................51
9.1.6. Phone Volume (Index 0Ch) ...............................................................................................51
9.1.7. Mic Volume (Index 0Eh) .....................................................................................................52
9.1.8. LineIn Volume (Index 10h) ................................................................................................52
9.1.9. CD Volume (Index 12h) .....................................................................................................53
9.1.10. Video Volume (Index 14h) ..............................................................................................53
9.1.11. Aux Volume (Index 16h) ..................................................................................................54
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2-9752-D1-3.2-1003
STAC9752/53
Two-Channel, 20-Bit, AC'97 2.3 Codecs with Microphone and Jack Sensing
9.1.12. PCMOut Volume (Index 18h) ..........................................................................................54
9.1.13. Record Select (1Ah) ........................................................................................................55
9.1.14. Record Gain (1Ch) ..........................................................................................................55
9.1.15. General Purpose (20h) ....................................................................................................56
9.1.16. 3D Control (22h) ..............................................................................................................56
9.1.17. Audio Interrupt and Paging (24h) .....................................................................................57
9.1.18. Powerdown Ctrl/Stat (26h) ...............................................................................................58
9.1.18.1. Ready Status .................................................................................................59
9.1.18.2. External Amplifier Power Down Control Output ..............................................59
9.1.19. Extended Audio ID (28h) .................................................................................................59
9.1.20. Extended Audio Control/Status (2Ah) .............................................................................61
9.1.20.1. Variable Rate Sampling Enable .....................................................................62
9.1.20.2. SPDIF ............................................................................................................62
9.1.20.3. SPCV (SPDIF Configuration Valid) ................................................................62
9.1.20.4. SPSA1, SPSA0 (SPDIF Slot Assignment) ....................................................62
9.1.21. PCM DAC Rate Registers (2Ch and 32h) .......................................................................63
9.1.22. PCM DAC Rate (2Ch) .....................................................................................................63
9.1.23. PCM LR ADC Rate (32h) ...............................................................................................63
9.1.24. SPDIF Control (3Ah) ........................................................................................................63
9.2. General Purpose Input & Outputs ....................................................................................................64
9.2.1. EAPD .................................................................................................................................64
9.2.2. GPIO Pin Definitions ..........................................................................................................64
9.2.3. GPIO Pin Implementation ..................................................................................................65
9.2.4. Extended Modem Status and Control Register (3Eh) ........................................................65
9.2.5. GPIO Pin Configuration Register (4Ch) .............................................................................65
9.2.6. GPIO Pin Polarity/Type Register (4Eh) ..............................................................................66
9.2.7. GPIO Pin Sticky Register (50h) ..........................................................................................66
9.2.8. GPIO Pin Mask Register (52h) ...........................................................................................66
9.2.9. GPIO Pin Status Register (54h) .........................................................................................67
9.3. Extended Codec Registers Page Structure Definition .....................................................................68
9.3.1. Extended Registers Page 00 .............................................................................................68
9.3.2. Extended Registers Page 01 .............................................................................................68
9.3.3. Extended Registers Page 02, 03 .......................................................................................68
9.4. STAC9752/53 Paging Registers ......................................................................................................69
9.4.1. Codec Class/Rev (60h
Page 01h
) ...................................................................................69
9.4.2. PCI SVID (62h
Page 01h
) ................................................................................................70
9.4.3. PCI SSID (64h
Page 01h
) ................................................................................................70
9.4.4. Function Select (66h
Page 01h
) .......................................................................................71
9.4.5. Function Information (68h
Page 01h
) ...............................................................................72
9.4.6. Digital Audio Control (6Ah, Page 00h) ...............................................................................74
9.4.7. Sense Details (6Ah
Page 01h
) .........................................................................................74
9.4.8. Revision Code (6Ch) .........................................................................................................76
9.4.9. Analog Special (6Eh) .........................................................................................................76
9.4.10. Analog Current Adjust (72h) .............................................................................................77
9.4.11. EAPD Access Register (74h) ..........................................................................................77
9.4.12. High Pass Filter Bypass (78h) .........................................................................................78
9.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) .......................................................................................79
9.5.1. Vendor ID1 (7Ch) ..............................................................................................................79
9.5.2. Vendor ID2 (7Eh) ...............................................................................................................79
10. LOW POWER MODES ........................................................................................................ 80
11. MULTIPLE CODEC SUPPORT ............................................................................................ 82
11.1. Primary/Secondary Codec Selection .............................................................................................82
11.1.1. Primary Codec Operation ................................................................................................82
11.1.2. Secondary Codec Operation ...........................................................................................82
11.2. Secondary Codec Register Access Definitions .............................................................................83
12. TESTABILITY ........................................................................................................................ 84
12.0.1. ATE Test Mode ................................................................................................................84
2-9752-D1-3.2-1003
5
STAC9752/53
Two-Channel, 20-Bit, AC'97 2.3 Codecs with Microphone and Jack Sensing
13. PIN DESCRIPTION ............................................................................................................... 85
13.1. Digital I/O .....................................................................................................................................86
13.2. Analog I/O .....................................................................................................................................87
13.3. Filter/References ..........................................................................................................................87
13.4. Power and Ground Signals ..........................................................................................................88
14. PACKAGE DRAWING .......................................................................................................... 89
15. APPENDIX A: PROGRAMMING REGISTERS .....................................................................90
16. DOCUMENT HISTORY ..........................................................................................................92
1.1.
List of Figures
Figure 1. Block Diagram ...................................................................................................................................9
Figure 2. Cold Reset Timing ..........................................................................................................................17
Figure 3. Warm Reset Timing ........................................................................................................................17
Figure 4. Clocks Timing .................................................................................................................................18
Figure 5. Data Setup and Hold Timing ...........................................................................................................19
Figure 6. Signal Rise and Fall Times Timing ..................................................................................................19
Figure 7. AC-Link Low Power Mode Timing ...................................................................................................20
Figure 8. ATE Test Mode Timing ...................................................................................................................20
Figure 9. Typical Connection Diagram ...........................................................................................................21
Figure 10. Split Independent Power Supply Operation ..................................................................................22
Figure 11. AC-Link to its Companion Controller .............................................................................................23
Figure 12. Codec Clock Source Detection ....................................................................................................24
Figure 13. STAC9752/53 Powerdown Timing ................................................................................................27
Figure 14. Bi-directional AC-link Frame with Slot assignments ......................................................................30
Figure 15. AC-Link Audio Output Frame ........................................................................................................34
Figure 16. Start of an Audio Output Frame ....................................................................................................35
Figure 17. STAC9752/53 Audio Input Frame .................................................................................................37
Figure 18. Start of an Audio Input Frame .......................................................................................................38
Figure 19. Bi-directional AC-link Frame with Slot assignments ......................................................................42
Figure 20. STAC9752 2-Channel Mixer Functional Diagram .........................................................................44
Figure 21. STAC9753 2-Channel Mixer Functional Diagram .........................................................................44
Figure 22. Example of STAC9752/53 Powerdown/Powerup flow ..................................................................80
Figure 23. Powerdown/Powerup flow with analog still alive ...........................................................................81
Figure 24. Pin Description Drawing ................................................................................................................85
Figure 25. 48-Pin TQFP Package Drawing ....................................................................................................89
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