Integrating Mixed-Signal Solutions
PRODUCT DATA SHEET
STAC9756/57
Two Channel AC'97 Codecs with
I
2
S Digital I/O and SPDIF Output
Two Channel AC'97 Codecs with I
2
S Digital I/O and SPDIF Output
2-9756-D1-3.3-0303
2
2-9756-D1-3.3-0303
STAC9756/57
Two Channel AC'97 Codecs with I
2
S Digital I/O and SPDIF Output
1. TABLE OF CONTENTS
1. TABLE OF CONTENTS ............................................................................................................. 2
1.1. List of Figures ....................................................................................................................................4
1.2. List of Tables ......................................................................................................................................5
2. PRODUCT BRIEF ...................................................................................................................... 6
2.1. Features .............................................................................................................................................6
2.2. Description .........................................................................................................................................6
2.3. Ordering Information ..........................................................................................................................7
2.4. STAC9756/57 Block Diagram ...........................................................................................................8
2.5. Key Specifications ..............................................................................................................................8
2.6. Related Materials ...............................................................................................................................8
2.7. Additional Support ..............................................................................................................................8
3. CHARACTERISTICS/SPECIFICATIONS .................................................................................. 9
3.1. Electrical Specifications .....................................................................................................................9
3.1.1. Absolute Maximum Ratings: ................................................................................................9
3.1.2. Recommended Operating Conditions ................................................................................9
3.1.3. Power Consumption ...........................................................................................................9
3.1.4. AC-Link Static Digital Specifications ..................................................................................10
3.1.5. STAC9756 Analog Performance Characteristics ...............................................................10
3.1.6. STAC9757 Analog Performance Characteristics ...............................................................11
3.2. AC Timing Characteristics ...............................................................................................................13
3.2.1. Cold Reset .........................................................................................................................13
3.2.2. Warm Reset .......................................................................................................................13
3.2.3. Clocks ................................................................................................................................14
3.2.4. Data Setup and Hold ..........................................................................................................14
3.2.5. Signal Rise and Fall Times ................................................................................................15
3.2.6. AC-Link Low Power Mode Timing ......................................................................................15
3.2.7. ATE Test Mode ..................................................................................................................16
4. TYPICAL CONNECTION DIAGRAM (3.3V OPERATION) ...................................................... 17
5. AC-LINK ................................................................................................................................... 18
5.1. Clocking ...........................................................................................................................................18
5.2. Reset ................................................................................................................................................18
6. DIGITAL INTERFACE .............................................................................................................. 19
6.1. AC-Link Digital Serial Interface Protocol ..........................................................................................19
6.1.1. AC-Link Audio Output Frame (SDATA_OUT) ...................................................................19
6.1.1.1. Slot 1: Command Address Port .......................................................................21
6.1.1.2. Slot 2: Command Data Port ..............................................................................21
6.1.1.3. Slot 3: PCM Playback Left Channel ..................................................................21
6.1.1.4. Slot 4: PCM Playback Right Channel ...............................................................22
6.1.1.5. Slot 5: Reserved ...............................................................................................22
6.1.1.6. Slot 6: PCM Center Channel ............................................................................22
6.1.1.7. Slot 7: PCM Left Surround Channel .................................................................22
6.1.1.8. Slot 8: PCM Right Surround Channel ...............................................................22
6.1.1.9. Slot 9: PCM Low Frequency Channel ...............................................................22
6.1.1.10. Slot 10: PCM Alternate Left ............................................................................22
6.1.1.11. Slot 11: PCM Alternate Right ..........................................................................23
Copyright 2001 SigmaTel, Inc. All rights reserved.
All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel,
Inc.
SigmaTel, the SigmaTel logo, and combinations thereof are trademarks of SigmaTel, Inc. Other product names used in this publication
are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this
document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information
contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or com-
pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes
to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without
notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation special, consequential, or incidential damages.
2-9756-D1-3.3-0303
3
STAC9756/57
Two Channel AC'97 Codecs with I
2
S Digital I/O and SPDIF Output
6.1.1.12. Slot 12: Reserved ...........................................................................................23
6.1.2. AC-Link Audio Input Frame (SDATA_IN) ...........................................................................23
6.1.2.1. Slot 1: Status Address Port ..............................................................................24
6.1.2.2. Slot 2: Status Data Port ...................................................................................25
6.1.2.3. Slot 3: PCM Record Left Channel .....................................................................25
6.1.2.4. Slot 4: PCM Record Right Channel ..................................................................25
6.1.2.5. Slots 5-12: Reserved ........................................................................................25
6.2. AC-Link Low Power Mode ...............................................................................................................25
6.2.1. Waking up the AC-Link ......................................................................................................26
6.3. I2S (ZV_PORT) Digital Audio Interface ...........................................................................................26
7. STAC9756/57 MIXER .............................................................................................................. 27
7.1. Analog Mixer Input ...........................................................................................................................28
7.2. Mixer Analog Output ........................................................................................................................29
7.3. Mixer Digital Input ............................................................................................................................29
7.4. Mixer Digital Output .........................................................................................................................29
7.5. PC Beep Implementation .................................................................................................................29
7.6. Programming Registers ...................................................................................................................30
7.6.1. Reset (00h) ........................................................................................................................31
7.6.2. Play Master Volume Registers (Index 02h, 04h, and 06h) .................................................31
7.6.2.1. Master Volume (02h) ........................................................................................31
7.6.2.2. LNLVL Mixer Volume (04h) ..............................................................................32
7.6.2.3. Master Volume MONO (06h) ............................................................................32
7.6.3. PC Beep Mixer Volume (Index 0Ah) ..................................................................................32
7.6.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h) .......................................................33
7.6.4.1. Phone Mixer Volume (0Ch) .............................................................................33
7.6.4.2. Mic Mixer Volume (0Eh) ...................................................................................33
7.6.4.3. Line In Mixer Volume (10h) ...............................................................................33
7.6.4.4. CD Mixer Volume (12h) ....................................................................................33
7.6.4.5. Video Mixer Volume (14h) ................................................................................34
7.6.4.6. AUX Mixer Volume (16h) ..................................................................................34
7.6.4.7. PCM Out Mixer Volume (18h) ...........................................................................34
7.6.5. Record Select (1Ah) ...........................................................................................................34
7.6.6. Record Gain (1Ch) .............................................................................................................35
7.6.7. General Purpose (20h) .......................................................................................................35
7.6.8. 3D Control (22h) .................................................................................................................36
7.6.9. Powerdown Ctrl/Stat (26h) .................................................................................................36
7.6.9.1. Ready Status ....................................................................................................37
7.6.9.2. Powerdown Controls .........................................................................................37
7.6.9.3. External Amplifier Power Down Control ............................................................37
7.6.10. Extended Audio ID (28h) ..................................................................................................37
7.6.11. Extended Audio Control/Status (2Ah) ..............................................................................38
7.6.11.1. Variable Rate Sampling Enable ......................................................................38
7.6.11.2. SPDIF .............................................................................................................39
7.6.11.3. SPCV (SPDIF Configuration Valid) .................................................................39
7.6.11.4. SPSA1, SPSA0 (SPDIF Slot Assignment) ......................................................39
7.6.12. PCM DAC Rate Registers (2Ch and 32h) ........................................................................39
7.6.12.1. PCM DAC Rate (2Ch) .....................................................................................40
7.6.12.2. PCM LR ADC Rate (32h) ................................................................................40
7.6.13. Z_DATA Volume (60h) .....................................................................................................40
7.6.14. Digital Audio Control (6Ah) ...............................................................................................41
7.6.14.1. SPDIF Control (3Ah) .......................................................................................42
7.6.15. Revision Code (6Ch) ........................................................................................................42
7.6.16. Analog Special (6Eh) .......................................................................................................43
7.6.16.1. 72h Enable (70h) ............................................................................................43
7.6.16.2. Analog Current Adjust (72h) ...........................................................................43
7.6.16.3. Internal Power-On/Off Anti-Pop Circuit ...........................................................44
7.6.17. Multi-Channel Selection (74h) ..........................................................................................44
4
2-9756-D1-3.3-0303
STAC9756/57
Two Channel AC'97 Codecs with I
2
S Digital I/O and SPDIF Output
7.6.17.1. Digital Audio Slot Selection .............................................................................45
7.6.18. Clock Access (Index 76h and 78h) ..................................................................................46
7.6.18.1. 78h Enable (76h) ............................................................................................46
7.6.18.2. Clock Access (78h) .........................................................................................46
7.6.19. Vendor ID1 and ID2 (Index 7Ch and 7Eh) .......................................................................47
7.6.19.1. Vendor ID1 (7Ch) ............................................................................................47
7.6.19.2. Vendor ID2 9756 (7Eh) ...................................................................................47
8. LOW POWER MODES ............................................................................................................48
9. MULTIPLE CODEC SUPPORT ...............................................................................................50
9.1. Primary/Secondary Codec Selection ...............................................................................................50
9.1.1. Primary Codec Operation ...................................................................................................50
9.1.2. Secondary Codec Operation ..............................................................................................50
9.2. Secondary Codec Register Access Definitions ................................................................................51
10. TESTABILITY ........................................................................................................................ 52
11. PIN DESCRIPTION ................................................................................................................ 53
11.1. Digital I/O .......................................................................................................................................54
11.2. Analog I/O ......................................................................................................................................55
11.3. Filter/References ............................................................................................................................55
11.4. Power and Ground Signals ............................................................................................................56
12. PACKAGE DRAWING .......................................................................................................... 57
13. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION .............................. 58
14. APPENDIX C: PROGRAMMING REGISTERS .....................................................................59
1.1.
List of Figures
Figure 1. STAC9756/57 Block Diagram ...........................................................................................................8
Figure 2. Cold Reset Timing ..........................................................................................................................13
Figure 3. Warm Reset Timing ........................................................................................................................13
Figure 4. Clocks Timing .................................................................................................................................14
Figure 5. Data Setup and Hold Timing ...........................................................................................................14
Figure 6. Signal Rise and Fall Times Timing ..................................................................................................15
Figure 7. AC-Link Low Power Mode Timing ...................................................................................................15
Figure 8. ATE Test Mode Timing ...................................................................................................................16
Figure 9. STAC9757 Typical Connection Diagram ........................................................................................17
Figure 10. AC-Link to its Companion Controller .............................................................................................18
Figure 11. AC'97 Standard Bi-directional Audio Frame .................................................................................20
Figure 12. AC-Link Audio Output Frame ........................................................................................................20
Figure 13. Start of an Audio Output Frame ....................................................................................................20
Figure 14. STAC9756/57 Audio Input Frame .................................................................................................23
Figure 15. Start of an Audio Input Frame .......................................................................................................24
Figure 16. STAC9756/57 Powerdown Timing ................................................................................................25
Figure 17. I
2
S Digital Audio Interface .............................................................................................................26
Figure 18. STAC9756 5V Analog Mode, 2-Channel Mixer Functional Diagram ............................................28
Figure 19. STAC9756 +3.3V Analog Mode and STAC9757 2-Channel Mixer Functional Diagram ...............28
Figure 20. Example of STAC9756/57 Powerdown/Powerup flow ..................................................................48
Figure 21. STAC9756/57 Powerdown/Powerup flow with analog still alive ...................................................49
Figure 22. STAC9756/57 Pin Description Drawing ........................................................................................53
Figure 23. 48-Pin TQFP Package Drawing ....................................................................................................57
Figure 24. STAC9756 Split Independent Power Supply Operation Typical Connection Diagram .................58
2-9756-D1-3.3-0303
5
STAC9756/57
Two Channel AC'97 Codecs with I
2
S Digital I/O and SPDIF Output
1.2.
List of Tables
Table 1. Recommended Operating Conditions ................................................................................................9
Table 2. Power Consumption ...........................................................................................................................9
Table 3. AC-Link Static Specifications ...........................................................................................................10
Table 4. STAC9756 Analog Performance Characteristics .............................................................................10
Table 5. STAC9757 Analog Performance Characteristics .............................................................................11
Table 6. Cold Reset Specifications ................................................................................................................13
Table 7. Warm Reset Specifications ..............................................................................................................13
Table 8. Clocks Specifications .......................................................................................................................14
Table 9. Data Setup and Hold Specifications .................................................................................................14
Table 10. Signal Rise and Fall Times Specifications .....................................................................................15
Table 11. AC-Link Low Power Mode Timing Specifications ...........................................................................15
Table 12. ATE Test Mode Specifications .......................................................................................................16
Table 13. STAC9756/57 Available Data Streams ..........................................................................................19
Table 14. Command Address Port Bit Assignments ......................................................................................21
Table 15. Command Data Port Bit Assignments ............................................................................................21
Table 16. Status Address Port Bit Assignments .............................................................................................24
Table 17. Status Data Port Bit Assignments ..................................................................................................25
Table 18. STAC9756/57 Mixer .......................................................................................................................27
Table 19. Programming Registers ..................................................................................................................30
Table 20. Play Master Volume Register .........................................................................................................31
Table 21. PC_BEEP Register ........................................................................................................................32
Table 22. Analog Mixer Input Gain Register ..................................................................................................33
Table 23. Record Select Control Registers ....................................................................................................34
Table 24. Record Gain Registers ..................................................................................................................35
Table 25. General Purpose Register ..............................................................................................................35
Table 26. 3D Control Registers .....................................................................................................................36
Table 27. Powerdown Status Registers .........................................................................................................36
Table 28. Extended Audio ID Register Functions .........................................................................................38
Table 29. Slot assignment relationship between SPSA1 and SPSA0 ............................................................39
Table 30. Hardware Supported Sample Rates ...............................................................................................39
Table 31. Z_Data Register .............................................................................................................................40
Table 32. Digital Audio Control (6Ah) Registers .............................................................................................41
Table 33. Digital Output Source Selection Table ...........................................................................................41
Table 34. SPDIF Control (3Ah) Registers ......................................................................................................42
Table 35. Analog Current Adjust ....................................................................................................................44
Table 36. STAC9756/57 Multi-Channel Programming Register .....................................................................44
Table 37. SPDIF Slot Selection (Reg. 2Ah: D5, D4 with Reg. 6Ah: D12 (I2S SEL) = 0) ...............................45
Table 38. I
2
S OUT2 Slot Selection (Reg. 2Ah: D5, D4 with Reg. 6Ah: D12 (I2S SEL) = 1) ..........................45
Table 39. I
2
S OUT1 Slot Selection (Reg. 6Ah: D5, D4) .................................................................................45
Table 40. SPDIF Control (3Ah) Registers ......................................................................................................46
Table 41. Low Power Modes ..........................................................................................................................48
Table 42. Codec ID Selection ........................................................................................................................50
Table 43. Secondary Codec Register Access Slot 0 Bit Definitions ...............................................................51
Table 44. Digital Connection Signals .............................................................................................................54
Table 45. Analog Connection Signals ............................................................................................................55
Table 46. Filtering and Voltage References ...................................................................................................55
Table 47. Power and Ground Signals ............................................................................................................56
Table 48. 48-Pin TQFP Package Dimensions ................................................................................................57
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