Rev. 2.2

_30

Seiko Instruments Inc.

The S-24C0XA is a series of 2-wired, low power 1K/2K/4K-bit EEPROMs
with a wide operating range. They are organized as 128-word

× 8-bit,

256-word

× 8-bit, and 512-word × 8-bit, respectively. Each is capable of

page write, and sequential read.
The time for byte write and page write is the same, i. e., 1 msec. (max.)
during operation at 5 V

± 10%.

Package

8-pin DIP (PKG drawing code : DP008-A,DP008-C)
8-pin SOP (PKG drawing code : FJ008-D,FJ008-E)

Pin Assignment

Figure 1

Pin Functions

Pin Number

Name

DIP

SOP

Function

Address input (no connection in the S-24C04A*)

Address input

GND

Ground

SDA

Serial data input/output

SCL

Serial clock input

TEST/WP

TEST pin (S-24C01A): Connected to GND.
WP (Write Protection) pin (S-24C02A, S-24C04A):
* Connected to Vcc:

Protection valid

* Connected to GND: Protection invalid

VCC

Power supply

CMOS 2-WIRE SERIAL EEPROM

S-24C01A/02A/04A

Endurance:

cycles/word

Data retention:

10 years

Write protection:

S-24C02A, S-24C04A

S-24C01A:

1 kbits

S-24C02A:

2 kbits

S-24C04A:

4 kbits

Features

Low power consumption

Standby: 1.0

A Max.

=5.5 V)

Operating: 0.4 mA Max.

=5.5 V)

0.3 mA Max.

=3.3 V)

Wide operating voltage range

Write:

2.5 to 5.5 V

Read:

1.8 to 5.5 V

Page write

8 bytes (S-24C01A, S-24C02A)
16 bytes (S-24C04A)

8-pin DIP

Top view

VCC

GND

SCL

SDA

TEST/WP

8-pin SOP

Top view

A0
A1

GND

6
5

8
7

3
4

1
2

TEST/WP

VCC

SCL
SDA

S-24C01ADPx-uu
S-24C02ADPx-uu
S-24C04ADPx-uu

S-24C01AFJA-zz-uuw
S-24C02AFJA-zz-uuw
S-24C04AFJA-zz-uuw

* Lower-case letters x, uu, zz and w differ

depending on the packing form.
See Ordering Information and Dimensions.

* When in use, connect to

GND or Vcc.

Table 1

CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

Block Diagram

Absolute Maximum Ratings

Parameter

Symbol

Ratings

Unit

Power supply voltage

-0.3 to +7.0

Input voltage

-0.3 to V

+0.3

Output voltage

OUT

-0.3 to V

Storage temperature under bias

bias

-50 to +95

°C

Storage temperature

stg

-65 to +150

°C

Figure 2

GND

Serial Clock

Controller

Device Address

Comparator

Address

Counter

Y Decoder

Data Output
ACK Output

Controller

High-Voltage Generator

Start/Stop

Detector

Data Register

EEPROM

Decoder

Selector

SCL
SDA

OUT

R / W

LOAD

INC

COMP

LOAD

TEST/WP*

S-24C02A or S-24C04A

Table 2

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

Recommended Operating Conditions

Table 3

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Read Operation

1.8

5.5

Power supply voltage

Write Operation

2.5

5.5

=2.5 to 5.5V

0.7

×V

High level input voltage

=1.8 to 2.5V

0.8

×V

=2.5 to 5.5V

0.0

0.3

×V

Low level input voltage

=1.8 to 2.5V

0.0

0.2

×V

Operating temperature

opr

-40

+85

°C

Pin Capacitance

Table 4

(Ta=25°C, f=1.0 MHz, V

=5 V)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Input capacitance

=0 V (SCL, A0, A1, A2, WP)

Input/output capacitance

I / O

=0 V (SDA)

Endurance

Table 5

Parameter

Symbol

Min.

Typ.

Max.

Unit

Endurance

cycles/word

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

DC Electrical Characteristics

Table 6

=4.5 V to 5.5

=2.5 to 4.5

=1.8 to 2.5 V

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Current consumption
(READ)

CC1

f=100 kHz

0.4

0.3

0.2

Current consumption
(PROGRAM)

CC2

f=100 kHz

2.0

1.5

Table 7

=4.5 V to 5.5 V

=2.5 to 4.5 V

=1.8 to 2.5 V

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Standby current

consumption

or GND

1.0

0.6

0.4

µA

Input leakage

current

=GND to V

0.1

1.0

0.1

1.0

0.1

1.0

µA

Output leakage

current

OUT

=GND to V

0.1

1.0

0.1

1.0

0.1

1.0

µA

=3.2 mA

0.4

=1.5 mA

0.3

0.5

Low level output

voltage

=100

µA

0.1

Current address

retention voltage

1.5

5.5

1.5

4.5

1.5

2.5

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

AC Electrical Characteristics

Table 9

=1.8V to 5.5V

Parameter

Symbol

Min.

Typ.

Max.

Unit

SCL clock frequency

SCL

100

kHz

SCL clock time "L"

LOW

4.7

µs

SCL clock time"H"

HIGH

4.0

µs

SDA output delay time

0.3

3.5

µs

SDA output hold time

0.3

µs

Start condition setup time

SU.STA

4.7

µs

Start condition hold time

HD.STA

4.0

µs

Data input setup time

SU.DAT

Data input hold time

HD.DAT

Stop condition setup time

SU.STO

4.7

µs

SCL

SDA rising time

1.0

µs

SCL

SDA falling time

0.3

µs

Bus release time

BUF

4.7

µs

Noise suppression time

100

Input pulse voltage

0.1

×V

to 0.9

×V

Input pulse rising/falling time

20 ns

Output judgment voltage

0.5

×V

Output load

100 pF+ Pullup resistance 1.0 k

Table 8

Measurement Conditions

R=1.0k

SDA

C=100pF

Figure 3

Output Load Circuit

Figure 4

Bus Timing

SCL

SDA IN

SDA OUT

BUF

SU.STO

SU.DAT

HD.DAT

HIGH

LOW

HD.STA

SU.STA

invalid

valid

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

Table 10

=4.5 to 5.5V

=2.5 to 4.5V

Item

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Write time

0.8

1.0

4.0

5.0

Pin Functions

1. Address Input Pins (A0, A1, and A2)

Connect pins A0, A1, and A2 to the GND or the V

, respectively, to assign slave addresses. There are 8

different ways to assign slave addresses in the S-24C01A and S-24C02A through a combination of pins
A0, A1, and A2, and 4 ways to assign them in the S-24C04A through a combination of pins A1 and A2.
When the input slave address coincides with the slave address transmitted from the master device, 1
device can be selected from among multiple devices connected to the bus. Always connect the address
input pin to GND or V

and leave it unchanged.

2. SDA (Serial Data Input/Output) Pin

The SDA pin is used for bilateral transmission of serial data. It consists of a signal input pin and an Nch
open-drain transistor output pin.
Usually pull up the SDA line via resistance to the V

, and use it with other open-drain or open-collector

output devices connected in a wired OR configuration.

3. SCL (Serial Clock Input) Pin

The SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling edges
of the SCL clock input signal. Make sure the rising time and falling time conform to the specifications.

4. TEST/WP Pin

The S-24C01A does not have a write protection (WP) function. The pin serves as a TEST pin and shoud
always be connect to the GND.
In the S-24C02A and S-24C04A, this pin is used for write protection. When there is no need for write
protection, connect the pin to the GND; when there is a need for write protection, connect the pin to the
Vcc.

Figure 5

Write Cycle

SCL

SDA

Write data

Acknowledge

Stop
condition

Start
condition

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

Operation

1. Start Condition

When the SCL line is "H," the SDA line changes from "H" to "L." This allows the device to go to the start
condition.
All operations begin from the start condition.

2. Stop Condition

When the SCL line is "H," the SDA line changes from "L" to "H." This allows the device to go to the stop
condition.
When the device receives the stop condition signal during a read sequence, the read operation is
interrupted, and the device goes to standby mode.
When the device receives the stop condition signal during write sequence, the retrieval of write data is
halted, and the EEPROM initiates rewrite

3. Data Transmission

Changing the SDA line while the SCL line is "L" allows the data to be transmitted. A start or stop condition
is recognized when the SDA line changes while the SCL line is "H."

Figure 6

Start/Stop Conditions

SU.STA

HD.STA

SU.STO

Start
Condition

Stop
Condition

SCL

SDA

Figure 7

Data Transmission Timing

SU.DAT

HD.DAT

SCL

SDA

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

4. Acknowledgment

The unit of data transmission is 8 bits. By turning the SDA line "L," the slave device mounted on the

system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal
verifying the data reception.
When the EEPROM is rewriting, the device does not output the acknowledgment signal.

5. Device Addressing

To perform data communications, the master device mounted on the system outputs the start condition
signal to the slave device.

Next, the master device outputs 7-bit length device address and a 1-bit length

read/write instruction code onto the SDA bus.

Upper 4 bits of the device address are called the "Device Code," and set to "1010." Successive 3 bits are called the
"Slave Address." It is used to select a device on the system bus, and compared to the predetermined address value
at the address input pin (A2, A1, or A0).
When the comparison results match, the slave device outputs the acknowledgment signal during the 9th clock
cycle

In the S-24C04A, "A0" does not exist in the slave addresses. So, "A0" becomes "P0." "P0" is a page address bit and
is equivalent to an additional uppermost bit of the word address. Accordingly, when P0="0," the former half area
corresponding to 2 kbits (addresses from 000h to 0FFh) in the entire memory are selected; when P0="1," the latter
half area corresponding to 2 kbits (addresses from 100h to 1FFh) in all areas of the memory are selected.

Figure 8

Acknowledgment Output Timing

Acknow-
ledgment
Output

Start
Condition

SCL

(EEPROM Input)

SDA

(Master Output)

SDA

(EEPROM Output)

Figure 9

Device Address

Slave Address

R/W

Device Code

S-24C01A

S-24C02A

MSB

LSB

R/W

S-24C04A

MSB

LSB

Device Code

Slave
Address

Page
Address

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

6. Write

6.1 Byte Write

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code

"0," following the start condition signal, it outputs the acknowledgment signal. Next, when the
EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal.
After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives the
stop condition signal. Next, the EEPROM at the specified memory address starts to rewrite.

When the EEPROM is rewriting, all operations are prohibited and the acknowledgment signal is not

output.

6.2 Page Write

Up to 8 bytes per page can be written in the S-24C01A and S-24C02A.

Up to 16 bytes per page can be written in the S-24C04A.

Basic data transmission procedures are the same as those in the "Byte Write." However, when the

EEPROM receives 8-bit write data which corresponds to the page size, the page can be written.

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code

"0," following the start condition signal, it outputs the acknowledgment signal. When the EEPROM
receives an 8-bit length word address, it outputs the acknowledgment signal.

After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives 8-
bit write data corresponding to the next word address, and outputs the acknowledgment signal. The
EEPROM repeats reception of 8-bit write data and output of the acknowledgment signal in
succession. It is capable of receiving write data corresponding to the maximum page size.

When the EEPROM receives the stop condition signal, it starts to rewrite, corresponding to the size

of the page, on which write data, starting from the specified memory address, is received.

Figure 10

Byte Write

S
T
A
R
T

1 0 1 0

T
E

S
T

DEVICE

ADDRES

WORD ADDRESS

DATA

S
B

SDA

ADR INC (ADDRESS INCREMENT)

A2 A1 A0

W7W6W5W4W3W2W1W0

D7 D6 D5 D4 D3 D2 D1 D0

A
C
K

S
B

A
C
K

W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

S
T
A
R
T

1 0 1 0

T
E

S
T

DEVICE

ADDRES

WORD ADDRESS (n)

DATA (n)

S
B

SDA LINE

ADR INC

A2 A1A0

W7W6W5W4W3W2W1W0

D7 D6 D5 D4 D3 D2 D1 D0

A
C
K

S
B

A
C
K

ADR INC

A
C
K

ADR INC

A
C
K

DATA (n+1)

DATA (n+x)

W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.

In the S-24C01A or S-24C02A, the lower 3 bits of the word address are automatically incremented

each when the EEPROM receives 8-bit write data.
Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the
lower 3 bits are rolled over and overwritten.

In the S-24C04A, the lower 4 bits at the word address are automatically incremented each when the

EEPROM receives 8 bit write data.
Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address
P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.

6.3 Acknowledgment Polling

Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.

After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are
prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device.
Accordingly, the master device transmits the start condition signal and the device address read/write
instruction code to the EEPROM (namely, the slave device) to detect the response of the slave
device. This allows users to know when the rewriting of the EEPROM is finished.

That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is

rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting
has been completed. It is recommended to use read instruction "1" for the read/write instruction
code transmitted by the master device.

6.4 Write Protection

The S-24C02A and the S-24C04A are capable of protecting the memory. When the WP pin is

connected to V

, writing to 50% of the latter half of all memory area (080h to 0FFh in the S-24C02A;

100h to 1FFh in the S-24C04A) is prohibited. Even when writing is prohibited, since the controller
inside the IC is operating, the response to the signal transmitted by the master device is not available
during the time of writing (t

When the WP pin is connected to GND, the write protection becomes invalid, and writing in all
memory area becomes available. However, when there is no need for using write protection, always
connect the WP pin to GND.

Figure 11

Page Write

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

Read

7.1 Current Address Read

The EEPROM is capable of storing the last accessed memory address during both writing and

reading. The memory address is stored as long as the power voltage is more than the retention
voltage V

Accordingly, when the master device recognizes the position of the address pointer inside the
EEPROM, data can be read from the memory address of the current address pointer without
assigning a word address. This is called "Current Address Read."

"Current Address Read" is explained for when the address counter inside the EEPROM is an "n"

address.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal. However, in the S-
24C04A, page address P0 becomes invalid, and the memory address of the current address pointer
becomes valid.
Next, 8-bit length data at an "n" address is output from the EEPROM, in synchronization with the
SCL clock.
The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data
is output, and the address counter goes to address n+1.

The master device does not output the acknowledgment signal and transmits the stop condition

signal to finish reading.

For recognition of the address pointer inside the EEPROM, take into consideration the following:

The memory address counter inside the EEPROM is automatically incremented for every falling
edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the
time of writing, upper bits of the memory address (upper 5 bits of the word address in the S-24C01A
and S-24C02A; upper 4 bits of the word address and page address P0 in the S-24C04A) are left
unchanged and are not incremented.

Figure 12 Current Address Read

S
T
A
R
T

1 0 1 0

R
E
A
D

S
T

DEVICE

ADDRESS

S
B

SDA LINE

ADR INC

A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

A
C
K

S
B

DATA

NO ACK from

Master

Device

(A0 is P0 in the S-24C04A)

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

7.2 Random Read

Random read is a mode used when the data is read from arbitrary memory addresses.
To load a memory address into the address counter inside the EEPROM, first perform a dummy write
according to the following procedures:

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0,"
following the start condition signal, it outputs the acknowledgment signal.

Next, the EEPROM receives an 8-bit length word address and outputs the acknowledgment signal. Last,
the memory address is loaded into the address counter of the EEPROM.
the EEPROM receives the write data during byte or page writing. However, data reception is not
performed during dummy write.

The memory address is loaded into the memory address counter inside the EEPROM during dummy write.
After that, the master device can read the data starting from the arbitrary memory address by transmitting
a new start condition signal and performing the same operation as that in the "Current Read."

That is, when the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal.
Next, 8-bit length data is output from the EEPROM, in synchronization with the SCL clock. The master
device does not output an acknowledgment signal and transmits the stop condition signal to finish reading.

S
T
A
R
T

0 1 0

S
T

DEVICE

ADDRESS

WORD ADDRESS (n)

S
B

SDA LINE

A2 A1 A0

W7W6W5W4W3W2W1W0

C
K

S
B

C
K

0 1 0 A2 A1 A0 1

D7 D6 D5 D4 D3 D2 D1 D0

DATA (n)

DUMMY WRITE

DEVICE

ADDRESS

R
E
A
D

NO ACK from

Master Device

ADR INC

S
T
A
R
T

W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.

Figure 13 Random Read

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

7.3 Sequential Read

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in
both current and random read operations, following the start condition signal, it outputs the
acknowledgment signal
When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory
address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by
which the 8th data is output.
When the master device transmits the acknowledgment signal, the next memory address data is output.

When the master device transmits the acknowledgment signal, the memory address counter inside the
EEPROM is incremented and read data in succession. This is called "Sequential Read."
When the master device does not output an acknowledgement signal and transmits the stop condition
signal, the read operation is finished.
Data can be read in the "Sequential Read" mode in succession. When the memory address counter
reaches the last word address, it rolls over to the first memory address.

Figure 14 Sequential Read

R
E
A
D

S
T

DEVICE

ADDRES

ADR INC

A
C
K

ADR INC

A
C
K

ADR INC

SDA LINE

DATA (n)

DATA (n+1)

DATA (n+2)

DATA (n+x)

NO ACK from

Master Device

ADR INC

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

8. Address Increment Timing

The address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory
address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is
output).

During writing operation, the memory address counter is also automatically incremented at the falling
edge of the SCL clock when the 8th bit write data is fetched.

Figure 15 Address Increment Timing During Reading

SCL

SDA

R / W=1

Address Increment

D7 Output

D0 Output

ACK Output

Figure 16 Address Increment Timing During Writing

SCL

SDA

R / W=0

D7 Input

D0 Input

ACK Output

Address Increment

Purchase of I

C components of Seiko Instruments Inc. conveys a license under the Philips I

Patent Rights to use these components in an I

C system, provided that the system conforms to the

C Standard Specification as defined by Philips.

Please note that any product or system incorporating this IC may infringe upon the Philips I

C Bus

Patent Rights depending upon its configuration.
In the event that such product or system incorporating the I

C Bus infringes upon the Philips Patent

Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and
arising from such patent infringement.

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

Ordering Information

S-24C0xA yyy - zz - uuw

P code (Distincion for package process)

None
S
1A

Endurance code

: 10

cycles

Taping specification

None for DIP and SOP in magazine
TB

Package code

: DIP

DPA

: DIP

FJA

: SOP

Product name

S-24C01A : 1k bits
S-24C02A : 2k bits
S-24C04A : 4k bits

Ordering names for DIP

Product name

Package code

Taping specification

Endurance

code

P code

Package/Tape/Reel

drawings

None

-1A

DP008-C

S-24C01A
S-24C02A
S-24C04A

DPA

None

-11

None

DP008-A

Note

The endurarance of S-24C0xADP-1A

is 10

cycles, though the ordering name does not have the endurance code.

Ordering names for SOP

Product name

Package code

Taping specification

Endurance

code

P code

Package/Tape/Reel

drawings

S-24C01A

FJA

-TB

(None for magazine)

-11

None

FJ008-D

None

FJ008-D

S-24C02A

FJA

-TB

(None for magazine)

-11

FJ008-D
FJ008-E

S-24C04A

FJA

-TB

(None for magazine)

-11

None

FJ008-D

Note

Package dimensions of SOPs whose package code is FJA are the same in the range of deviation.

Please contact an SII local office or a local representative for details.

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

Characteristics

1. DC Characteristics

1.1 Current consumption (READ) I

CC1

Ambient temperature Ta

1.2 Current consumption (READ) I

CC1

Ambient temperature Ta

1.3 Current consumption (READ) I

CC1

Ambient temperature Ta

1.4 Current consumption (READ) I

CC1

Power supply voltage V

1.5 Current consumption (READ) I

CC1

Power supply voltage V

1.6 Current consumption (READ) I

CC1

Clock frequency

fscl

1.7 Current consumption (PROGRAM) I

CC2

Ambient temperature Ta

1.8 Current consumption (PROGRAM) I

CC2

Ambient temperature Ta

Ta (°C)

200

100

=5.5 V

fscl=100 KHz
DATA=0101

-40

CC1

(

µA)

Ta (°C)

200

100

=3.3 V

fscl=100 KHz
DATA=0101

-40

CC1

(

µA)

Ta (°C)

=1.8 V

fscl=100 KHz
DATA=0101

-40

CC1

(

µA)

100

2 3 4

5 6

Ta=25°C
fscl=100 KHz
DATA=0101

(V)

CC1

(

µA)

100

2 3 4 5 6

Ta=25°C
fscl=400 KHz
DATA=0101

(V)

100

CC1

(

µA)

=5.0 V

Ta=25°C

100K 200K

fscl(Hz)

CC1

(

µA)

300K 400K

Ta (°C)

1.0

0.5

=5.5 V

-40

CC2

(mA)

Ta (°C)

1.0

0.5

=3.3 V

-40

CC2

(mA)

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

1.10 Current consumption (PROGRAM) I

CC2

Power supply voltage V

1.11 Standby current consumption I

Ambient temperature Ta

1.12 Input leakage current I

Ambient temperature Ta

1.13 Input leakage current I

Ambient temperature Ta

1.14 Output leakage current I

Ambient temperature Ta

1.15 Output leakage current I

Ambient temperature Ta

1.9 Current consumption (PROGRAM) I

CC2

Ambient temperature Ta

Ta (°C)

1.0

0.5

=2.5 V

-40

CC2

(mA)

1.0

0.5

2 3 4 5 6

Ta=25°C

(V)

CC2

(mA)

-6

-7

-8

-9

-10

=5.5 V

-11

Ta (°C)

-40

Ta (°C)

1.0

0.5

=5.5 V

A0, A1, A2, SDA
SCL,TEST/WP=0V

-40

(

µA)

(A)

Ta (°C)

1.0

0.5

=5.5 V

SDA=0V

-40

(

µA)

Ta (°C)

1.0

0.5

-40

=5.5 V

A0, A1, A2, SDA
SCL, TEST/WP=5.5V

(

µA)

Ta (°C)

1.0

0.5

=5.5 V

SDA=5.5 V

-40

(

µA)

CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2

_30

Seiko Instruments Inc.

1.20 High input inversion voltage VIH

Power supply voltageV

1.16 Low level output voltage V

Ambient temperature Ta

1.17 Low level output voltage V

Ambient temperature Ta

1.18 Low level output current I

Ambient temperature Ta

1.19 Low level output current I

Ambient temperature Ta

1.21 High input inversion voltage VIH

Ambient temperature Ta

1.22 Low input inversion voltage VIL

Power supply voltageV

1.23 Low input inversion voltage VIL

Ambient temperature Ta

Ta (°C)

0.3

0.2

=4.5 V

=2.3 mA

-40

(V)

0.1

Ta (°C)

0.03

0.02

=1.8 V

=100

-40

(V)

0.01

Ta (°C)

=4.5 V

=0.45 V

-40

(mA)

Ta (°C)

1.0

0.5

=1.8 V

=0.1 V

-40

(mA)

Ta=25°C

A0, A1, A2, SDA
SCL, TEST/WP

1.0

2.0

3.0

VIH

(V)

1 2 3 4 5 6 7

(V)

=5.0 V

A0, A1, A2, SDA
SCL, TEST/WP

1.0

2.0

3.0

VIH

(V)

Ta (°C)

-40

Ta=25°C

A0, A1, A2, SDA
SCL, TEST/WP

1.0

2.0

3.0

VIL

(V)

1 2 3 4 5 6 7

(V)

1.0

2.0

3.0

VIL

(V)

Ta (°C)

-40

Ta=5.0V

A0, A1, A2, SDA
SCL, TEST/WP

CMOS 2-WIRE SERIAL EEPROM

Rev. 2.2

_30

S-24C01A/02A/04A

Seiko Instruments Inc.

2. AC Characteristics

2.1

Maximum operating frequency fmax

Power supply voltage V

2.2 Write time t

Power supply voltage V

2.3 Write time t

Ambient temperature Ta

2.4 Write time t

Ambient temperature Ta

2.5 SDA output delay time t

Ambient temperature Ta

2.6 SDA output delay time t

Ambient temperature Ta

2.7 Data output delay time t

Ambient temperature Ta

10K

2 3 4

Ta=25°C

(V)

max

(Hz)

2 3 4 5 6

Ta=25°C

(V)

(ms)

100K

Ta (

1.5

1.0

=4.5 V

-40

0.5

(ms)

Ta (°C)

=2.5 V

-40

(ms)

Ta (°C)

1.5

1.0

=4.5 V

-40

0.5

(

µs)

Ta (°C)

1.5

1.0

=2.7 V

-40

0.5

(

µs)

Ta (°C)

3.0

2.0

=1.8 V

-40

1.0

(

µs)

The information described herein is subject to change without notice.

Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.

When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.

Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.

The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.

Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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