Document Outline
- S-24CS64A
- Cover
- Features
- Packages
- Pin Assignments
- Block diagram
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Pin Capacitance
- Endurance
- DC Electrical Characteristics
- AC Electrical Characteristics
- Pin Functions
- Operation
- Write inhibition function at low power voltage
- Using S-24CS64A
- Precautions
- I2C Bus License
- Typical Characteristics
- Product Code Structure
- Package drawing
- 8-Pin SOP (JEDEC)
- 8-Pin TSSOP
- WLP-8C
Rev.2.0
_00
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Seiko Instruments Inc.
1
The S-24CS64A is a 2-wired, low power and wide
range operation 64 K-bit E
2
PROM organized as 8192
words
8 bits.
Page write and sequential read are available.
Features
Low power consumption Standby : 5.0 A Max. (V
CC
=5.5 V)
Read :
0.8 mA Max. (V
CC
=5.5 V)
Operating voltage range Read :
1.8 to 5.5 V
Write :
2.7 to 5.5 V
Page write :
32 bytes / page
Sequential read
Operating Frequency :
400 kHz (V
CC
=5 V
10 %)
Write disable function when power supply voltage is low
Endurance:
10
6
cycles/word (at +25C) write capable,
10
5
cycles/word (at +85C)
Data retention:
10 years (after rewriting 10
5
cycles/word at +85C)
Write protection :
100 %
Packages
Package name
Drawing code
Package
Tape Reel
8-Pin SOP (JEDEC)
FJ008-A
FJ008-D
FJ008-D
8-Pin
TSSOP
FT008-A FT008-E FT008-E
WLP-8C
HC008-A HC008-A HC008-A
Caution This product is intended to use in general electronic devices such as consumer electronics,
office equipment, and communications devices. Before using the product in medical
equipment or automobile equipment including car audio, keyless entry and engine control
unit, contact to SII is indispensable.
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
2
Pin Assignments
8-Pin SOP (JEDEC)
Top view
Table 1
Pin
Number
Pin
Name
Function
1
A0
Slave address input
2
A1
Slave address input
3
A2
Slave address input
4 GND
Ground
5
SDA
Serial data input / output
6
SCL
Serial clock input
7 WP
Write protection input
Connected to V
CC
: Protection
valid
Connected to GND: Protection invalid
8 VCC
Power supply
Remark See Dimensions for details of the package drawings.
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
GND
A2
Figure 1
S-24CS64A0I-J8T1
8-Pin TSSOP
Top view
Table 2
Pin
Number
Pin
Name
Function
1
A0
Slave address input
2
A1
Slave address input
3
A2
Slave address input
4 GND
Ground
5
SDA
Serial data input / output
6
SCL
Serial clock input
7 WP
Write protection input
Connected to V
CC
: Protection
valid
Connected to GND: Protection invalid
8 VCC
Power supply
Remark See Dimensions for details of the package drawings.
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
GND
A2
Figure 2
S-24CS64A0I-T8T1
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
3
WLP-8C
Bottom view
Table 3
Pin
Number
Pin
Name
Function
1
A0
Slave address input
2 VCC
Power
supply
3 WP
Write protection input
Connected to V
CC
: Protection
valid
Connected to GND: Protection invalid
4
SCL
Serial clock input
5
SDA
Serial data input / output
6 GND
Ground
7
A2
Slave address input
8
A1
Slave address input
Remark See Dimensions for details of the package drawings.
VCC WP
SCL
SDA
GND
1
5
2
3
4
6
A0
(1.94
1.970.6 max.)
A1
A2
7
8
Figure 3
S-24CS64A0I-H8T1
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
4
Block diagram
VCC
GND
Serial Clock
Controller
Device Address
Comparator
Address
Counter
Y Decoder
Data Output
ACK Output
Controller
Start / Stop
Detector
Data Register
E
2
PROM
X Decoder
Selector
High-Voltage Generator
SCL
SDA
A2
D
IN
D
OUT
R / W
LOAD
INC
COMP
LOAD
WP
A1
A0
Voltage Detector
Figure 4
Absolute Maximum Ratings
Table 4
Parameter Symbol
Ratings
Unit
Power supply voltage
V
CC
-0.3 to +7.0 V
Input voltage
V
IN
-0.3 to V
CC
+0.3 V
Output voltage
V
OUT
-0.3 to V
CC
V
Storage temperature
T
stg
-65 to +150 C
Caution The absolute maximum ratings are rated values exceeding which the
product could suffer physical damage. These values must therefore not be
exceeded under any conditions.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
5
Recommended Operating Conditions
Table 5
Parameter Symbol
Conditions Min.
Typ.
Max.
Unit
Power supply voltage
V
CC
Read
Operation
1.8
5.5 V
Write
Operation
2.7
5.5 V
High level input voltage
V
IH
V
CC
=2.5 to 5.5 V
0.7
V
CC
V
CC
V
V
CC
=1.8 to 2.5 V
0.8
V
CC
V
CC
V
Low level input voltage
V
IL
V
CC
=2.5 to 5.5 V
0.0
0.3V
CC
V
V
CC
=1.8 to 2.5 V
0.0
0.2
V
CC
V
Operating temperature
T
opr
-40
+85
C
Pin Capacitance
Table 6
(Ta
=25C, f=1.0 MHz, V
CC
=5 V)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
C
IN
V
IN
=0 V (SCL, A0, A1, A2, WP)
--
--
10
pF
Input/output capacitance
C
I / O
V
I / O
=0 V (SDA)
--
--
10
pF
Endurance
Table 7
Parameter Symbol
Operation
temperature Min. Typ. Max.
Unit
Endurance N
W
-40 to +85C 10
5
--
--
cycles / word
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
6
DC Electrical Characteristics
Table 8
Parameter Symbol
Conditions
V
CC
=4.5 to 5.5 V
f = 400 kHz
V
CC
=2.7 to 4.5 V
f = 100 kHz
V
CC
=1.8 to 2.7 V
f = 100 kHz
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Current consumption
(READ)
I
CC1
0.8
0.5
0.3
mA
Current consumption
(WRITE)
I
CC2
4.0
3.0
mA
Table 9
Parameter
Symbol
Conditions
V
CC
=4.5 to 5.5 V
V
CC
=1.8 to 4.5 V
Unit
Min. Typ. Max. Min. Typ. Max.
Standby current consumption
I
SB
V
IN
=V
CC
or GND
5.0
3.0
A
Input leakage current
I
LI
V
IN
=GND to V
CC
0.1 1.0
0.1 1.0
A
Output leakage current
I
LO
V
OUT
=GND to V
CC
0.1 1.0
0.1 1.0
A
Low level output voltage
V
OL
I
OL
=3.2 mA
0.4
V
I
OL
=1.5 mA
0.3
0.3 V
Current address hold voltage
V
AH
1.5
5.5 1.5
4.5 V
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
7
AC Electrical Characteristics
Table 10 Measurement Conditions
Input pulse voltage
0.1
V
CC
to 0.9
V
CC
Input pulse rising / falling time
20 ns
Output judgment voltage
0.5
V
CC
Output load
100 pF
+ Pullup resistance 1.0 k
V
CC
R=1.0 k
SDA
C=100 pF
Figure 5 Output Load Circuit
Table 11
Parameter Symbol
V
CC
=4.5 to 5.5 V
V
CC
=1.8 to 4.5 V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL clock frequency
f
SCL
0
400 0
100 kHz
SCL clock time "L"
t
LOW
1.0
4.7
s
SCL clock time"H"
t
HIGH
0.9
4.0
s
SDA output delay time
t
AA
0.1
0.9 0.1
3.5
s
SDA output hold time
t
DH
50
100
ns
Start condition setup time
t
SU.STA
0.6
4.7
s
Start condition hold time
t
HD.STA
0.6
4.0
s
Data input setup time
t
SU.DAT
100
200
ns
Data input hold time
t
HD.DAT
0
0
ns
Stop condition setup time
t
SU.STO
0.6
4.7
s
SCL SDA rising time
t
R
0.3
1.0
s
SCL SDA falling time
t
F
0.3
0.3
s
Bus release time
t
BUF
1.3
4.7
s
Noise suppression time
t
I
50
100 ns
SCL
SDA IN
SDA OUT
t
BUF
t
R
t
SU.STO
t
SU.DAT
t
HD.DAT
t
DH
t
AA
t
HIGH
t
LOW
t
HD.STA
t
SU.STA
t
F
Figure 6 Bus Timing
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
8
Table 12
Parameter Symbol V
CC
=2.7 to 5.5 V
Unit
Min.
Typ.
Max.
Write time
t
WR
--
6.0
10.0
ms
SCL
SDA
D0
Write data
Acknowledge
Stop Condition
Start Condition
t
WR
Figure 7 Write Cycle Timing
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
9
Pin Functions
1. Address Input Pins (A0, A1 and A2)
The slave address is assigned by connecting pins A0, A1 and A2 to the GND or to the V
CC
respectively.
One of the eight different slave address can be assigned by the combination of pins A0, A1 and A2.
The given slave address, which is compared with the slave address transmitted from the master device, is
used to select the one among the multiple devices connected to the bus. The address input pin should be
connected to the GND or to the V
CC
.
2. SDA (Serial Data Input / Output) Pin
The SDA pin is used for bi-directional transmission of serial data. It consists of a signal input pin and an
Nch open-drain output pin.
The SDA line is usually pulled up to the V
CC
, and OR-wired with other open-drain or open-collector output
devices.
3. SCL (Serial Clock Input) Pin
The SCL pin is used for serial clock input. Since signals are processed at the rising or falling edge of the
SCL clock input signal, attention should be paid to the rising time and falling time to conform to the
specifications.
4. WP Pin
The write protection is enabled by connecting the WP pin to the V
CC
. When there is no need for write
protection, connect the pin to the GND.
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
10
Operation
1. Start Condition
Start is identified by a high to low transition of the SDA line while the SCL line is stable at high.
Every operation begins from a start condition.
2. Stop Condition
Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high.
When a device receives a stop condition during a read sequence, the read operation is interrupted, and the
device enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is halted,
and the E
2
PROM initiates a write cycle.
t
SU.STA
t
HD.STA
t
SU.STO
Start Condition
Stop Condition
SCL
SDA
Figure 8 Start / Stop Conditions
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
11
3. Data Transmission
Changing the SDA line while the SCL line is low, data is transmitted.
Changing the SDA line while the SCL line is high, a start or stop condition is recognized.
t
SU.DAT
t
HD.DAT
SCL
SDA
Figure 9 Data Transmission Timing
4. Acknowledge
The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down
the SDA line to acknowledge the receipt of the 8-bit data.
When a internal write cycle is in progress, the device does not generate an acknowledge.
1
8
9
Acknowledge
Output
t
AA
t
DH
Start Condition
SCL
(E
2
PROM Input)
SDA
(Master Output)
SDA
(E
2
PROM Output)
Figure 10 Acknowledge Output Timing
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
12
5. Device Addressing
To start communication, the master device on the system generates a start condition to the bus line. Next,
the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The 4 most significant bits of the device address are called the "Device Code", and are fixed to "1010".
Successive 3 bits are called the "Slave Address". These 3 bits are used to identify a device on the system
bus and are compared with the predetermined value which is defined by the address input pins (A0, A1 and
A2). When the comparison result matches, the slave device responds with an acknowledge during the 9th
clock cycle.
Slave Address
1
0
1
0
A2
A1
A0
R/W
Device Code
LSB
MSB
Figure 11 Device Address
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
13
6. Write
6.1 Byte Write
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to "0", following
a start condition, the E
2
PROM acknowledges it. The E
2
PROM then receives the upper 8 bits of the word
address and responds with an acknowledge. And the E
2
PROM receives the lower 8 bits of the word
address and responds with an acknowledge. After the E
2
PROM receives 8-bit write data and responds
with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed
memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
A2
A1
A0
S
T
A
R
T
1
0
1
0
W
R
I
T
E
DEVICE
ADDRESS
UPPER WORD ADDRESS
R
/
W
M
S
B
SDA LINE
ADR INC
(ADDRESS INCREMENT)
A
C
K
L
S
B
LOWER WORD ADDRESS
A
C
K
A
C
K
0
S
T
O
P
DATA
X
X
X
W7
W6
W5
W4
W3
W2
W1
W0
D7
D6
D5
D4
D3
D2
D1
D0
A
C
K
A
C
K
W12
W11
W10
W9
W8
Figure 12 Byte Write
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
14
6.2 Page Write
The page write mode allows up to 32 bytes to be written in a single wire operation in the S-24CS64A.
Basic data transmission procedure is the same as that in the "Byte Write". However, when the E
2
PROM
receives 8-bit write data which corresponds to the page size, the page can be written.
When the E
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to "0",
following a start condition, it generates an acknowledge. Then the E
2
PROM receives the upper 8 bits of
the word address and responds with an acknowledge. And the E
2
PROM receives the lower 8 bits of the
word address and responds with an acknowledge. After the E
2
PROM receives 8-bit write data and
responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and
generates an acknowledge. The E
2
PROM repeats reception of 8-bit write data and generation of
acknowledge in succession. The E
2
PROM can receive as many write data as the maximum page size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory address
and having the page size equal to the received write data.
S
T
A
R
T
1
0
1
0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRESS
LOWER WORD ADDRESS (n)
UPPER WORD ADDRESS (n)
R
/
W
M
S
B
SDA
LINE
A2
A1
A0
A
C
K
L
S
B
A
C
K
A
C
K
0
X
X
X
W12
D7
D0
ADR INC
A
C
K
ADR INC
A
C
K
DATA (n)
DATA (n+x)
W11
W10
W9
W7
W5
W4
W3
W2
W1
W0
W6
W8
D7
D0
Figure 13 Page Write
The lower 5 bits of the word address are automatically incremented every time when the E
2
PROM
receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 8 bits of the word
address remain unchanged, and the lower 5 bits are rolled over and previously received data will be
overwritten.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
15
6.3 Acknowledge Polling
Acknowledge polling is used to know the completion of the write cycle in the E
2
PROM.
After the E
2
PROM receives a stop condition and once starts the write cycle, all operations are forbidden
and no response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in the E
2
PROM by detecting
a response from the slave device after transmitting the start condition, the device address and the
read/write instruction code to the E
2
PROM, namely to the slave devices.
That is, if the E
2
PROM does not generate an acknowledge, the write cycle is in progress and if the
E
2
PROM generates an acknowledge, the write cycle has been completed.
It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the
master device.
6.4 Write Protection
Write protection is available in the S-24CS64A. When the WP pin is connected to the V
CC
, write operation
to memory area is forbidden at all.
When the WP pin is connected to the GND, the write protection is invalid, and write operation in all memory
area is available. There is no need for using write protection, the WP pin should be connected to the GND.
The write protection is valid in the operating voltage range.
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
16
7. Read
7.1 Current Address Read
Either in writing or in reading the E
2
PROM holds the last accessed memory address, internally
incremented by one. The memory address is maintained as long as the power voltage is higher than the
current address hold voltage V
AH
.
The master device can read the data at the memory address of the current address pointer without
assigning the word address as a result, when it recognizes the position of the address pointer in the
E
2
PROM. This is called "Current Address Read".
In the following the address counter in the E
2
PROM is assumed to be "n".
When the E
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to "1"
following a start condition, it responds with an acknowledge.
Next an 8-bit data at the address "n" is sent from the E
2
PROM synchronous to the SCL clock. The address
counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of the
address counter becomes n
+1.
The master device has to not acknowledge the 8-bit data and terminates the reading with a stop condition.
S
T
A
R
T
1 0 1 0
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
R
/
W
M
S
B
SDA LINE
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
ADR INC
1
DATA
NO ACK from
Master Device
Figure 14 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in the E
2
PROM.
In the read operation the memory address counter in the E
2
PROM is automatically incremented at every
falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the
upper 8 bits of the memory address are left unchanged and are not incremented at the falling edge of the
SCL clock for the 8th bit of the received data.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
17
7.2 Random Read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the E
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to "0"
following a start condition, it responds with an acknowledge. The E
2
PROM then receives an 8-bit upper
word address and responds with an acknowledge. Next the E
2
PROM then receives an 8-bit lower word
address and responds with an acknowledge. The memory address is loaded to the address counter in the
E
2
PROM by these operations. Reception of write data does not follow in a dummy write whereas reception
of write data follows in a byte write and in a page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device
can read the data starting from the arbitrary memory address by transmitting a new start condition and
performing the same operation in the current address read.
That is, when the E
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to
"1", following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from
the E
2
PROM in synchronous to the SCL clock. The master device has to not acknowledge and terminates
the reading with a stop condition.
SDA
LINE
S
T
A
R
T
1 0 1 0
W
R
I
T
E
DEVICE
ADDRESS
LOWER WORD ADDRESS
R
/
W
M
S
B
A2 A1 A0
A
C
K
L
S
B
W7
W6
W5
W4
W3
W2
W1
A
C
K
0
DUMMY WRITE
S
T
O
P
S
T
A
R
T
1 0 1 0
R
E
A
D
DEVICE
ADDRESS
R
/
W
M
S
B
A2 A1 A0
A
C
K
L
S
B
1
?????
NO ACK from
Master Device
ADR INC
DATA
UPPER WORD ADDRESS
X
W9
W8
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
W12
W11
W10
W0
Figure 15 Random Read
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
18
7.3 Sequential Read
When the E
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to "1"
following a start condition both in current and random read operations, it responds with an acknowledge.
An 8-bit data is then sent from the E
2
PROM synchronous to the SCL clock and the address counter is
automatically incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowledge, the data at the next memory address is
transmitted. Response with an acknowledge by the master device has the memory address counter in the
E
2
PROM incremented and makes it possible to read data in succession. This is called "Sequential Read".
The master device has not acknowledge and terminates the reading with a stop condition.
Data can be read in succession in the sequential read mode. When the memory address counter reaches
the last word address, it rolls over to the first memory address.
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
R
/
W
ADR INC
A
C
K
A
C
K
A
C
K
1
ADR INC
A
C
K
ADR INC
SDA
LINE
DATA(n)
D7
D0
D7
D0
D7
D0
D7
D0
DATA (n+1)
DATA (n+2)
DATA (n+x)
NO ACK from
Master Device
ADR INC
Figure 16 Sequential Read
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
19
8. Address Increment Timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the
read data in read operation and the the falling edge of the SCL clock for the 8th bit of the received data in
write operation.
SCL
SDA
R / W=1
Address Increment
8
9
1
8
9
D7 Output
D0 Output
ACK Output
Figure 17 Address Increment Timing in Reading
SCL
SDA
R / W=0
8
9
1
8
9
D7 Input
D0 Input
ACK Output
ACK Output
Address Increment
Figure 18 Address Increment Timing in Writing
Write inhibition function at low power voltage
The S-24CS64A have a detection circuit for low power voltage. The detection circuit cancels a write
instruction when the power voltage is low or the power switch is on. The detection voltage is 1.85 V typically
and the release voltage is 1.95 V typically, the hysteresis of approximate 0.1 V thus exists. (See Figure 19.)
When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.
When the power voltage lowers during a data transmission or a write operation, the date at the address of
the operation is not assured.
Power supply voltage
Write Instruction
cancel
Release voltage (+V
DET
)
1.95 V typ.
Detection voltage (-V
DET
)
1.85 V typ.
Hysteresis width
0.1 V approximately
Figure 19 Operation at low power voltage
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
20
Using S-24CS64A
1. Adding a pull-up resistor to SDA I/O pin and SCL input pin
Add a 1 k
to 5 k pull-up resistor to the SCL input pin
*1
and the SDA I/O pin in order to enable the
functions of the I
2
C Bus protocol. Normal communication cannot be provided without a pull-up resistor.
*1. When the SCL input pin of the E
2
PROM is connected to a tri-state output pin of the microprocessor,
connect the same pull-up resistor to prevent a high impedance status from being input to the SCL input
pin.
This protects the E
2
PROM from malfunction due to an undefined output (high impedance) from the tri-
state pin when the microprocessor is reset when the voltage drops.
2. I/O pin equivalent circuit
The I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output.
The following shows the equivalent circuits.
SCL
Figure 20 SCL Pin
SDA
Figure 21 SDA Pin
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
21
WP
Figure 22 WP Pin
A0, A1, A2
Figure 23 A0, A1, A2 Pin
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
22
3. Matching phases while E
2
PROM is accessed
The S-24CS64A does not have a pin for resetting (the internal circuit), therefore, the E
2
PROM cannot be
forcibly reset externally. If a communication interruption occurs in the E
2
PROM, it must be reset by
software.
For example, even if a reset signal is input to the microprocessor, the internal circuit of the E
2
PROM is not
reset as long as the stop condition is not input to the E
2
PROM. In other words, the E
2
PROM retains the
same status and cannot shift to the next operation. This symptom applies to the case when only the
microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage
is restored, reset the E
2
PROM (after matching the phase with the microprocessor) and input an instruction.
The following shows this reset method.
[How to reset E
2
PROM]
The E
2
PROM can be reset by the start and stop instructions. When the E
2
PROM is reading data "0" or
is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor
cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation
or read operation, and then input a start instruction. Figure 24 shows this procedure.
First, input the condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the
microprocessor sets the SDA line to high level. By this operation, the E
2
PROM interrupts the
acknowledge output operation or data output, so input the start condition
*1
. When a start condition is
input, the E
2
PROM is reset. To make doubly sure, input the stop condition to the E
2
PROM. Normal
operation is then possible.
1
2
8
9
SCL
SDA
Start
condition
Stop
condition
Start
condition
Dummy clock
Figure 24 Resetting E
2
PROM
*1. After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition being
input, a write operation may be started upon receipt of a stop condition. To prevent this, input a start
condition after 9 clocks (dummy clocks).
Remark It is recommended to perform the above reset using dummy clocks when the system is
initialized after the power supply voltage has been raised.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
23
4. Acknowledge check
The I
2
C Bus protocol includes an acknowledge check function as a handshake function to prevent a
communication error. This function allows detection of a communication failure during data communication
between the microprocessor and E
2
PROM. This function is effective to prevent malfunction, so it is
recommended to perform an acknowledge check on the microprocessor side.
5. Built-in power-on-clear circuit
E
2
PROMs have a built-in power-on-clear circuit that initializes the E
2
PROM. Unsuccessful initialization may
cause a malfunction. For the power-on-clear circuit to operate normally, the following conditions must be
satisfied for raising the power supply voltage.
5.1 Raising power supply voltage
Raise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply
voltage to be used within the time defined by t
RISE
as shown in Figure 25.
For example, when the power supply voltage to be used is 5.0 V, t
RISE
is 200 ms as shown in Figure 26.
The power supply voltage must be raised within 200 ms.
0.2 V
V
INIT
(Max.)
t
INIT
*2
(Max.)
t
RISE
(Max.)
Power supply voltage (V
CC
)
0 V
*1
*1. 0 V means there is no difference in potential between the V
CC
pin and the
GND pin of the E
2
PROM.
*2.
t
INIT
is the time required to initialize the E
2
PROM. No instructions
are accepted during this time.
Figure 25 Raising Power Supply Voltage
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
24
Rise time (t
RISE
) Max.
[ms]
Power supply voltage
(V
CC
)
[V]
50
5.0
4.0
3.0
2.0
100 150 200
For example:
If your E
2
PROM supply voltage = 5.0 V, raise the power supply
voltage to 5.0 V within 200 ms.
Figure 26 Raising Time of Power Supply Voltage
When initialization is successfully completed via the power-on-clear circuit, the E
2
PROM enters the
standby status.
If the power-on-clear circuit does not operate, the following are the possible causes.
(1) Because the E
2
PROM has not been initialized, an instruction formerly input is valid or an instruction
may be inappropriately recognized. In this case, writing may be performed.
(2) The voltage may have dropped due to power off while the E
2
PROM is being accessed. Even if the
microprocessor is reset due to the low power voltage, the E
2
PROM may malfunction unless the
power-on-clear operation conditions of E
2
PROM are satisfied. For the power-on-clear operation
conditions of E
2
PROM, refer to 5.1 Raising power supply voltage.
If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E
2
PROM circuit
is normally reset. The statuses of the E
2
PROM immediately after the power-on-clear circuit operates and
when phase is matched (reset) are the same.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
25
5.2 Wait for the initialization sequence to end
The E
2
PROM executes initialization during the time that the supply voltage is increasing to its normal
value. All instructions must wait until after initialization. The relationship between the initialization time
(t
INIT
) and rise time (t
RISE
) is shown in Figure 27.
Rise time (t
RISE
)
[s]
E
2
PROM initialization
time (t
INIT
) Max.
[s]
100 m
10 m
1.0 m
100
10
1.0
1.0
10 100
1.0 m 10 m 100 m
Figure 27 Initialization Time of E
2
PROM
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
26
6. Data hold time (t
HD, DAT
=
=
=
= 0 ns)
If SCL and SDA of the E
2
PROM are changed at the same time, it is necessary to prevent the start/stop
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E
2
PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3
s maximum in the S-24CS64A.
This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.
SCL
SDA
t
HD, DAT
= 0.3
s Max.
Figure 28 E
2
PROM Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-24CS64A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means
that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
The guaranteed for details, refer to noise suppression time (t
I
) in Table 11.
Noise suppression time (t
I
) Max.
[ns]
200
100
300
2 3 4 5
Power supply voltage (V
CC
)
[V]
Figure 29 Noise Suppression Time for SDA and SCL Pins
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
27
8. Trap: E
2
PROM operation in case that the stop condition is received during write operation before
receiving the defined data value (less than 8-bit) to SCL pin
When the E
2
PROM receives the stop condition signal compulsorily, during receiving 1 byte of write data,
"write" operation is aborted.
When the E
2
PROM receives the stop condition signal after receiving 1 byte or more of data for "page write",
8-bit of data received normally before receiving the stop condition signal can be written.
9. Trap: E
2
PROM operation and write data in case that write data is input more than defined page size at
"page write"
When write data is input more than defined page size at page write operation, for example, S-24CS64A
(which can be executed 32-byte page write) is received data more than 33 byte, 8-bit data of the 33rd byte
is over written to the first byte in the same page. Data over the capacity of page address cannot be written.
10. Trap: Severe environments
Absolute maximum ratings: Do not operate these ICs in excess of the absolute max ratings, as listed on
the data sheet. Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the E
2
PROM pins may occur malfunction by short-circuit between pins.
Especially, in occasions like picking the E
2
PROM up from low temperature tank during the evaluation. Be
sure that not remain frost on E
2
PROM pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
28
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
Precautions for WLP package
The side of device silicon substrate is exposed to the marking side of device package. Since this portion
has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc
should be careful of the handing of a package enough. Moreover, the exposed side of silicon has electrical
potential of device substrate, and needs to be kept out of contact with the external potential.
In this package, the overcoat of the resin of translucence is carried out on the side of transistor area. Keep
it mind that it may affect the characteristic of a package when exposed a device in the bottom of a high
light source.
I
2
C Bus License
Purchase of I
2
C components of Seiko Instruments Inc., conveys a license under the Philips I
2
C Patent.
Rights to use these components in an I
2
C system, is granted provided that the system conforms to the I
2
C
Standard Specification as defined by Philips.
Please note that a product or a system incorporating this IC may infringe upon the Philips I
2
C Patent Rights
depending upon its configuration. In the event of such infringement Seiko Instruments Inc., shall not bear
any responsibility for any matters with regard to and arising from such patent infringement.
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
29
Typical Characteristics
1. DC Characteristics
1.1 Current consumption (READ) I
CC1
1.2 Current consumption (READ) I
CC1
Ambient temperature Ta
Ambient temperature Ta
V
CC
=5.5 V
f
SCL
=100 kHz
DATA
=0101
40 0
85
300
100
200
0
I
CC1
(
A)
Ta (
C)
Ta (
C)
V
CC
=3.3 V
f
SCL
=100 kHz
DATA
=0101
40 0
85
300
100
200
0
I
CC1
(
A)
1.3 Current consumption (READ) I
CC1
1.4 Current consumption (READ) I
CC1
Ambient temperature Ta
Power supply voltage V
CC
V
CC
=1.8 V
f
SCL
=100 kHz
DATA
=0101
300
100
200
0
I
CC1
(
A)
Ta (
C)
40 0
85
Ta
=25C
f
SCL
=100 kHz
DATA
=0101
2 3 4 5 6 7
V
CC
(V)
300
100
200
0
I
CC1
(
A)
1.5 Current consumption (READ) I
CC1
1.6 Current consumption (READ) I
CC1
Power supply voltage V
CC
Clock frequency f
SCL
Ta
=25C
f
SCL
=400 kHz
DATA
=0101
2 3 4 5 6 7
V
CC
(V)
500
200
400
0
I
CC1
(
A)
300
100
V
CC
=5.0 V
Ta
=25C
100k
f
SCL
(Hz)
400k 1M
I
CC1
(
A)
500
200
400
300
100
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
30
1.7 Current consumption (PROGRAM) I
CC2
1.8 Current consumption (PROGRAM) I
CC2
Ambient temperature Ta
Ambient temperature Ta
V
CC
=5.5 V
Ta (
C)
40 0
85
1.0
0.5
0
I
CC2
(mA)
1.5
V
CC
=3.3 V
Ta (
C)
40 0
85
I
CC2
(mA) 1.0
0.5
0
1.5
1.9 Current consumption (PROGRAM) I
CC2
1.10 Current consumption (PROGRAM) I
CC2
Ambient temperature Ta
Power supply voltage V
CC
V
CC
=2.7 V
I
CC2
(mA)
Ta (
C)
40 0
85
1.0
0.5
0
1.5
Ta
=25C
V
CC
(V)
I
CC2
(mA)
2
1
3 4 5 6
1.0
0.5
0
1.5
1.11 Standby current consumption I
SB
1.12 Input leakage current I
LI
Ambient temperature Ta
Ambient temperature Ta
2.0
1.0
V
CC
=5.5 V
0
I
SB
(
A)
Ta (
C)
40 0
85
1.0
0.5
0
I
LI
(
A)
Ta (
C)
40 0
85
V
CC
=5.5 V
SDA, SCL, WP
=0 V
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
31
1.13 Input leakage current I
LI
1.14 Output leakage current I
LO
Ambient temperature Ta
Ambient temperature Ta
1.0
0.5
V
CC
=5.5 V
0
I
LI
(
A)
Ta (
C)
40 0
85
SDA, SCL, WP
=5.5 V
1.0
0.5
V
CC
=5.5 V
SDA
=0 V
0
I
LO
(
A)
Ta (
C)
40
0
85
1.15 Output leakage current I
LO
1.16 Low level output voltage V
OL
Ambient temperature Ta
Low level output current I
OL
1.0
0.5
V
CC
=5.5 V
SDA
=5.5 V
0
I
LO
(
A)
Ta (
C)
40 0
85
0.3
0.2
V
OL
(V)
0.1
0
2
1 3
4
5
6
Ta
=-40C
I
OL
(mA)
V
CC
=1.8 V
V
CC
=5.0 V
1.17 Low level output voltage V
OL
1.18 Low level output voltage V
OL
Low level output current I
OL
Low level output current I
OL
0.3
0.2
V
OL
(V)
0.1
0
2
1
3 4 5 6
Ta
=25C
I
OL
(mA)
V
CC
=1.8 V
V
CC
=5.0 V
0.3
0.2
V
OL
(V)
0.1
0
2
1 3
4
5
6
Ta
=85C
I
OL
(mA)
V
CC
=1.8 V
V
CC
= 5.0 V
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
32
1.19 High input inversion voltage V
IH
1.20 High input inversion voltage V
IH
Power supply voltage V
CC
Ambient temperature Ta
Ta
=25C
SDA, SCL
1.0
0
2.0
3.0
V
IH
(V)
V
CC
(V)
7
6
2 3 4 5
1
V
CC
=5.0 V
SDA, SCL
1.0
0
2.0
3.0
V
IH
(V)
Ta (
C)
40 0
85
1.21 Low input inversion voltage V
IL
1.22 Low input inversion voltage V
IL
Power supply voltage V
CC
Ambient temperature Ta
1.0
0
2.0
3.0
V
IL
(V)
V
CC
(V)
7
6
2 3 4 5
1
Ta
=25C
SDA, SCL
1.0
0
2.0
3.0
V
IL
(V)
Ta (C)
40 0
85
V
CC
=5.0 V
SDA, SCL
1.23 Low power supply detection voltage
-V
DET
1.24 Low power supply release voltage
+V
DET
Ambient temperature Ta
Ambient temperature Ta
1.0
0
2.0
-V
DET
(V)
Ta (C)
40 0
85
1.0
0
2.0
+V
DET
(V)
Ta (C)
40 0
85
2-WIRE CMOS SERIAL E
2
PROM
Rev.2.0
_00
S-24CS64A
Seiko Instruments Inc.
33
2. AC Characteristics
2.1 Maximum operating frequency f
max.
2.2 Write time t
WR
Power supply voltage V
CC
Power supply voltage V
CC
10k
2 3 4 5
Ta
=25C
V
CC
(V)
fmax.
(Hz)
1
100k
1M
V
CC
(V)
8
4
Ta
=25C
t
WR
(ms)
2
6
0
6
2 3 4 5
1
2.3 Write time t
WR
Ambient temperature Ta
2.4 Write time t
WR
Ambient temperature Ta
V
CC
=4.5 V
t
WR
(ms)
9
6
3
0
Ta (
C)
40 0
85
V
CC
=2.7 V
t
WR
(ms)
9
6
3
0
Ta (
C)
40 0
85
2.5 SDA output delay time t
AA
2.6 SDA output delay time t
AA
Ambient temperature Ta
Ambient temperature Ta
Ta (
C)
40 0
85
V
CC
=4.5 V
1.0
0.5
t
AA
(
s)
0
Ta (
C)
40 0
85
V
CC
=2.7 V
1.0
0.5
t
AA
(
s)
0
2-WIRE CMOS SERIAL E
2
PROM
S-24CS64A
Rev.2.0
_00
Seiko Instruments Inc.
34
2.7 SDA output delay time t
AA
Ambient temperature Ta
Ta(
C)
40 0
85
V
CC
=1.8 V
1.0
0.5
t
AA
(
s)
0
Product Code Structure
S-24CS64A 0I - xxxx
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
H8T1: WLP-8C, Tape
Fixed
Product name
S-24CS64A: 64 K-bit
No. FJ008-A-P-SD-2.1
0.40.05
1.27
0.200.05
5.020.2
1
4
8
5
No.
TITLE
SCALE
UNIT
mm
SOP8J-A-PKG Dimensions
Seiko Instruments Inc.
FJ008-A-P-SD-2.1
No.
TITLE
SCALE
UNIT
mm
5
8
1
4
2.00.05
1.550.05
0.30.05
2.10.1
8.00.1
5max.
6.70.1
2.00.05
Seiko Instruments Inc.
Feed direction
4.00.1(10 pitches:40.00.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
TITLE
SCALE
UNIT
mm
QTY.
2,000
20.5
13.50.5
60
20.5
130.2
210.8
Seiko Instruments Inc.
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
0.170.05
3.00
+0.3
-0.2
0.65
0.20.1
1
4
5
8
TSSOP8-A-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
1.550.05
2.00.05
8.00.1
1.55
+0.1
-0.05
(4.4)
0.30.05
1
4
5
8
4.00.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
20.5
130.5
210.8
13.41.0
17.51.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
0.06 S
S
8-(0.3)
0.5
0.5
0.30.02
0.6max.
0
.
4
0
.
0
2
0
.
6
m
a
x
.
0.1
5
0.0
3
0.5
0.5
No.
TITLE
SCALE
UNIT
mm
No. HC008-A-P-SD-1.0
WLP-8C-A-PKG Dimensions
HC008-A-P-SD-1.0
Seiko Instruments Inc.
Pin No.
1
2
3
4
5
6
A0
VCC
WP
SCL
SDA
GND
Pin name
3
6
4
5
7
8
1
2
7
8
A2
A1
A
B
1
.
9
7
0
.
0
2
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
No. HC008-A-C-SD-1.0
2.0
3
0.0
5
0.640.05
0.180.05
Feed direction
8.0
0
.2
3.5
0
.05
1.7
5
0.1
2.00.05
4.00.1
1.5
+0.1
-0
1.050.05
0.
74
2.00.1
4.00.1
0.8
2.36
0.6
Count mark (0.8,Depth 0.2)
(Every 10 pockets)
1
3
4
5
2.
33
2.060.05
3.
0
HC008-A-C-SD-1.0
W L P - 8 C - A - C a r r i e r T a p e
0.22
2
6 7
8
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
No. HC008-A-R-SD-1.0
HC008-A-R-SD-1.0
W L P - 8 C - A - R e e l
QTY.
3,000
12.5max.
9.00.3
6
0
+1
-0
18
0
+0
-3
20
.5
130.2
21
0.
8
Enlarged drawing in the central part
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
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When the products described herein are regulated products subject to the Wassenaar Arrangement or other
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failure or malfunction of semiconductor products may occur. The user of these products should therefore
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