ChipFind - документация

Электронный компонент: S-24VC64A

Скачать:  PDF   ZIP
Rev.0.3
TENTATIVE
Seiko Instruments Inc.
1
S-24CV64A
CMOS 2-WIRED SERIAL EEPROM
The S-24CV64A is a 2-wired, low power and wide range operation 64k-bit
EEPROM organized as 8192 words
8 bits.
Page write and sequential read are available.
Wide package line up makes the S-24CV6A best for any application from
consumer electronics to communication devices.
Features
Low power consumption
Endurance:
10
5
cycles/word
Standby:
5.0
A Max. (V
CC
=5.5 V)
Data retention:
10 years
Read:
0.8 mA Max. (V
CC
=5.5 V)
Write protection area:
100 %
Operating voltage range
Read:
1.8 to 5.5 V
Write:
2.5 to 5.5 V
Page write
32 bytes/ page
Sequential read
Pin Assignment
8-pin DIP
Top view
VCC
GND
WP
SCL
A1
A2
SDA
A0
1
4
3
2
S-24CV64AFT
S-24CV64AFJ
S-24CV64ADP
5
8
7
6
A1
A0
8-pin SOP
Top view
VCC
SCL
SDA
A2
GND
6
5
8
7
3
4
1
2
WP
8-pin TSSOP
Top view
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
Figure 1
Pin Functions
Table 1
Name
Pin Number
Function
A0
1
Slave address input
A1
2
Slave address input
A2
3
Slave address input
GND
4
Ground
SDA
5
Serial data input/output
SCL
6
Serial clock input
WP
7
Write protection input
Connected to Vcc:
Protection valid
Connected to GND: Protection invalid
VCC
8
Power supply
This product is intended to use in general electronic devices such as consumer electronics, office equipment,
and communications devices. Before using the product in medical equipment or automobile equipment
including car audio, keyless entry and engine control unit, contact to SII is indispensable .
CMOS 2-WIRED SERIAL EEPROM
TENTATIVE
S-24CV64A Rev.0.3
2
Seiko Instruments Inc.
Block diagram
V
CC
GND
Serial Clock
Controller
Device Address
Comparator
Address
Counter
Y Decoder
Data Output
ACK Output
Controller
High-Voltage Generator
Start/Stop
Detector
Data Register
EEPROM
X
Decoder
Selector
SCL
SDA
A2
A1
A0
D
IN
D
OUT
R / W
LOAD
INC
COMP
LOAD
WP
Figure 2
Absolute Maximum Ratings
Table 2
Parameter
Symbol
Ratings
Unit
Power supply voltage
V
CC
-0.3 to +7.0
V
Input voltage
V
IN
-0.3 to V
CC
+0.3
V
Output voltage
V
OUT
-0.3 to V
CC
V
Storage temperature under bias
T
bias
-50 to +95
C
Storage temperature
T
stg
-65 to +150
C
Recommended Operating Conditions
Table 3
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Power supply voltage
V
CC
Read Operation
1.8
--
5.5
V
Write Operation
2.5
--
5.5
V
High level input voltage
V
IH
V
CC
=2.5 to 5.5V
0.7
V
CC
--
V
CC
V
V
CC
=1.8 to 2.5V
0.8
V
CC
--
V
CC
V
Low level input voltage
V
IL
V
CC
=2.5 to 5.5V
0.0
--
0.3
V
CC
V
V
CC
=1.8 to 2.5V
0.0
--
0.2
V
CC
V
Operating temperature
T
opr
--
-40
--
+85
C
TENTATIVE
CMOS 2-WIRED SERIAL EEPROM
Rev.0.3 S-24CV64A
Seiko Instruments Inc.
3
Pin Capacitance
Table 4
(Ta=25C, f=1.0 MHz, V
CC
=5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
C
IN
V
IN
=0 V (SCL, A0, A1, A2, WP)
--
--
10
pF
Input/output capacitance
C
I/O
V
I/O
=0 V (SDA)
--
--
10
pF
Endurance
Table 5
Parameter
Symbol
Min.
Typ.
Max.
Unit
Endurance
N
W
10
5
--
--
cycles/word
DC Electrical Characteristics
Table 6
V
CC
=4.5 V to 5.5 V
V
CC
=2.5 to 4.5 V
V
CC
=1.8 to 2.5 V
Parameter
Symbol
f=400 KHz
f=100 KHz
f=100 KHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Current consumption
(READ)
I
CC1
--
--
0.8
--
--
0.5
--
--
0.3
mA
Current consumption
(PROGRAM)
I
CC2
--
--
4.0
--
--
3.0
--
--
--
mA
Table 7
Parameter
Symbol
Conditions
V
CC
=4.5 V to 5.5 V
V
CC
=1.8 to 2.5 V
Unit
Min.
Typ.
Max.
Min. Typ.
Max.
Standby current consumption
I
SB
V
IN
=V
CC
or GND
--
--
5.0
--
--
3.0
A
Input leakage current
I
LI
V
IN
=GND to V
CC
--
0.1
1.0
--
0.1
1.0
A
Output leakage current
I
LO
V
OUT
=GND to V
CC
--
0.1
1.0
--
0.1
1.0
A
Low level output voltage
V
OL
I
OL
=3.2 mA
--
--
0.4
--
--
--
V
I
OL
=1.5 mA
--
--
0.3
--
--
0.3
V
Current address hold voltage
V
AH
I
OL
=100
A
1.5
--
5.5
1.5
--
4.5
V
CMOS 2-WIRED SERIAL EEPROM
TENTATIVE
S-24CV64A Rev.0.3
4
Seiko Instruments Inc.
AC Electrical Characteristics
Table 8 Measurement Conditions
Figure 3 Output Load Circuit
Table 9
Parameter
Symbol
V
CC
=4.5V to 5.5V
V
CC
=1.8V to 4.5V
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL clock frequency
f
SCL
0
--
400
0
--
100
kHz
SCL clock time "L"
t
LOW
1.0
--
--
4.7
--
--
s
SCL clock time"H"
t
HIGH
0.9
--
--
4.0
--
--
s
SDA output delay time
t
AA
0.1
--
0.9
0.3
--
3.5
s
SDA output hold time
t
DH
50
--
--
100
--
--
ns
Start condition setup time
t
SU.STA
0.6
--
--
4.7
--
--
s
Start condition hold time
t
HD.STA
0.6
--
--
4.0
--
--
s
Data input setup time
t
SU.DAT
100
--
--
200
--
--
s
Data input hold time
t
HD.DAT
0
--
--
0
--
--
s
Stop condition setup time
t
SU.STO
0.6
--
--
4.7
--
--
s
SCL SDA rising time
t
R
--
--
0.3
--
--
1.0
s
SCL SDA falling time
t
F
--
--
0.3
--
--
0.3
s
Bus release time
t
BUF
1.3
--
--
4.7
--
--
s
Noise suppression time
t
I
--
--
50
--
100
s
SCL
SDA IN
SDA OUT
t
BUF
t
R
t
SU.STO
t
SU.DAT
t
HD.DAT
t
DH
t
AA
t
HIGH
t
LOW
t
HD.STA
t
SU.STA
t
F
invalid
valid
Figure 4
Bus Timing
V
CC
R=1.0k
SDA
C=100pF
Input pulse voltage
0.1
V
CC
to 0.9
V
CC
Input pulse rising/falling time
20 ns
Output judgment voltage
0.5
V
CC
Output load
100 pF+ Pullup resistance 1.0 k
TENTATIVE
CMOS 2-WIRED SERIAL EEPROM
Rev.0.3 S-24CV64A
Seiko Instruments Inc.
5
Table 10
Item
Symbol
Min.
Typ.
Max
Unit
Write time
t
WR
-
7.0
10.0
ms
SCL
SDA
D0
Write data
Acknowledge
Stop
condition
Start
condition
t
WR
Figure 5 Write Cycle Timing
Pin Functions
1.
Address Input Pins (A0, A1, and A2)
Slave address is assigned by connecting pins A0, A1, and A2 to the GND or to the V
CC
, respectively.
One of the 8 different slave addresses can be assigned to the S-24CV64A by the combination of pins
A0, A1, and A2. The given slave address, which is compared with the slave address transmitted from
the master device, is used to select the one among the multiple devices connected to the bus. The
address input pins should be connected to the GND or to the V
CC
.
2.
SDA (Serial Data Input/Output) Pin
The SDA pin is used for bi-directional transmission of serial data. It consists of a signal input pin and an
Nch open-drain output pin.
The SDA line is usually pulled up to the V
CC
, and OR-wired with other open-drain or open-collector
output devices.
3.
SCL (Serial Clock Input) Pin
The SCL pin is used for serial clock input. Since signals are processed at the rising or falling edge of the
SCL clock input signal, attention should be paid to the rising time and falling time to conform to the
specifications.
4.
WP Pin
Write protection is enabled by connecting the WP pin to the V
CC
. When there is no need for write
protection, connect the pin to the GND.
CMOS 2-WIRED SERIAL EEPROM
TENTATIVE
S-24CV64A Rev.0.3
6
Seiko Instruments Inc.
Operation
1.
Start Condition
Start is identified by a high to low transition of the SDA line while the SCL line is stable at high.
Every operation begins from a start condition.
2.
Stop Condition
Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high.
When a device receives a stop condition during a read sequence, the read operation is interrupted, and
the device enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is
halted, and the EEPROM initiates a write cycle.
t
SU.STA
t
HD.STA
t
SU.STO
Start
Condition
Stop
Condition
SCL
SDA
Figure 6 Start/Stop Conditions
3.
Data Transmission
Changing the SDA line while the SCL line is low, data is transmitted.
Changing the SDA line while the SCL line is high, a start or stop condition is recognized.
t
SU.DAT
t
HD.DAT
SCL
SDA
Figure 7 Data Transmission Timing
4.
Acknowledge
The unit of data transmission is 8 bits. Uring the 9th clock cycle period the receiver on the bus pulls
down the SDA line to acknowledge the receipt of the 8-bit data.
When a internal write cycle is in progress, the device does not generate an acknowledge.
1
8
9
Acknow ledge
Output
t
AA
t
DH
Start
Condition
SCL
(EEPROM Input)
SDA
(Master Output)
SDA
(EEPROM Output)
Figure 8 Acknowledge Output Timing
TENTATIVE
CMOS 2-WIRED SERIAL EEPROM
Rev.0.3 S-24CV64A
Seiko Instruments Inc.
7
5.
Device Addressing
To start communication, the master device on the system generates a start condition to the bus line.
Next, the master device sends 7-bit device address and a 1-bit read/write instruction code onto the SDA
bus.
The 4 most significant bits of the device address are called the "Device Code," and are fixed to "1010."
Successive 3 bits are called the "Slave Address." These 3 bits are used to identify a device on the
system bus and are compared with the predetermined value which is defined by the address input pins
P0, P1 and P2. When the comparison result matches, the slave device reponds with an acknowledge
during the 9th clock cycle.
Slave Address
1
0
1
0
A2
A1
A0
R/W
Device Code
LSB
MSB
Figure 9 Device Address
6.
Write
6.1 Byte Write
When the master sends a 7-bit device address and a 1-bit read/write instruction code set to "0",
following a start condition, the EEPROM acknowledges it. The EEPROM then receives an 8-bit upper
word address and reponds with an aknowledge. Next the EEPROM receives an 8-bit lower word
address and reponds with an aknowledge.
After the EEPROM receives 8-bit write data and reponds with an aknowledge, it receives a stop
condition and that initiates the write cycle at the addressed memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
A2 A1 A0
S
T
A
R
T
1
0
1
0
W
R
I
T
E
DEVICE
ADDRESS
UPPER WORD ADDRESS
R
/
W
M
S
B
SDA LINE
ADR INC
(ADDRESS INCREMENT)
A
C
K
L
S
B
LOWER WORD ADDRESS
A
C
K
0
S
T
O
P
DATA
X
X
X
W12 W11W10W9 W8
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
A
C
K
Figure 10 Byte Write
6.2 Page Write
The page write mode allows up to 32 bytes to be written in a single write operation in the S-24CV64A.
Basic data transmission procedure is the same as that in the "Byte Write." But instead of generrating a
stop condition, the master transmitts 8-bit write data up to 32 bytes before the page write.
When the EEPROM receives a 7-bit device address and a 1-bit read/write instruction code set to "0",
following a start condition, it generates an acknowledge. Then the EEPROM receives an 8-bit upper
word address, and reponds with an aknowledge. Next the EEPROM receives an 8-bit lower word
address and reponds with an aknowledge. After the EEPROM receives 8-bit write data and reponds
with an aknowledge, it receives 8-bit write data corresponding to the next word address, and generates
an acknowledge. The EEPROM repeats reception of 8-bit write data and generation of acknowledge in
succession. The EEPROM can receive as many write data as the maximum page size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory
address and having the page size equal to the received write data.
CMOS 2-WIRED SERIAL EEPROM
TENTATIVE
S-24CV64A Rev.0.3
8
Seiko Instruments Inc.
S
T
A
R
T
1
0
1
0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRESS
ADDRESS (n)
LOWER WORD
ADDRESS (n)
UPPER WORD
R
/
W
M
S
B
SDA
LINE
A2 A1 A0
A
C
K
L
S
B
A
C
K
A
C
K
0
X
X
X
W12 W11W10 W9 W8
W7 W6 W5 W4 W3 W2 W1 W0
D7
D0
D7
D0
ADR INC
A
C
K
ADR INC
A
C
K
DATA (n)
DATA (n+x)
Figure 11 Page Write
The lower 5 bits of the word address are automatically incremented every time when the EEPROM
receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 8 bits of the word
address remain unchanged, and the lower 5 bits are rolled over and previously received data will be
overwritten.
6.3 Acknowledge Polling
Acknowledge polling is used to know the completion of the write cycle in the EEPROM.
After the EEPROM receives a stop condition and once starts the write cycle, all operations are forbidden
and no response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in the EEPROM by
detecting a response from the slave device after transmitting the start condition, the device address and
the read/write instruction code to the EEPROM, namely to the slave devices.
That is, if the EEPROM does not generate an acknowledge, the write cycle is in progress and if the
EEPROM generates an acknowledge, the write cycle has been completed.
It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the
master device.
6.4 Write Protection
Write protection is available in the S-24CV64A. When the WP pin is connected to V
CC
, write operation to
memory area is forbidden at all. Even the writing is forbidden, the EEPROM does not respond to a
signal transmitted by the master device during the time of writing (t
WR
), since the control circuit inside
the IC operates.
When the WP pin is connected to GND, the write protection is invalid, and write operation in all memory
area is available. There is no need for using write protection, the WP pin should be connected to GND.
The write protection is valid in the operating voltage range.
7.
Read
7.1 Current Address Read
Either in writing or in reading the EEPROM holds the last accessed memory address, internally
incremented by one. The memory address is maintained as long as the power voltage is higher than the
current address hold voltage V
AH
.
The master device can read the data at the memory address of the current address pointer without
assigning the word address as a result, when it recognizes the position of the address pointer in the
EEPROM. This is called "Current Address Read."
In the following the address counter in the EEPROM is assumed to be n.
When the EEPROM receives a 7-bit device address and a 1-bit read/write instruction code set to "1"
following a start condition, it responds with an acknowledge.
Next an 8-bit data at the address "n" is sent from the EEPROM synchronous to the SCL clock. The
address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content
of the address counter becomes n+1.
The master device has to not acknowledge the 8-bit data and terminates the reading with a stop
condition.
TENTATIVE
CMOS 2-WIRED SERIAL EEPROM
Rev.0.3 S-24CV64A
Seiko Instruments Inc.
9
S
T
A
R
T
1 0
1
0
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
R
/
W
M
S
B
SDA LINE
ADR INC
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
1
DATA
NO ACK from
Master Device
Figure 12 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in the EEPROM.
In the read operation the memory address counter in the EEPROM is automatically incremented at every
falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand,
the 8-bit upper address is left unchanged and is not incremented at the falling edge of the SCL clock for
the 8th bit of the received data.
7.2 Random Read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the EEPROM receives a 7-bit device address and a 1-bit read/write instruction code set to "0"
following a start condition, it reponds with an acknowledge. The EEPROM then receives an 8-bit upper
word address and reponds with an acknowledge. Next the EEPROM then receives an 8-bit lower word
address and reponds with an acknowledge. The memory address is loaded to the address counter in
the EEPROM by these operations. Reception of write data does not follow in a dummy write whereas
reception of write data follows in a byte write and in a page write.
Since the memory address is loaded into the memory address counter by dummy write, the master
device can read the data starting from the arbitrary memory address by transmitting a new start
condition and performing the same operation in the current address read.
That is, when the EEPROM receives a 7-bit device address and a 1-bit read/write instruction code set to
"1," following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted
from the EEPROM in synchronous to the SCL clock. The master device has to not acknowledge and
terminates the reading with a stop condition.
SDA
LINE
S
T
A
R
T
1
0
0
W
R
I
T
E
DEVICE
ADDRESS
UPPER WORD ADDRESS
R
/
W
M
S
B
A2 A1 A0
A
C
K
L
S
B
LOWER WORD ADDRESS
X
X
X
W12 W11 W10 W9 W8
W7 W6 W5 W4 W3 W2 W1 W0
A
C
K
0
DUMMY WRITE
S
T
A
R
T
1
0 1
0
R
E
A
D
DEVICE
ADDRESS
R
/
W
M
S
B
A2 A1 A0
A
C
K
L
S
B
1
NO ACK from
Master Device
ADR INC
DATA
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
Figure 13 Random Read
CMOS 2-WIRED SERIAL EEPROM
TENTATIVE
S-24CV64A Rev.0.3
10
Seiko Instruments Inc.
7.3 Sequential Read
When the EEPROM receives a 7-bit device address and a 1-bit read/write instruction code set to "1"
following a start condition both in current and random read operations, it responds with an acknowledge.
An 8-bit data is then sent from the EEPROM synchronous to the SCL clock and the address counter is
automatically incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowlidge, the data at the next memory address is
transmitted. Response with an acknowledge by the master device has the memory address counter in
the EEPROM incremented and makes it possible to read data in succession. This is called "Sequential
Read."
The master device has not acknowledge and terminates the reading with a stop condition.
Data can be read in succession in the sequential read mode. When the memory address counter
reaches the last word address, it rolls over to the first memory address.
R
E
A
D
S
T
O
P
DEVICE
ADDRES
R
/
W
ADR INC
A
C
K
A
C
K
A
C
K
1
ADR INC
A
C
K
ADR INC
SDA
LINE
DATA(n)
D7
D0
D7
D0
D7
D0
D7
D0
DATA (n+1)
DATA (n+2)
DATA (n+x)
NO ACK from
Master Device
ADR INC
Figure 14 Sequential Read
8.
Address Increment Timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the
read data in read operation and the the falling edge of the SCL clock for the 8th bit of the received data
in write operation. (See figures 15 and 16.)
Figure 15 Address Increment Timing in Reading
Figure 16 Address Increment Timing in Writing
SCL
SDA
R / W=1
Address Increment
8
9
1
8
9
D7 Output
D0 Output
ACK Output
SCL
SDA
R / W=0
8
9
1
8
9
D7 Input
D0 Input
ACK Output
ACK Output
Address Increment
TENTATIVE
CMOS 2-WIRED SERIAL EEPROM
Rev.0.3 S-24CV64A
Seiko Instruments Inc.
11
Precautions
Generally, an EEPROM may cause a malfunction by the operation in low voltage range induced by power
ON/OFF. The S-24CV16A initializes itself by the power on clear circuit at power on.
Attention should be paid to the followings so as to operate the power on clear circuit correctly, otherwise
malfunction may occur.
1.
All input and output pins should be connected to V
CC
or GND level so as not to be floating.
2.
Raise the power voltage up to the operation voltage from 0 V without staying at middle range.
3.
Raising speed of the power voltage should be faster than 40 ms/V.
4.
Power off interval before power on should be longer than 100 ms.
I
2
C Bus License
Purchase of I
2
C components of Seiko Instruments Inc., conveys a license under the Philips I
2
C Patent.
Rights to use these components in an I
2
C system, is granted provided that the system conforms to the I
2
C
Standard Specification as defined by Philips.
Please note that a product or a system incorporating this IC may infringe upon the Philips I
2
C Patent
Rights depending upon its configuration. In the event of such infringement Seiko Instruments Inc., shall
not bear any responsibility for any matters with regard to and arising from such patent infringement.