Электронный компонент: S-7600A

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Seiko Instruments Inc.

Hardware Specification

S-7600A

TCP/IP Network Stack LSI

Components Marketing Dept.
Marketing Section 2

Phone +81-43-211-1028
Fax +81-43-211-8035

8, Nakase 1-chome, Mihama-ku
Chiba-shi, Chiba 261-8507, Japan

S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

TABLE OF CONTENTS

INTRODUCTION........................................................................................................................... 1-1

1.1.

RODUCT

VERVIEW

............................................................................................................... 1-1

1.2.

EATURES

............................................................................................................................... 1-1

1.3.

ENEFITS

................................................................................................................................. 1-1

1.4.

RADEMARKS

........................................................................................................................... 1-2

1.5.

EFINITIONS

............................................................................................................................ 1-2

1.6.

PPLICABLE

OCUMENTS

......................................................................................................... 1-2

1.7.

AUTIONS

................................................................................................................................ 1-2

FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1

TERMINALS.................................................................................................................................. 3-1

3.1.

SSIGNMENT

...................................................................................................................... 3-1

3.2.

ACKAGE

IMENSIONS

............................................................................................................. 3-2

3.3.

ESCRIPTION

..................................................................................................................... 3-3

3.4.

ONFIGURATION

................................................................................................................ 3-4

ELECTRICAL CHARACTERISTICS............................................................................................. 4-1

4.1.

BSOLUTE

AXIMUM

ATINGS

.................................................................................................. 4-1

4.2.

ECOMMENDED

PERATING

ONDITIONS

................................................................................. 4-1

4.3.

DC C

HARACTERISTICS

............................................................................................................. 4-2

4.4.

OWER

URRENT

ONSUMPTION

............................................................................................. 4-2

MPU INTERFACE ......................................................................................................................... 5-1

5.1.

VERVIEW

............................................................................................................................... 5-1

5.2.

ARALLEL

NTERFACE

............................................................................................................... 5-1

5.2.1.

68k Family MPU Mode.................................................................................................... 5-2

5.2.1.1.

Write Cycle Timing ................................................................................................................5-2

5.2.1.2.

Read Cycle Timing ................................................................................................................5-3

5.2.2.

x80 Family MPU Mode.................................................................................................... 5-4

5.2.2.1.

Write Cycle Timing ................................................................................................................5-4

5.2.2.2.

Read Cycle Timing ................................................................................................................5-5

5.3.

ERIAL

NTERFACE

................................................................................................................... 5-6

5.3.1.

Write Cycle Timing.......................................................................................................... 5-6

5.3.2.

Read Cycle Timing.......................................................................................................... 5-7

5.4.

NTERRUPT

............................................................................................................................... 5-8

MEMORY REQUIREMENTS ........................................................................................................ 6-1

6.1.

VERVIEW

............................................................................................................................... 6-1

6.2.

EMORY

NTERFACE

RCHITECTURE

........................................................................................ 6-1

6.3.

EMORY

.......................................................................................................................... 6-2

S-7600A REGISTER DEFINITIONS ............................................................................................. 7-1

7.1.

VERVIEW

............................................................................................................................... 7-1

7.2.

API R

EGISTER

................................................................................................................. 7-1

7.3.

EGISTER

EFINITIONS

............................................................................................................ 7-4

7.3.1.

Revision Register (0x00)................................................................................................ 7-4

7.3.2.

General Control Register (0x01) .................................................................................... 7-4

7.3.3.

Generic Socket Location Register (0x02) ...................................................................... 7-5

7.3.4.

Master Interrupt (0x04) .................................................................................................. 7-5

7.3.5.

Serial Port Configuration / Status Register (0x08) ......................................................... 7-6

7.3.6.

Serial Port Interrupt Register (0x09) .............................................................................. 7-8

7.3.7.

Serial Port Interrupt Mask Register (0x0A) .................................................................... 7-8

7.3.8.

Serial Port Data Register (0x0B).................................................................................... 7-9

7.3.9.

BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

7.3.10.

Our IP Address Registers (0x10-0x13) ...................................................................... 7-9

7.3.11.

Clock Divider Registers (0x1C-0x1D) ...................................................................... 7-10

7.3.12.

Index Register (0x20) ............................................................................................... 7-10

7.3.13.

Type of Service Register (TOS) (0x21) .................................................................... 7-10

7.3.14.

Socket Config Status Low Register (0x22)............................................................... 7-11

7.3.15.

Socket Status Mid Register (0x23)........................................................................... 7-13

7.3.16.

Socket Activate Register (0x24) ............................................................................... 7-14

7.3.17.

Socket Interrupt Register (0x26) .............................................................................. 7-14

7.3.18.

Socket Data Available Register (0x28)..................................................................... 7-15

7.3.19.

Socket Interrupt Mask Low Register (0x2A)............................................................. 7-16

7.3.20.

Socket Interrupt Mask High Register (0x2B)............................................................ 7-16

7.3.21.

Socket Interrupt Low Register (0x2C) ...................................................................... 7-17

7.3.22.

Socket Interrupt High Register (0x2D) ..................................................................... 7-17

7.3.23.

Socket Data Register (0x2E).................................................................................... 7-18

7.3.24.

TCP Data Send and Buffer Out Length Registers (0x30-0x31) ............................... 7-18

7.3.25.

Buffer In Length Registers (0x32-0x33) ................................................................... 7-18

7.3.26.

Urgent Data Pointer Registers (0x34-0x35) ............................................................. 7-18

7.3.27.

Their Port Registers (0x36-0x37) ............................................................................. 7-19

7.3.28.

Our Port Registers (0x38-0x39) ............................................................................... 7-19

7.3.29.

Socket Status High Register (0x3A)......................................................................... 7-19

7.3.30.

Their IP Address Registers (0x3C-0x3F) ................................................................. 7-20

7.3.31.

PPP Control and Status Register (0x60).................................................................. 7-21

7.3.32.

PPP Interrupt Code (0x61) ....................................................................................... 7-22

7.3.33.

PPP Max Retry, (0x62).............................................................................................. 7-22

7.3.34.

PAP String (0x64)..................................................................................................... 7-23

DATA COMMUNICATIONS.......................................................................................................... 8-1

8.1.

VERVIEW

............................................................................................................................... 8-1

8.2.

ERIAL

ORT

EGISTER

................................................................................................... 8-1

8.2.1.

Hardware Flow Control (RTS/CTS Handshaking) .......................................................... 8-2

8.2.2.

Serial Port Control........................................................................................................... 8-2

8.3.

TCP/UDP D

ATA

OMMUNICATIONS

.......................................................................................... 8-3

8.3.1.

TCP Data Communications ............................................................................................ 8-3

8.3.2.

UDP Data Communications ............................................................................................ 8-4

RESET FUNCTIONS .................................................................................................................... 9-1

9.1.

VERVIEW

............................................................................................................................... 9-1

9.1.1.

Hardware Reset Function ............................................................................................... 9-1

9.1.2.

Software Reset Function................................................................................................. 9-1

10. APPLICATION EXAMPLES........................................................................................................ 10-1

10.1.1. In Case of x80 Family MPU with LCD Controller .......................................................... 10-1
10.1.2. In Case of 68k Family MPU with LCD Controller .......................................................... 10-2
10.1.3. In Case of Serial Interface with LCD Controller ............................................................ 10-3

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

iii

LIST OF FIGURES

IGURE

2-1

LOCK

IAGRAM

............................................................................................................... 2-1

IGURE

3-1

SSIGNMENT

.............................................................................................................. 3-1

IGURE

3-2

ACKAGE

IMENSIONS

...................................................................................................... 3-2

IGURE

3-3

ONFIGURATION OF

ACH

........................................................................................... 3-4

IGURE

5-1

AMILY

MPU W

RITE

IMING

....................................................................................... 5-2

IGURE

5-2

AMILY

MPU R

EAD

IMING

......................................................................................... 5-3

IGURE

5-3

80 F

AMILY

MPU W

RITE

YCLE

IMING

............................................................................ 5-4

IGURE

5-4

80 F

AMILY

MPU R

EAD

YCLE

IMING

.............................................................................. 5-5

IGURE

5-5

ERIAL

NTERFACE

RITE

IMING

..................................................................................... 5-6

IGURE

5-6

ERIAL

NTERFACE

EAD

IMING

....................................................................................... 5-7

IGURE

5-7

INT1 I

NTERRUPT

IMING

................................................................................................... 5-8

IGURE

6-1

EMORY

NTERFACE

RCHITECTURE

................................................................................. 6-1

IGURE

8-1

ERIAL

ATA

ORMAT

....................................................................................................... 8-1

IGURE

9-1

ARDWARE

ESET

IMING

................................................................................................ 9-1

IGURE

9-2

OFTWARE

ESET

IMING

................................................................................................. 9-1

IGURE

10-1 E

XAMPLE FOR X

80 F

AMILY

MPU...................................................................................... 10-1

IGURE

10-2 E

XAMPLE FOR

AMILY

MPU...................................................................................... 10-2

IGURE

10-3 E

XAMPLE FOR

ERIAL

NTERFACE

.................................................................................... 10-3

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

LIST OF TABLES

ABLE

3-1 P

SSIGNMENT

.................................................................................................................. 3-1

ABLE

3-2 P

ESCRIPTION

.................................................................................................................. 3-3

ABLE

4-1 A

BSOLUTE

AXIMUM

ATINGS

.............................................................................................. 4-1

ABLE

4-2 R

ECOMMENDED

PERATING

ONDITIONS

.............................................................................. 4-1

ABLE

4-3 DC

HARACTERISTICS

.......................................................................................................... 4-2

ABLE

4-4 P

OWER

URRENT

ONSUMPTION

.......................................................................................... 4-2

ABLE

5-1 I

NTERFACE

ELECTION

.......................................................................................................... 5-1

ABLE

5-2 C

ONNECTION

ELATIONSHIP BETWEEN

MPU

AND

INS

.......................................................... 5-1

ABLE

5-3 68

AMILY

MPU W

RITE

YCLE

IMING

................................................................................ 5-2

ABLE

5-4 68

AMILY

MPU R

EAD

YCLE

IMING

................................................................................. 5-3

ABLE

5-5

80 F

AMILY

MPU W

RITE

YCLE

IMING

................................................................................ 5-4

ABLE

5-6

80 F

AMILY

MPU R

EAD

YCLE

IMING

................................................................................. 5-5

ABLE

5-7 S

ERIAL

NTERFACE

RITE

YCLE

IMING

.............................................................................. 5-6

ABLE

5-8 S

ERIAL

NTERFACE

EAD

YCLE

IMING

................................................................................ 5-7

ABLE

5-9 I

NTERRUPT

ELECTION

ABLE

............................................................................................... 5-8

ABLE

6-1 S-7600A M

EMORY

ANK

0) ......................................................................................... 6-2

ABLE

6-2 S-7600A M

EMORY

ANK

1) ......................................................................................... 6-2

ABLE

7-1

API R

EGISTER

............................................................................................................. 7-2

ABLE

7-2

API R

EGISTER

ONTINUED

) ........................................................................................ 7-3

ABLE

7-3 R

EVISION

EGISTER

EFINITIONS

.................................................................................... 7-4

ABLE

7-4 R

EVISION

EGISTER

ESCRIPTION

........................................................................................ 7-4

ABLE

7-5 G

ENERAL

ONTROL

EGISTER

EFINITIONS

.................................................................... 7-4

ABLE

7-6 G

ENERAL

ONTROL

EGISTER

ESCRIPTION

......................................................................... 7-4

ABLE

7-7 G

ENERIC

OCKET

OCATION

EGISTER

EFINITIONS

....................................................... 7-5

ABLE

7-8 G

ENERIC

OCKET

OCATION

EGISTER

ESCRIPTION

........................................................... 7-5

ABLE

7-9 M

ASTER

NTERRUPT

EGISTER

EFINITIONS

.................................................................... 7-5

ABLE

7-10 M

ASTER

NTERRUPT

EGISTER

ESCRIPTIONS

ONTINUED

) ............................................... 7-6

ABLE

7-11 C

ONF

TATUS

EGISTER

EFINITIONS

........................................................................... 7-6

ABLE

7-12 C

ONF

TATUS

EGISTER

ESCRIPTION

............................................................................... 7-7

ABLE

7-13 S

ERIAL

ORT

NTERRUPT

EGISTER

EFINITIONS

.......................................................... 7-8

ABLE

7-14 S

ERIAL

ORT

NTERRUPT

EGISTER

ESCRIPTION

............................................................... 7-8

ABLE

7-15 S

ERIAL

ORT

NTERRUPT

ASK

EGISTER

EFINITIONS

................................................. 7-8

ABLE

7-16 S

ERIAL

ORT

NTERRUPT

ASK

EGISTER

ESCRIPTION

..................................................... 7-8

ABLE

7-17 O

IP A

DDRESS

EGISTER

EFINITIONS

10) .......................................................... 7-9

ABLE

7-18 O

IP A

DDRESS

EGISTER

EFINITIONS

11) .......................................................... 7-9

ABLE

7-19 O

IP A

DDRESS

EGISTER

EFINITIONS

12) ........................................................ 7-10

ABLE

7-20 O

IP A

DDRESS

EGISTER

EFINITIONS

13) ........................................................ 7-10

ABLE

7-21 I

NDEX

EGISTER

EFINITION

....................................................................................... 7-10

ABLE

7-22 I

NDEX

EGISTER

ESCRIPTION

.......................................................................................... 7-10

ABLE

7-23 S

OCKET

ONFIG

TATUS

EGISTER

EFINITIONS

................................................ 7-11

ABLE

7-24 S

OCKET

ONFIG

TATUS

EGISTER

ESCRIPTION

..................................................... 7-12

ABLE

7-25 S

OCKET

TATUS

EGISTER

EFINITIONS

.............................................................. 7-13

ABLE

7-26 S

OCKET

TATUS

EGISTER

ESCRIPTION

................................................................... 7-13

ABLE

7-27 S

OCKET

CTIVATE

EGISTER

EFINITIONS

.................................................................. 7-14

ABLE

7-28 S

OCKET

CTIVATE

EGISTER

ESCRIPTION

....................................................................... 7-14

ABLE

7-29 S

OCKET

NTERRUPT

EGISTER

EFINITIONS

................................................................ 7-14

ABLE

7-30 S

OCKET

NTERRUPT

EGISTER

ESCRIPTION

.................................................................... 7-15

ABLE

7-31 S

OCKET

ATA

VAIL

EGISTER

EFINITIONS

............................................................... 7-15

ABLE

7-32 S

OCKET

ATA

VAIL

EGISTER

ESCRIPTION

................................................................... 7-15

ABLE

7-33 S

OCKET

NTERRUPT

ASK

EGISTER

EFINITIONS

.............................................. 7-16

ABLE

7-34 S

OCKET

NTERRUPT

ASK

EGISTER

ESCRIPTION

................................................... 7-16

ABLE

7-35 S

OCKET

NTERRUPT

ASK

IGH

EGISTER

EFINITIONS

.............................................. 7-16

ABLE

7-36 S

OCKET

NTERRUPT

ASK

IGH

EGISTER

ESCRIPTION

.................................................. 7-16

ABLE

7-37 S

OCKET

NTERRUPT

EGISTER

EFINITIONS

........................................................ 7-17

ABLE

7-38 S

OCKET

NTERRUPT

EGISTER

ESCRIPTION

............................................................. 7-17

ABLE

7-39 S

OCKET

NTERRUPT

IGH

EGISTER

EFINITIONS

....................................................... 7-17

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

ABLE

7-40 S

OCKET

NTERRUPT

IGH

EGISTER

ESCRIPTION

............................................................ 7-18

ABLE

7-41 T

HEIR

ORT

EGISTER

EFINITIONS

36) ................................................................ 7-19

ABLE

7-42 T

HEIR

ORT

EGISTER

EFINITIONS

37) ................................................................ 7-19

ABLE

7-43 O

ORT

EGISTER

EFINITIONS

38)................................................................... 7-19

ABLE

7-44 O

ORT

EGISTER

EFINITIONS

39)................................................................... 7-19

ABLE

7-45

OCKET

TATUS

IGH

EGISTER

EFINITIONS

............................................................. 7-19

ABLE

7-46 S

OCKET

TATUS

IGH

EGISTER

ESCRIPTION

................................................................. 7-20

ABLE

7-47 T

HEIR

IP A

DDRESS

EGISTER

EFINITIONS

3C) ..................................................... 7-20

ABLE

7-48 T

HEIR

IP A

DDRESS

EGISTER

EFINITIONS

3D) ..................................................... 7-20

ABLE

7-49 T

HEIR

IP A

DDRESS

EGISTER

EFINITIONS

3E)...................................................... 7-20

ABLE

7-50 T

HEIR

IP A

DDRESS

EGISTER

EFINITIONS

3F)...................................................... 7-20

ABLE

7-51 PPP C

ONTROL AND

TATUS

EGISTER

EFINITIONS

60) ........................................ 7-21

ABLE

7-52 PPP C

ONTROL

TATUS

EGISTER

ESCRIPTION

............................................................... 7-21

ABLE

7-53 PPP I

NTERRUPT

ODE

EGISTER

EFINITIONS

........................................................... 7-22

ABLE

7-54 PPP I

NTERRUPT

RROR

ODES

........................................................................................ 7-22

ABLE

7-55 PPP M

ETRY

EGISTER

.............................................................................................. 7-22

ABLE

7-56 PAP S

TRING

ORMAT

....................................................................................................... 7-23

ABLE

7-57 PAP S

TRING

XAMPLE

...................................................................................................... 7-23

ABLE

8-1 S

ERIAL

ORT

EGISTER

................................................................................................ 8-1

ABLE

8-12 H

EADER

TRUCTURE

.......................................................................................................... 8-5

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

1-1

1. Introduction

1.1. Product Overview

The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier
connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer.
Implementing this LSI into your system can significantly reduce your software development cost. Also its
low operating frequency gives benefits to the power consumption.
The S-7600A also supports a microprocessor interface via the iReady iAPI

to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow
any micro controller system to interface with the internal modules.

1.2. Features

Industry standard protocols support :

TCP/IP (Ver.

4.0)

PPP

(STD-51-compliant)

UDP

General purpose sockets :

Configured for two sockets

MPU interface :

68k/x80(MOTO/Intel) bus interface or Synchronous serial interface

Physical Transport Layer Interface :

Universal Asynchronous Receiver/Transmitter (UART)

Low clock rate :

Multiplied four by the bit-rate

Operating frequency :

256kHz

typical

Low power consumption :

Full-transmitting Operating current consumption : 0.9mA typ.
Non-transmitting Operating current consumption : 150�A typ.
Standby current consumption : 1.0�A typ.

Stand-by mode :

held by RESET signal

Wide operating voltage range :

2. 4V to 3.6V

Easier application development :

portable

iAPI

support

1.3. Benefits

Off-loads MIPS allowing system to operate with low end and low cost processors.
Consumes minimal power-up to 1/100 of competing solution.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

1-2

Seiko Instruments Inc.

1.4. Trademarks

iReady iAPI

and iAPI

is a trademark of iReady Corporation. All other products and brand names are

trademarks and registered trademarks of their respective companies.

1.5. Definitions

Internet

Protocol

PPP

Point-to-Point

Protocol

TCP

Transmission Control Protocol

UDP

User Datagram Protocol

API

Application Programming Interface

1.6. Applicable Documents

S-7600A Functional Specification
S-7600A API Application Manual

1.7. Cautions

1. DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If

applied, the IC may malfunction or be destroyed.
The standard values are set with sufficient margins, but use the IC within the recommended
operating conditions to optimize device quality.

2. Measures against static electricity

2.1 When transporting or storing ICs, use conductive containers or metal coated boxes.
2.2 Check that there is no current leakage in electrical facilities, and be sure to ground them.

Also ensure that workbenches and people who handle ICs are grounded.

3. Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading

to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause,
and turn on the device again.

4. Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These

may cause wires to break.

5. Environment

5.1 Use and store ICs below the absolute maximum rated temperature.
5.2 DO NOT use or store ICs where condensation can occur.
5.3 DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO

These may cause leaks between element leads and cause corrosion.

5.4 To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load

to ICs.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

2-1

2. Functional Block Diagram

Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and
other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for
various data terminal equipment.

Figure 2-1

Block Diagram

The transport and network layers contain:

Two general sockets that provide connectivity between the application layer and the transport layer.

TCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission)

datagram deliveries.

IP module that provides connectionless packet delivery.
PPP module that provides point-to-point connection link between two hosts.

U Interface

CTSX

Network Stack

Physical Layer

Interface

SRAM

10Kbytes

SD(7:0)

CS
PSX
C86
RS
READX
WRITEX
BUSYX
INTCTL
INT1
INT2X

DSRX

RXD

DCD

DTRX

RTSX

TXD

RESETX

CLK

PPP

UDP

TCP

terface

S2P

16-byte

FIFO

P2S

1-byte

BUFFER

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

3-1

Seiko Instruments Inc.

3. Terminals

3.1.

Pin Assignment

Figure 3-1 shows Pin Assignment in Package.

Table 3-1 shows signal names, listed by Pin Number.

Pin No.

Pin name

Pin No.

Pin name

Pin No.

Pin name

Pin No.

Pin name

RESETX

TO7

TI3

SD7

TEST

TO6

CLK

TO5

TI2

VSS

TO4

C86

SD6

CTSX

TO3

READX

TI1

DSRX

TO2

VSS

VDD

TO1

PSX

SD5

RXD

VDD

WRITEX

SD4

DCD

TI7

INTCTRL

SD3

DTRX

TI6

INT1

SD2

RTSX

TI5

INT2X

SD1

TXD

TI4

BUSYX

SD0

Table 3-1

Pin Assignment

RXD

VSS

EST

RESET

TI4
TI5
TI6
TI7
VDD
TO1
TO2
TO3
TO4
TO5
TO6
TO7

REA

VSS

WRI

2
X

SD7
NC
TI2
SD6
TI1
VDD
SD5
SD4
SD3
SD2
SD1
SD0

Figure 3-1Pin Assignment

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

3-2

3.2. Package Dimensions

S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is
depicted in Figure 3-2.

Figure 3-2

Package Dimensions

0.20

+0.10
-0.05

0.50

0�

9.0�0.3

7.0

0�

5�

0.15

+0.10
-0.06

UNIT:mm

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

3-3

Seiko Instruments Inc.

3.3. Pin Description

The pins and signal descriptions are listed by function in Table 3-2.

Name

I/O

Description

Type

VDD1,VDD2

Positive power supply

VSS1,VSS2

GND potential

RESETX

Reset input

TEST,

TI1 to TI7

Test input (pull-down resistor is built in)

When normal use, connect to V

or open

TO1 to TO7

Test output

When normal use, open

CLK

Clock input

CTSX

Clear to send input

DSRX

Data set ready input

Ring indicator input

RXD

Serial received data input

DCD

Data carrier detect input

DTRX

Data terminal ready output

RTSX

Request to send output

TXD

Serial transmit data output

Chip selection input

C86

MPU interface mode selection input

68k mode : 1

x80 mode : 0

READX

x80 mode : read requirement input

68k mode : enable input

PSX

parallel/serial interface selection input

WRITEX

x80 mode : write requirement input

68k/Serial mode : read/write selection input

INTCTRL

INT1/INT2X drive type(CMOS/OD) selection input

INT1

*OT Interrupt output(active High) from S-7600A chip to MPU

INT2X

*OT Interrupt output(active Low) from S-7600A chip to MPU

BUSYX

busy indicator output

SD7

x80/68k mode : data bus

Serial mode : serial data input

SD6

x80/68k mode : data bus

Serial mode : serial clock input

SD5

x80/68k mode : data bus

Serial mode : serial data output

SD0 to SD4

Data bus

*OT : Tri-state output

*B :

bi-directional

Table 3-2

Pin Description

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

3-4

3.4. Pin Configuration

Figure 3-3 shows configuration of each pin.

Figure 3-3

Configuration of Each Pin

pad

cin

oen

cin

Vss

pad

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

4-1

Seiko Instruments Inc.

4. Electrical Characteristics

4.1. Absolute Maximum Ratings

Parameter

Symbol

Conditions

Rating

Unit

Storage temperature

sta

-40 to +125

�

Operating temperature

opr

-40 to +85

�

Power supply voltage

Ta=25

�

-0.3 to +4.0

Input voltage

Ta=25

�

-0.3 to V

+0.3

Output voltage

OUT

Ta=25

�

to V

Table 4-1

Absolute Maximum Ratings

4.2. Recommended Operating Conditions

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Note

Operating Frequency

range

OPR

Ta=-40 to +85

�

0.256

MHz

Clock Pulse

width

Ta=-40 to +85

�

Operating voltage

range

Ta=-40 to +85

�

2.4

3.6

Input voltage

Ta=-40 to +85

�

Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate.

(The multiplier is an integer whose tolerance is <

�

2%)

Table 4-2

Recommended Operating Conditions

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

4-2

4.3. DC Characteristics

Unless otherwise specified: V

=3.0V, V

=0V, Ta=25

�

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Low level input

voltage

0.2

�

High level input

voltage

0.8

�

Low level input

leakage current

-1.0

1.0

�A

High level input

leakage current

All input terminals without

pull-down resister

-1.0

1.0

�A

High level input

current

All input terminals with

pull-down resister

220

�A

Low level output

current

=0.4V

5.0

High level output

current

=2.6V

-3.5

Schmitt Hysteresis

voltage

0.46

Table 4-3

DC Characteristics

4.4. Power Current Consumption

Unless otherwise specified: V

=3.0V, V

=0V, Ta=25

�

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Full-transmitting

Operating current

consumption

DD1

Ta=-40 to +85

�

OPR

=256KHz

0.9

2.2

Non-transmitting

Operating current

consumption

DD2

Ta=-40 to +85

�

OPR

=256KHz

RESETX=V

150

300

�A

Ta=-10 to +70

�

1.0

15.0

Standby current

consumption

Ta=-40 to +85

�

30.0

�A

Table 4-4

Power Current Consumption

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

5-1

Seiko Instruments Inc.

5. MPU Interface

5.1. Overview

The S-7600A supports two MPU interfaces: parallel and serial. In parallel interface mode, S-7600A can
interface with x80 Family MPU or 68k Family MPU.

PSX

READ

WRITEX

BUSYX

C86

SD7

SD6

SD5

SD4 to SD0

parallel x80

READ

WRITEX

BUSYX

D4 to D0

parallel 68k

R/WX

BUSYX

D4 to D0

serial

H or L

R/WX

BUSYX

H or L

SCL

Hi-Z

Table 5-1

Interface Selection

5.2. Parallel Interface

Setting PSX to "H" select the parallel interface. In parallel interface mode the S-7600A can interface with
either x80 Family MPU or 68k Family MPU. The desired MPU mode can be selected by setting the C86
pin to "H" or "L".

68k Family MPU

R/WX

x80 Family MPU

Function

READX

WRITEX

Read Register

Write Register

Read Index Register

Write Index Register

Table 5-2

Connection Relationship between MPU and Pins

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

5-2

5.2.1. 68k Family MPU Mode

This mode can be selected by pulling the C86 input pin "H" and the PSX input pin "H". In this mode, the
address and data are muxed into a single 8-bit bus. All cycles start by placing an address on the bus and
setting the RS pin to "L". In this mode WRITEX signal works as read/write(R/WX) signal and READX is
the enable(E) signal for 68k Family MPU interface. After the address cycle, the MPU generates a read or
writes strobe by setting the READX and WRITEX pins. The S-7600A MPU interface logic assert a
BUSYX signal low during data write and read phases. The MPU samples the BUSYX signal before
starting a new cycle. The can initiate a new cycle if the bit is "H".

5.2.1.1. Write Cycle Timing

Figure 5-1

68k Family MPU Write Timing

Symbol

Description

Min

Max

Notes

CYC6

System Cycle Time

100 ns

AH6

Address Hold Time

20ns

AW6

Address Setup Time

20ns

DS6

Data Setup time

20ns

DH6

Data Hold Time

20 ns

Enable Pulse Width

40 ns

1.9CLK

BD6

BUSYX Delay Time

30ns

CL=80pF

BC6

BUSYX Pulse Width

2CLK

BOD6

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-3

68k Family MPU Write Cycle Timing

WRITEX
(R/WX)

CLK

BUSYX

READX
(E)

SD7 to 0

AH6

AW6

DH6

DS6

BD6

BC6

DH6

AH6

AW6

CYC6

Address

Data

DS6

BOD6

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S-7600A

Hardware Specification Revision 1.3

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Seiko Instruments Inc.

5.2.1.2. Read Cycle Timing

Figure 5-2

68k Family MPU Read Timing

Symbol

Description

Min

Max

Notes

CYC6

System Cycle Time

100 ns

AH6

Address Hold Time

20ns

AW6

Address Setup Time

20ns

DS6

Data Setup time

20ns

DH6

Data Hold Time

20 ns

ACC6

Access time

30ns

CL=80pF

OH6

Output Disable Time

20 ns

CL=80pF

Enable Pulse Width

40 ns

1.9CLK

BD6

BUSYX Delay Time

30ns

CL=80pF

BC6

BUSYX Pulse Width

2CLK

BOD6

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-4

68k Family MPU Read Cycle Timing

WRITEX
(R/WX)

CLK

BUSYX

READX
(E)

SD7 to 0

AH6

DH6

DS6

BD6

BC6

OH6

AW6

AH6

ACC6

CYC6

AW6

AH6

Address

Data

Address

BOD

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

5-4

5.2.2. x80 Family MPU Mode

This mode is selected by pulling the C86 input pin "L" and the PSX input pin "H". In this mode, the
address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus.
This address is then latched internally on the rising edge of WRITEX. The RS pin "L" indicates that the
WRITEX strobe is for the address phase. In the next phase, data is either written or read by generating
WRITEX or READX strobe. The MPU interface logic will assert the BUSYX signal after READX or
WRITEX strobes are de-asserted. The BUSYX signal is de-asserted after the S-7600A complete a read
or writes operation. The MPU samples the BUSYX signal before starting a new cycle. The MPU can
initiate a new cycle after the BUSYX signal gets de-asserted.

5.2.2.1. Write Cycle Timing

Figure 5-3

x80 Family MPU Write Cycle Timing

Symbol

Description

Min

Max

Notes

CYC8

System Cycle Time

100 ns

AH8

Address Hold Time

20ns

AW8

Address Setup Time

20ns

DS8

Data Setup time

20ns

DH8

Data Hold Time

20 ns

CC8

Control Pulse Width

40 ns

1.9CLK

BD8

BUSYX Delay Time

30ns

CL=80pF

BC8

BUSYX Pulse Width

2CLK

BOD8

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-5

x80 Family MPU Write Cycle Timing

READX

CLK

BUSYX

WRITEX

SD7 to 0

AH8

AW8

CC8

DH8

DS8

BD8

BC8

DH8

AH8

AW8

CYC8

CC8

DS8

BOD8

Address

read

Data

read

TCP/IP Network Stack LSI

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Hardware Specification Revision 1.3

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Seiko Instruments Inc.

5.2.2.2. Read Cycle Timing

Figure 5-4

x80 Family MPU Read Cycle Timing

Symbol

Description

Min

Max

Notes

CYC8

System Cycle Time

100 ns

AH8

Address Hold Time

20ns

AW8

Address Setup Time

20ns

DS8

Data Setup time

20ns

DH8

Data Hold Time

20 ns

ACC8

Access time

30ns

CL=80pF

OH8

Output Disable Time

20 ns

CL=80pF

CC8

Control Pulse Width

40 ns

1.9CLK

BD8

BUSYX Delay Time

30ns

CL=80pF

BC8

BUSYX Pulse Width

2CLK

BOD8

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-6

x80 Family MPU Read Cycle Timing

READX

CLK

BUSYX

WRITEX

SD7 to 0

AH8

BD8

BC8

OH8

AW8

AH8

ACC8

CYC8

AW8

AH8

Address

Data

Address

CC8

DS8

BOD

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S-7600A

Hardware Specification Revision 1.3

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5-6

5.3. Serial Interface

This mode is selected by pulling the PSX input pin "L". In this mode Bit 6 of the Data Bus is used as the
serial clock and bit 5 and 7 are used as Data Input and Data Output. Bit 0 to 4 are high impedance. By
pulling WRITEX signal to "H" or "L", the MPU performs a read or write operation.

5.3.1. Write Cycle Timing

Figure 5-5

Serial Interface Write Timing

Symbol

Description

Min

Max

Notes

CYCS

System Cycle Time

100 ns

1.9CLK

CLLS

Clock L Time

40ns

CLHS

Clocl H Time

40 ns

ASS

Address Setup Time

20ns

AHS

Address Hold Time

20ns

DSS

Data Setup time

20ns

DHS

Data Hold Time

20 ns

BDS

BUSYX Delay Time

30ns

CL=80pF

BCS

BUSYX Pulse Width

2CLK

BODS

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-7

Serial Interface Write Cycle Timing

WRITEX
(R/WX)

CLK

BUSYX

SD6
(SCL)

SD7
(SI)

AHS

ASS

BDS

BCS

ASS

AHS

CYCS

DSS

DHS

BODS

CLLS

CLHS

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

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Seiko Instruments Inc.

5.3.2. Read Cycle Timing

WRITEX
(R/WX)

CLK

BUSYX

SD6
(SCL)

SD7
(SI)

AHS

ASS

BDS

BCS

CYCS

DHS

DDS

DSS

OHS

AHS

ASS

AHS

OHS

SD5
(SO)

DDS

BODS

CLLS

CLHS

Figure 5-6

Serial Interface Read Timing

Symbol

Description

Min

Max

Notes

CYCS

System Cycle Time

100 ns

1.9CLK

CLLS

Clock L Time

40ns

CLHS

Clocl H Time

40 ns

ASS

Address Setup Time

20ns

AHS

Address Hold Time

20ns

DSS

Data Setup time

20ns

DHS

Data Hold Time

20 ns

DDS

Data delay Time

30ns

CL=80pF

OHS

Output Disable Time

20ns

CL=80pF

BDS

BUSYX Delay Time

30ns

CL=80pF

BCS

BUSYX Pulse Width

2CLK

BODS

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

�

CLK is the clock of S-7600A

�

Timing is specified of 50% of the signal waveform.

�

Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-8

Serial Interface Read Cycle Timing

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

5-8

5.4. Interrupt

The interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the
S-7600A's interrupt register. The interrupt signal returns to an inactive level if the flag clears. Show the
interrupt timing in the Figure 5-7.
The INT1 and INT2X can be Open Drain or CMOS output depending on the setting of INTCTL. The INT1
and INT2X outputs are CMOS if INTCTL is "H" otherwise outputs are Open Drain. Table 5-9 defines the
interrupt selection.

Interrupt flag

INTCTL

INT1

INT2X

Set

Reset

Hi-Z

Table 5-9

Interrupt Selection Table

Figure 5-7

INT1 Interrupt Timing

CLK

BUSYX

WRITEX

SD7 to 0

Address

Data

INT1

Clear

(x80 Family MPU mode, INTCTL=high)

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

6-1

Seiko Instruments Inc.

6. Memory Requirements

6.1. Overview

S-7600A contains two general sockets along with the TCP/UDP/IP and PPP protocols. Their total
memory requirement is 10K bytes. This memory is included on the S-7600A chip.

6.2. Memory Interface Architecture

The Network Stack feeds all of its memory requests into a single Memory Arbiter inside of the Network
Stack core. The arbiter then feeds out one memory request to the SRAM interface. This interface serves
to translate the network stack's timing into signal timing required by the SRAM. This architecture is
shown in Figure 6-1.

TCP / UDP

PPP

Network Stack

Serial Port

Memory

Arbiter

SRAM

Interface

SRAM

Figure 6-1

Memory Interface Architecture

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

6-2

6.3. Memory Map

The memory map has been configured to make the SRAM supporting the S-7600A compact. S-7600A
has two 5 K byte memory banks (denoted as "0" and "1"). Their mapping addresses are given in Table
6-1 and Table 6-2.
The actual capacity of the incoming buffer is 2047 bytes.
The actual capacity of the outgoing buffer is 1023 bytes for TCP mode and 1015 bytes for UDP mode.

Table 6-1

S-7600A Memory Map (Bank 0)

Address

Size

Contents

0x0000 - 0x07FF

2 K

Socket 0 Receive Buffer

0x0800 - 0x0BFF

1 K

Socket 0 Send Buffer

0x0C00 - 0x0FFF

1 K

TCP Data Base

0x1000 - 0x13FF

1 K

IP Buffer

Table 6-2

S-7600A Memory Map (Bank 1)

Address

Size

Contents

0x0000 - 0x07FF

2 K

Socket 1 Receive Buffer

0x0800 - 0x0BFF

1 K

Socket 1 Send Buffer

0x0C00 - 0x0FFF

1 K

PPP Buffer

0x1000 - 0x13FF

1 K

PAP Buffer

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7-1

Seiko Instruments Inc.

7. S-7600A Register Definitions

7.1. Overview

This section covers the S-7600A's API registers. The register are divided into three types: global, direct
and indexed.

Global registers occupy the address space from 0x00 to 0x1D and 0x60 to 0x6F. Direct and indexed
registers occupy the configuration space from 0x20 to 0x3F. Indexed register require the socket index to
be set prior to accessing the registers.

7.2. iAPI Register Map

Table 7-1 and Table 7-2 shows the complete iAPI register map for the S-7600A chip. All registers not
listed are reserved, and should not be accessed.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

7-2

Table 7-1

iAPI Register Map

Add

Register

Bit Definitions

0x00

Revision

Major Revision Number

Minor Revision Number

0x01

General_Control

SW_
RST

0x02

General_Socket_

Location

0x04

Master_Interrupt

PT_
INT

LINK
_INT

SOCK
_INT

0x08

Serial_Port_Config

DA
V

DCD

DSR/

HWFC

CTS

DTR

RTS

SCTL

0x09

Serial_Port_Int

PT_

INT

0x0A

Serial_Port_Int_

Mask

PINT

_EN

DSINT_
EN

0x0B

Serial_Port_Data

Serial Data Register

0x0C - 0x0D BAUD_Rate_Div

BAUD Rate Divider Registers

0x10 - 0x13

Our_IP_Address

Our IP Address

0x1C

Clock_Div_Low

Low Byte for 1 kHz clock divider

0x1D

Clock_Div_High

High Byte for 1 kHz clock divider

0x20

Index

Socket index

0x21

TOS*

Type of Service Field

0x22

Socket_
Config_Status_Low*

Buff_

Empty

Buff_

Full

Data_

Avail/

RST

Protocol_Type

0x23

Socket_Status_Mid*

URG

RST

Term

ConU

TCP State

0x24

Socekt_Activate

0x26

Socket_Interrupt

0x28

Socket_Data_Avail

DAV1

DAV0

NOTE:

1)Reserved bits are signified by a dash (-). All reserved bits should be written as "0".
2)Indexed registers are signified by an asterisk (*).

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

7-3

Seiko Instruments Inc.

Table 7-2

iAPI Register Map (Continued)

Add

Register

Bit Definitions

0x2A

Socket_Interrupt_
Mask_Low*

TO_

Buff_

Emp_

Buff_F

ull

Data_
Avail_

0x2B

Socket_Interrupt_
Mask_High*

URG_En

RST_

Term_

ConU_

0x2C

Socket_Interrupt_Low*

Buff_

Empty

Buff_

Full

Data_

Avail

0x2D

Socket_Interrupt_High*

URG

RST

Term

ConU

0x2E

Socket_Data*

Socket 8-bit data

0x30

TCP_Data_Send (WO)*

Any write causes data to be sent

0x30 - 0x31

Buffer_Out (RO)*

Buffer Out Length

0x32 - 0x33

Buffer_In (RO)*

Buffer In Length

0x34 - 0x35

Urgent_Data_Pointer*

Urgent Data Offset Pointer

0x36 - 0x37

Their_Port*

Target Port Address

0x38 - 0x39

Our_Port*

Our Port Address

0x3A

Socket_Status_High*

Snd

_bsy

0x3C - 0x3F

Their_IP_Address*

Target IP Address

0x60

PPP_Control_Status

PPP_Int

Con_

Val

Use_

PAP

To_

Dis

PPP_

Int_En

Kick

PPP_

Up /

SRset

0x61

PPP_Interrupt_Code

Interrupt Code

0x62

PPP_Max_Retry

PPP Maximum retry

0x64

PPP_String

Pap user name and password

NOTE:

1)Reserved bits are signified by a dash (-). All reserved bits should be written as "0".
2)Indexed registers are signified by an asterisk (*).

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

7-4

7.3. Register Definitions

7.3.1. Revision Register (0x00)

(Read-Only, Default 0x21)

This direct read-only register reports back the design revision. See the design revision form in Table 7-3
and Table 7-4.

Table 7-3

Revision Register Bit Definitions

Bit

Def.

Major Revision Number

Minor Revision Number

Default

0x2

0x1

Table 7-4

Revision Register Description

Bit

Bit Name

Access

Description

7:4

Major Revision
Number

This nibble indicates the major revision number for
the S-7600A core.

3:0

Minor Revision
Number

This nibble indicates the minor revision number for
the S-7600A core.

7.3.2. General Control Register (0x01)

(Read/Write, Default 0x00)

This direct register contains the master software reset. See the register format in Table 7-5 and Table
7-6.See the wave format in figure 9.-2.

Table 7-5

General Control Register Bit Definitions

Bit

Def.

SW_RST

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

Table 7-6

General Control Register Description

Bit

Bit Name

Access

Description

SW_RST

R/W

Software Reset.

This active high reset returns the S-7600A core to
power-on reset settings. It is self-clearing and does
not need to be written to "0" for proper operations.

0 = Normal operation

1 = Soft reset

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S-7600A

Hardware Specification Revision 1.3

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Seiko Instruments Inc.

7.3.3. Generic Socket Location Register (0x02)

(Read-Only)

This register is used to report back the location of general sockets to the software layer. Only bits [1:0] will
be set because the S-7600A chip is equipped with two general sockets.

Table 7-7

Generic Socket Location Register Bit Definitions

Bit

Def.

Value

Table 7-8

Generic Socket Location Register Description

Bit

Bit Name

Access

Description

Not available

General socket 1 available

General socket 0 available

7.3.4. Master Interrupt (0x04)

(Read-Only, Default 0x00)

This direct register indicates the source of the S-7600A interrupt.

Table 7-9

Master Interrupt Register Bit Definitions

Bit

Def.

PT_INT

LINK_INT

SOCK_INT

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0".

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

7-6

Table 7-10

Master Interrupt Register Descriptions (Continued)

Bit

Bit Name

Access

Description

PT_INT

Physical Transport Interrupt

The physical transport triggers this interrupt. An
application should check the Serial Port Int register
to determine the actual cause of the interrupt.

LINK_INT

Link Layer Interrupt

The link layer triggers this interrupt. An application
should check the PPP Interrupt Code register to
determine the actual cause of the interrupt.

SOCK_INT

Socket Interrupt

One of the sockets that need servicing causes this
interrupt. An application should check the Socket
Interrupt register to determine the actual socket
number.

7.3.5. Serial Port Configuration / Status Register (0x08)

(Read/Write, Default 0X0XX110B)

This register configures the serial port as shown in Table 7-11 and Table 7-12.

Table 7-11

Conf Status Register Bit Definitions

Bit

Def.

S_DAV

DCD

DSR/

HWFC

CTS

DTR

RTS

SCTL

Default

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S-7600A

Hardware Specification Revision 1.3

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Seiko Instruments Inc.

Table 7-12

Conf Status Register Description

Bit

Bit Name

Access

Description

S_DAV

R/W

Serial Port Data Available

When read, bit indicates that Serial Port data is
available.

This bit should be written 0.

DCD

R/W

Carrier Detect

This bit reflects the current state of the DCD bit on
the serial port. It is independent of the SCTL bit
setting.

This bit should be written 0.

DSR / HWFC

R/W

Data Send Ready / Hardware Flow Control

When read, this bit reflects the current state of the
DSR bit on the serial port.

When this bit written:

0 = Hardware Flow control is deactivated

1 = Hardware Flow control activated

Refer to Chapter 8 for more information about
Hardware Flow Control.

CTS

Clear To Send

This read-only bit reflects the current state of the
CTS bit on the serial port. It is independent of the
SCTL bit setting.

Ring Indicator

This read-only bit reflects the current state of the RI
bit on the serial port. It is independent of the SCTL
bit setting.

DTR

R/W

Data Terminal Ready

Reading this bit follows the current state of the
DTR bit on the serial port. The MPU can control the
DTR by writing to this bit.

RTS

R/W

Request To Send

Reading this bit follows the current state of the
RTS bit on the serial port. The MPU can control the
RTS by writing to this bit.

SCTL

R/W

Serial Port Control

This bit determines who controls the serial port.
When this bit is low (default), the MPU controls the
port. When the SCTL bit is high, the network stack
controls the serial serial port.

0 = MPU controls serial port

1 = Hardware controls serial port

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7.3.6. Serial Port Interrupt Register (0x09)

(Read-Only, Default 0X000000B)

This register indicates the state of the serial port interrupt.

Table 7-13

Serial Port Interrupt Register Bit Definitions

Bit

Def.

PT_INT

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0".

Table 7-14

Serial Port Interrupt Register Description

Bit

Bit Name

Access

Description

PT_INT

Port Transport Interrupt

This bit indicates when the serial port interrupt is
active. This condition depends on the states of the
PINT_EN and DSINT_EN bits in the Serial Port
Interrupt Mask Register.
When PINT_EN is 1, an interrupt will occur
whenever data is available in the serial port input
FIFO ("S_DAV" in the Serial Port
Configuration/Status Register is 1).
When DSINT_EN is 1, an interrupt will be active
whenever the CPU can write to the Serial Port Data
Register to transmit a byte of data.
If both PINT_EN and DSINT_EN are enabled,
the interrupt will be active if either condition is met.

7.3.7. Serial Port Interrupt Mask Register (0x0A)

(Read/Write, Default 0x00)

This register enables the serial port interrupts. The default for this register is 0x00 (interrupts disabled).

Table 7-15

Serial Port Interrupt Mask Register Bit Definitions

Bit

Def.

PINT_EN

DSINT_EN

Default

NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0".

Table 7-16

Serial Port Interrupt Mask Register Description

Bit

Bit Name

Access

Description

PINT_EN

R/W

Port Interrupt Enable

This is the enable for the port interrupt.

DSINT_EN

R/W

Data sent interrupt Enable.

This is enable for the data sent interrupt.

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7.3.8. Serial Port Data Register (0x0B)

(Read/Write)

This register sends data to and reads data from the serial port UART. The data is valid when the S_DAV
bit in the Serial Port Config register is set. Data can be written to this register when the PT_INT bit in the
Serial Port Interrupt register is set. See the register description in Table 7.-14.

Note: This register should only be used when the SCTL bit in the Serial Port config register is low.

7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)

(Read/Write, Default 0x0000)

These registers set the BAUD rate for the serial port. Calculate the value by using the following formula:

Program Value = [(clk Frequency) / (BAUD Rate)] - 1

Where clk is the clock for the S-7600A core

Example: The clock rate of the S-7600A is 256 KHz and a BAUD rate of 64 Kbps is desired, the
programmed value should be:

(256 KHz / 64 k) - 1 = 4 - 1 = 3

Note: The lowest value that should be programmed into these registers is 0x0003.

7.3.10. Our IP Address Registers (0x10-0x13)

(Read/Write, Default 0x00000000)

These registers store our IP address or the IP address of the local device. The 0x10 register stores the
least significant byte and the 0x13 register stores the most significant byte. If the system controller dose
not write an IP address, it will be negotiated for during PPP negotiations (floating IP address). When a
PPP connection is established (indicated by bit 0, register 60) these registers can be read to query the IP
address obtained.

Table 7-17

Our IP Address Register Bit Definitions (0x10)

Bit

Def.

Least significant byte of the local IP address

Default

0x00

Table 7-18

Our IP Address Register Bit Definitions (0x11)

Bit

Def.

3rd byte of the local IP address

Default

0x00

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Table 7-19

Our IP Address Register Bit Definitions (0x12)

Bit

Def.

2nd byte of the local IP address

Default

0x00

Table 7-20

Our IP Address Register Bit Definitions (0x13)

Bit

Def.

Most significant byte of the local IP address

Default

0x00

7.3.11. Clock Divider Registers (0x1C-0x1D)

(Read/Write, Default

0x03E7)

These registers program the 1kHz clock generator. This clock is used internally for various S-7600A
timing functions. The following equation determines the value programmed into these registers:

(clk Freq/1 kHz) - 1 = Divide Count

Where clk Freq is S-7600A clock frequency. Therefore, for a 1 MHz clock, the divide count equals 1M /
1kHz - 1= 999 = 0x03e7.

7.3.12. Index Register (0x20)

(Read/Write, Default 0x00)

This register must be programmed prior to accessing indexed socket registers. Valid programmed
values are 0x00 and 0x01. If the selected socket number has not changed since the last access, this
register not need to be reprogrammed.

Table 7-21

Index Register Bit Definition

Bit

Def.

Socket Index [7:0]

Default

0x00

Table 7-22

Index Register Description

Bit

Bit Name

Access

Description

7:0

Socket_Index

R/W

0x00 : General Socket 0 Selected

0x01: General Socket 1 Selected

All other values are reserved

7.3.13. Type of Service Register (TOS) (0x21)

(Read/Write, Default 0x00)

This register configures the TOS field in the IP header for outgoing datagrams. It is an optional setting
that defaults to 0x00.

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7.3.14. Socket Config Status Low Register (0x22)

(Read/Write, Default 0x40)

This register configures the socket.

Table 7-23

Socket Config Status Low Register Bit Definitions

Bit

Def.

Buff_

Empty

Buff_Full

Data_

Avail / RST

Protocol_Type

Default

NOTE: Reserved bits are signified by a dash ( - ). All reserved bits should be written as "0".

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Table 7-24

Socket Config Status Low Register Description

Bit

Bit Name

Access

Description

TCP Timeout

This bit indicates that a TCP timeout condition
occurred while attempting to establish a TCP
connection or while waiting for a TCP packet after the
connection was established.

0 = Normal Operating Condition

1 = Timeout Occurred

Buff_Empty

This bit indicates whether or not a socket's outgoing data buffer
is empty. The bit sets on an empty condition. It then clears and
remains clear as long as there is any data in the socket's
outgoing data buffer.

0 = Buffer Not Empty

1 = Buffer Empty

Buff_Full

This bit indicates whether the outgoing buffer is full
(1023 bytes or more). It also triggers an interrupt when
the outgoing data buffer is full, and the Buff_Full_En
bit in the Socket Interrupt Mask Low register (0x2A) is
set. The Data Register should not be written to when
this bit is a "1".

0 = Buffer Space Available

1 = No Buffer Space Available

Data_Avail / RST

R/W

Writing this bit resets all socket parameters to default
settings. It is self-clearing and dose not need to be
written to low for proper operations. Before resetting,
ensure that Snd_Bsy bit of Socket Status High
register (0x3A) is 0. When read, this bit indicates that
the socket has data available.

2:0

Protocol_Type

R/W

These bits are used to set the protocol of the socket.
All decodes not shown are reserved.

010 = TCP Client Mode

101 = UDP Mode

110 = TCP Server mode

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7.3.15. Socket Status Mid Register (0x23)

(Read-Only, Default 0x00)

This read-only register reports other socket status conditions.

Table 7-25

Socket Status Mid Register Bit Definitions

Bit

Def.

URG

RST

Term

ConU

TCP State

Default

0x0

Table 7-26

Socket Status Mid Register Description

Bit

Bit Name

Access

Description

URG

This bit indicates the arrival of urgent data. Writing a "1" to the
URG bit in the Socket Interrupt register (bit 7) clears this bit.

0 = No urgent data present

1 = Urgent data present

RST

This bit indicates when the socket receives the RST signal from
the TCP peer.

0 = No RST received

1 = RST received

Term

This bit indicates when the socket terminates from the source
and triggers an interrupt if the Term_En bit is set in the Socket
Interrupt Mask High register (0x2B). The interrupt mask setting
does not effect the reporting of this status bit.

0 = Normal Operating Condition

1 = Socket terminated from source

This bit becomes "1" when the S-7600A receives a TCP
segment with the FIN flag on. This means that the remote peer
has requested to close the TCP connection.

ConU

This bit indicates when the socket establishes a connection to a
host machine. The bit clears when the connection terminates (by
either end).

0 = No Connection Established

1 = Connection Established

3:0

TCP State

These bits indicate the current TCP state.

0 = CLOSED

1 = SYN_SENT

2 = ESTABLISHED

3 = CLOSE_WAIT

4 = LAST_ACK

5 = FIN_WAIT1

6 = FIN_WAIT2

7 = CLOSING

8 = TIME_WAIT

9 = LISTEN

a = SYN_RECVD

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7.3.16. Socket Activate Register (0x24)

(Read/Write, Default 0x00)

This register is used to activate the sockets and also show the current status of each socket. Setting a bit
to "1" activates the corresponding socket. This register defaults to 0x00 upon resets.

Table 7-27

Socket Activate Register Bit Definitions

Bit

Def.

Default

Table 7-28

Socket Activate Register Description

Bit

Bit Name

Access

Description

R/W

This bit is used to activate general socket 1.

0 = General socket 1 inactive

1 = General socket 1 active

R/W

This bit is used to activate general socket 0.

0 = General socket 0 inactive

1 = General socket 0 active

7.3.17. Socket Interrupt Register (0x26)

(Read-Only, Default 0x00)

This register indicates which socket has interrupts pending. When identification of an interrupting socket
occurs, the actual source of the interrupt is determined by examining the specific socket's interrupt
register.

Table 7-29

Socket Interrupt Register Bit Definitions

Bit

Def.

Default

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Table 7-30

Socket Interrupt Register Description

Bit

Bit Name

Access

Description

This bit is used to indicate that socket 1 has an
interrupt pending.

0 = General socket 1 interrupt inactive

1 = General socket 1 interrupt active

This bit is used to indicate that socket 0 has an
interrupt pending.

0 = General socket 0 interrupt inactive

1 = General socket 0 interrupt active

7.3.18. Socket Data Available Register (0x28)

(Read-Only, Default 0x00)

This read-only register indicates which socket has data pending in the input buffer. A "1" in a bit position
indicates that the socket has data available. The bit remains set as long as there is data available.

Table 7-31

Socket Data Avail Register Bit Definitions

Bit

Def.

DAV1

DAV0

Default

Table 7-32

Socket Data Avail Register Description

Bit

Bit Name

Access

Description

DAV1

This bit is used to indicate that socket 1 has data
available.

0 = General socket 1 has no data available

1 = General socket 1 has data available

DAV0

This bit is used to indicate that socket 0 has data
available.

0 = General socket 0 has no data available

1 = General socket 0 has data available

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7.3.19. Socket Interrupt Mask Low Register (0x2A)

(Read/Write, Default 0x00)

This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.

Table 7-33

Socket Interrupt Mask Low Register Bit Definitions

Bit

Def.

TO_En

Buff_

Emp_En

Buff_Full_En

Data_Avail_En

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

Table 7-34

Socket Interrupt Mask Low Register Description

Bit

Bit Name

Access

Description

TO_En

R/W

Writing a "1" enables the Timeout interrupt.

Buff_Empty_En

R/W

Writing a "1" enables the Buffer Empty interrupt.

Buff_Full_En

R/W

Writing a "1" enables the Buffer Full interrupt.

Data_Avail_En

R/W

Writing a "1" enables the Data Available interrupt.

7.3.20. Socket Interrupt Mask High Register (0x2B)

(Read/Write, Default 0x00)

This register enables certain types of interrupt conditions. Setting bits enables their corresponding
interrupts.

Table 7-35

Socket Interrupt Mask High Register Bit Definitions

Bit

Def.

URG_En

RST_En

Term_En

ConU_En

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

Table 7-36

Socket Interrupt Mask High Register Description

Bit

Bit Name

Access

Description

URG_En

R/W

Writing a "1" to enable the Urgent Data interrupt.

RST_En

R/W

Writing a "1" to enable the Connection Reset interrupt.

Term_En

R/W

Writing a "1" to enable the Socket Termination interrupt.

ConU_En

R/W

Writing a "1" to enable the Connection Up interrupt.

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7.3.21. Socket Interrupt Low Register (0x2C)

(Read/Write, Default 0x00)

This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is
set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding
enable bit prevents the interrupt from showing.

Table 7-37

Socket Interrupt Low Register Bit Definitions

Bit

Def.

Buff_Emplty

Buff_Full

Data_Avail

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

Table 7-38

Socket Interrupt Low Register Description

Bit

Bit Name

Access

Description

R/W

This interrupt is generated when a timeout condition
occurred while trying to establish a connection.
Writing a "1" to this bit clears the interrupt.

Buff_Empty

R/W

This interrupt is generated when outgoing buffer is
empty. Writing a "1" to this bit clears the interrupt.

Buff_Full

R/W

This interrupt is generated when the outgoing buffer is
full (1023 bytes). Writing a "1" to this bit clears the
interrupt. Do not use this bit in UDP.

Data_Avail

R/W

This interrupt is generated when data is available from
the incoming buffer. Writing a "1" to this bit clears the
interrupt.

7.3.22. Socket Interrupt High Register (0x2D)

(Read/Write, Default 0x00)

Table 7-39

Socket Interrupt High Register Bit Definitions

Bit

Def.

URG

RST

Term

ConU

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

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Table 7-40

Socket Interrupt High Register Description

Bit

Bit Name

Access

Description

URG

R/W

This interrupt is generated when urgent data arrives.
The system interface should read the Urgent Data
Pointer register to see the location of the data. Writing
a "1" to this bit clears the interrupt.

RST

R/W

This interrupt is generated when a TCP peer sends
the socket RST flag indicating that the current TCP
session is not valid. Writing a "1" to this bit clears this
interrupt. When this condition occurs, the hardware no
longer operates and re-initializing the socket is
recommended.

Term

R/W

This interrupt is generated when the socket
connection is terminated and a TCP FIN flag is
received. Writing a "1" to this bit clears the interrupt.

ConU

R/W

This interrupt is generated when a connection is
established. Writing a "1" to this bit clears the
interrupt.

7.3.23. Socket Data Register (0x2E)

(Memory Mapped Read/Write, Default 0x00)

This register is used by a system controller to read incoming data packets and write outgoing data. Data
transmissions start for TCP connections only after a write occurs at 0x30.

7.3.24. TCP Data Send and Buffer Out Length Registers (0x30-0x31)

(Read/Write, Default 0x03FF)

When read, these registers report the amount of space available in the outgoing buffer. Register 0x30
stores the least significant byte; 0x31 stores the most significant byte. Writing any data to 0x30 causes
data transmissions to start on TCP connections.

7.3.25. Buffer In Length Registers (0x32-0x33)

(Read-Only, Default 0x0000)

These read-only registers report the amount of data available in the received data buffer. 0x32 stores the
least significant byte; 0x33 stores the most significant byte.

7.3.26. Urgent Data Pointer Registers (0x34-0x35)

(Read-Only, Default 0x0000)

These read-only registers report the offset to the start of urgent data (as marked through the TCP
header) relative to the incoming data buffer. Register 0x34 stores the least significant byte; 0x35 stores
the most significant byte.

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7.3.27. Their Port Registers (0x36-0x37)

(Read/Write, Default 0x0000)

These registers specify the destination port for an outgoing data packets. For TCP client or UDP mode,
this value must be set prior to activating the socket. For TCP server mode, these registers are
automatically setup on a connection with the peer's port number. Register 0x36 stores the least
significant byte and 0x37 stores the most significant byte.

Table 7-41

Their Port Register Bit Definitions (0x36)

Bit

Def.

Least significant byte of the target port number

Default

0x00

Table 7-42

Their Port Register Bit Definitions (0x37)

Bit

Def.

Most significant byte of the target port number

Default

0x00

7.3.28. Our Port Registers (0x38-0x39)

(Read/Write, Default 0x0000)

These registers are used it indicate the source port for an outgoing data packet. When setting a TCP
client or sending data using UDP, these registers should be set to the proper value. Normally in client
applications, the software increments the value of this register. The TCP and UDP server application
should set these registers to be the value used by the server applications. Register 0x38 stores the least
significant byte; 0x39 stores the most significant byte.

Table 7-43

Our Port Register Bit Definitions (0x38)

Bit

Def.

Least significant byte of the local port number

Default

0x00

Table 7-44

Our Port Register Bit Definitions (0x39)

Bit

Def.

Most significant byte of the local port number

Default

0x00

7.3.29. Socket Status High Register (0x3A)

(Read-Only, Default 0x00)

This register reports the busy status of the socket.

Table 7-45

Socket Status High Register Bit Definitions

Bit

Def.

Snd_Bsy

Default

NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".

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Table 7-46

Socket Status High Register Description

Bit

Bit Name

Access

Description

Snd_Bsy

This bit indicates that the current socket is busy
sending TCP segments. Before the socket is reset,
this bit should be 0.

0 = Socket not busy

1 = Socket busy

7.3.30. Their IP Address Registers (0x3C-0x3F)

(Read/Write, Default 0x00000000)

These registers indicate the destination IP address for the socket. For TCP client or UDP mode, this
value must be set prior to activating the socket. For TCP server mode, these register are automatically
setup on a connection with the peer's IP address The registers can be written in any order.

Table 7-47

Their IP Address Register Bit Definitions (0x3C)

Bit

Def.

Least significant byte of Destination IP address

Default

0x00

Table 7-48

Their IP Address Register Bit Definitions (0x3D)

Bit

Def.

3rd byte of Destination IP address

Default

0x00

Table 7-49

Their IP Address Register Bit Definitions (0x3E)

Bit

Def.

2nd byte of Destination IP address

Default

0x00

Table 7-50

Their IP Address Register Bit Definitions (0x3F)

Bit

Def.

Most significant byte of Destination IP address

Default

0x00

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7.3.31. PPP Control and Status Register (0x60)

(Read/Write, Default 0x00)

This register control the PPP layer and reports its status.

Table 7-51

PPP Control and Status Register Bit Definitions (0x60)

Bit

Def.

PPP_Int

Con_Val

Use_

PAP

TO_Dis

PPP_Int_En

Kick

PPP_En

PPP_Up

/SRst

Default

Table 7-52

PPP Control Status Register Description

Bit

Bit Name

Access

Description

PPP_Int

R/W

PPP Interrupt

This bit indicates that the PPP triggered an interrupt condition.
Read the PPP interrupt code register to determine the cause.
Writing a "1" to this bit position clears the interrupt.

Con_Val

R/W

Connection Valid

This bit indicates to the network stack that the underlying
connection is up and valid.

0 = Connection down
1 = Connection up

Use_PAP

R/W

This bit enables PAP authentication within the PPP protocol. If
enabled, a PAP request is issued after PAP authentication is
negotiated. The PAP string enters through register 0x64.

0 = PAP disabled (default)
1 = PAP enabled

TO_Dis

R/W

Timeouts Disabled

This bit disables the PPP block from timeouts for diagnostic
purposes. It should remain enable for normal operations.

0 = Timeouts enabled (default)
1 = Timeouts disabled

PPP_Int_En

R/W

PPP Interrupt Enable

This bit enables the PPP interrupt.

0 = PPP Interrupt disabled (default)
1 = PPP Interrupt enabled

Kick

PPP Kick Start

When written to a 1, this bit will start the PPP if it falls into a
timeout condition. It clears once the kick operation performs.
This bit is self-clearing.

PPP_En

R/W

PPP Enable

This bit enables the PPP layer. The bit must be set before any
transmissions occur.

0 = PPP disabled (default)
1 = PPP enabled

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Bit

Bit Name

Access

Description

PPP_UP/SRst

R/W

When read, this bit indicates when the PPP layer establishes a
connection.

0 = PPP Connection down

1 = PPP Connection established

When written, this bit will reset the PPP engine. It is self-clearing
and goes not need to be written low for normal operations.

0 = PPP Normal operation

1 = PPP Reset

7.3.32. PPP Interrupt Code (0x61)

(Read-Only, Default 0x00)

This register indicates the interrupt condition that causes the PPP interrupt to trigger.

Table 7-53

PPP Interrupt Code Register Bit Definitions

Bit

Def.

PPP Interrupt Code

Default

Table 7-54

PPP Interrupt Error Codes

Error Code

Definition

0x00

Reserved

0x01

PPP Failed initial LCP negotiations

0x02

PPP Failed NCP negotiations

0x05

PAP Failed negotiations

7.3.33. PPP Max Retry, (0x62)

(Read/Write, Default 0x0A)

This register configures the maximum retry number. This number is used to determine the maximum
number of configuration requests that are sent during the PPP negotiation stage.

Table 7-55

PPP Max Retry Register

Bit

Def.

PPP Maximum Retry

Default

0x0

0xA

NOTE: Reserved bits are signified by a dash (-).

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7.3.34. PAP String (0x64)

(Write-Only)

This write-only register enters the string for the PAP configuration request packet. Enter the string
according to the format shown Table 7-56.

Table 7-56

PAP String Format

Byte

String

[0]

Length of username

[1]

First byte of username

[2]

Second byte of username

[n]

Last byte of username (where n is the length of the username string)

[n+1]

Length of password

[n+2]

First byte of password

[n+m+1]

Last byte of password (where m is the length of the password string)

As an example, if the username string is "joe" and the password is "public", enter the bytes as shown in
Table 7-57.

Table 7-57

PAP String Example

byte:0

0x03

Length of username string

byte:1

0x6a

Character "j"

byte:2

0x6f

Character "o"

byte:3

0x65

Character "e"

byte:4

0x06

Length of password string

byte:5

0x70

Character "p"

byte:6

0x75

Character "u"

byte:7

0x62

Character "b"

byte:8

0x6C

Character "l"

byte:9

0x69

Character "I"

byte:a

0x63

Character "c"

If PAP is used, the Use_PAP bit must be set in the PPP Control and Status register (0x60) prior to
entering the PAP string.

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8. Data Communications

8.1. Overview

The S-7600A chip contains a on-board serial port for physical transports. The data format of the serial
port is fixed at 1 start bit (logic "0"), 8 data bits, 1 stop bit (logic "1") and no parity bits. The data bits are
sent out, least significant bit first. This data format is shown in Figure 8-1. Also included with the serial
port is a 16- byte Receive FIFO and 1-byte Send Buffer.

Figure 8-1

Serial Data Format

8.2. Serial Port Register Map

The following registers are used to communicate with the serial port.

Table 8-1

Serial Port Register Map

Add

Register

Bit Definitions

0x08

Serial_Port_Config

S_DAV

DCD

DSR/

HWFC

CTS

DTR

RTS

SCTL

0x09

Serial_Port_Int

PT_INT

0x0A

Serial_Port_Int_

Mask

PINT_E

DSINT_
EN

0x0B

Serial_Port_Data

Serial Port Data Register

0x0C -
0x0D

BAUD_Rate_Div

BAUD Rate Divider Registers

rxd / txd

start

stop

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8-2

Seiko Instruments Inc.

8.2.1. Hardware Flow Control (RTS/CTS Handshaking)

The Hardware Flow Control is turned off by default. In this mode, data is transmitted independent of the
state of the CTSX signal. While the MPU is in control of the serial port, it can monitor the state of all the
serial port control signals and control when data gets sent or received, either through polling the status
bits or interrupts. It can also control the RTSX signal by asserting the RTS bit in the Serial Port Config
register. When the S-7600A controls the serial port, data will be sent out as soon as it is available from
the PPP layer. When receiving data, the software in the MPU control mode should read the data out of
the 16-byte FIFO fast enough to prevent buffer overflow.

Hardware Flow Control can be turned on by writing a "1" to bit 5 (DSR/HWFC) of the Serial Port Config
Register (0x08). With the hardware flow control turned on, full RTS/CTS handshaking is supported.
When the serial port detects that CTS is de-asserted, it will stop sending data until CTS is reasserted.
Any byte output at the time CTS is de-asserted will complete, but no further bytes will be sent until CTS is
asserted.

In the other direction, the S-7600A will de-assert RTS if the serial port's 16-byte FIFO is half full. This
indicates to the machine on the other end of the serial line to stop transmitting data. The RTS bit will
reassert when the MPU or the S-7600A has read data out of the Receive FIFO and room becomes
empty. If the machine communicating with the S-7600A over the serial port does not support RTS/CTS
handshaking, the Receive FIFO may overflow and data loss will occur.

8.2.2. Serial Port Control

The control of the serial port is turned over to the MPU by default and after any reset condition. In this
mode, any data written to the Serial Port Data register will be sent out and all data received will be made
available to the MPU via this same register. Prior to using the data register, the MPU should set the
BAUD Rate Div register to the proper setting. An interrupt can be triggered when data is available from
the serial port by asserting the PINT_EN bit. When this bit is asserted, an interrupt will trigger any time
that there is data available to be read from the port. If there is more than one byte in the Receive FIFO,
the interrupt will remain active until all bytes are read. An interrupt can also trigger indicating that the
outgoing data byte has been sent, by asserting the DSINT_EN bit. This interrupt will trigger whenever
there is no more data to be sent.

The MPU turns over control to the S-7600A by asserting the SCTL bit in the Serial Port Config register.
When the S-7600A controls the port, the MPU should not access the Serial Port Data register. The S-
7600A chip will automatically send PPP packets to the serial port and read incoming bytes from the serial
port. The serial port interrupts are not valid when the S-7600A controls the port.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

8-3

8.3. TCP/UDP Data Communications

8.3.1. TCP Data Communications

TCP data communications can be performed if the SCTL-bit of the Serial Port Config register (0x08) is
set to "1."
For data transmission, data is written to the Socket Data register (0x2E). The S-7600A stores data in its
outgoing buffer via the Socket Data Register. The address of the outgoing buffer is specified by the
Buffer Out Length register (0x30-0x31). The value of the Buffer Out Length register is 0x03ff when the
outgoing buffer is empty. The value of the Buffer Out Length register decrements each time a byte of
data is written to the Socket Data register (0x2E). After the data is written, if any data is written to the
TCP Data Send register (0x30), the data in the outgoing buffer is processed by TCP protocols and
transmitted. The value of the Buffer Out Length register increases by the value of the number of bytes of
transmitted data and returns to 0x03ff when all data has been sent. In TCP data transmission, the
outgoing buffer has a capacity of 1023 bytes. Datagrams longer than 1023 bytes are split by the MPU
and transmitted in chunks. When the outgoing buffer becomes full (i.e., comes to contain 1023 bytes of
data), the value of the Buffer Out Length register becomes 0x0000. This can be confirmed by checking
the Buff_Full bit in the Socket Config Status Low register (0x22). It can also be confirmed by examining
the Buff_Full bit in the Socket Interrupt Low register (0x2C) following an interrupt. No more than 1023
bytes of data are permitted in the Socket Data register. If data is written to the TCP Data Send register
under these conditions, the data in the outgoing buffer is transmitted. The MPU repeats the procedure of
sending residual data after verifying that the Buffer Out Length register has been reset to 0x03ff.
Transmission of all data in the outgoing buffer can be confirmed by checking the Buff_Empty bit in the
Socket Config Status Low register (0x22), as well as the Buff_Empty bit in the Socket Interrupt Low
register (0x2C) following an interrupt.

When the S-7600A receives TCP data, it applies TCP protocol processing and stores data in the
incoming buffer. The address of the incoming buffer is specified by the Buffer In Length register (0x32-
0x33). The value of the Buffer In Length register is 0x0000 when the incoming buffer is empty.
Otherwise, it increments by a value equal to the number of bytes of the stored data. Data reception is
detected by checking the Data_Avail bit in the Socket Config Status Low register (0x22), Socket Data
Available register (0x28), and the Data_Avail bit in the Socket Interrupt Low register (0x2C) following an
interrupt. Read the Socket Data register (0x2E) while monitoring the Data_Avail bit in the Socket Config
Status Low register. This reads in the received data from the incoming buffer. Each time a byte of data
is read out from the Socket Data register, the value of the Buffer In Length register decrements. When all
data is read out, its value returns to 0x0000. The incoming buffer can hold up to 2047 bytes of data for
TCP data reception. The S-7600A and its peer apply TCP protocols to prevent overflowing incoming
buffers during data reception.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

8-4

Seiko Instruments Inc.

8.3.2. UDP Data Communications

UDP data communications are performed if the SCTL-bit of the Serial Port Config register (0x08) is set to
"1."
For data transmission, data is written to the Socket Data register (0x2E). The S-7600A stores data in its
outgoing buffer via the Socket Data register. The address of the outgoing buffer is specified by the Buffer
Out Length register (0x30-0x31). The value of the Buffer Out Length register is 0x03ff when the outgoing
buffer is empty. The value of the Buffer Out Length register decrements each time a byte of data is
written to the Socket Data register (0x2E). After the data is written, if any data is written to the TCP Data
Send register (0x30), the data stored in the outgoing buffer is processed by UDP protocols and
transmitted. Since the value of the Buffer Out Length register increases by the value of the number of
bytes of transmitted data, it is reset to 0x03ff when all data has been sent. For UDP data transmission,
the outgoing buffer can hold up to 1015 bytes of data. Datagrams longer than 1015 bytes are split by the
MPU and transmitted in chunks. When the outgoing buffer accumulates 1015 bytes of data, the value of
the Buffer Out Length register becomes 0x0008. No more than 1015 bytes of data are permitted in the
Socket Data register. Since this condition is not indicated by the Buff_Full bit in the Socket Config Status
Low register (0x22) or by the Buff_Full bit in the Socket Interrupt Low register (0x2C), the Buffer Out
Length register must be monitored, or supervised in the application layer. If data is written to the TCP
Data Send register under these conditions, the data in the outgoing buffer is transmitted. The MPU
repeats the procedure of sending residual data after checking that the Buffer Out Length register has
been restored to 0x03ff. The transmission of all data in the outgoing buffer can be confirmed by checking
the Buff_Empty bit in the Socket Config Status Low register (0x22) and the Buff_Empty bit in the Socket
Interrupt Low register (0x2C) following an interrupt.
When the S-7600A receives UDP data, it applies UDP protocol processing and stores the processed
data in the incoming buffer after adding 12 bytes of header information. Data reception can be
determined by checking whether the value of the Buffer In Length register equals 0x0000 or a different
value. The Data_Avail bit in the Socket Config Status Low register (0x22), the Socket Data Available
register (0x28), and the Data_Avail bit following an interrupt in the Socket Interrupt Low register (0x2C)
can all indicate data reception. Read the Socket Data register (0x2E) while monitoring the Data_Avail bit
in the Socket Config Status Low register. This fetches the 12 byte header from the incoming buffer,
followed by the data. Table 8-2 shows the header structure.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

8-5

Table 8-12

Header Structure

Byte position from head

Implication of each byte

Remarks

The most significant byte of their IP
address

The second significant byte of their IP
address

The third significant byte of their IP
address

The least significant byte of their IP
address

The most significant byte of their port
number

The least significant byte of their port
number

The most significant byte of our port
number

The least significant byte of our port
number

The most significant byte of UDP
datagram size

The least significant byte of UDP
datagram size

8 bytes of UDP
header are not
included here

The most significant byte of UDP
checksum

The least significant byte of UDP
checksum

Each time a byte of data is read out from the Socket Data register, the value of the Buffer In Length
register decrements. When all data is read out, the register value returns to 0x0000. In UDP data
reception, the incoming buffer has a maximum capacity of 2047 bytes, including the 12-byte header. The
application layer is responsible for using the header information and the buffer control to prevent any
overflow in the two incoming buffers.

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

9-1

Seiko Instruments Inc.

9. Reset Functions

9.1. Overview

The S-7600A has two reset functions which are hardware reset and software reset.

9.1.1. Hardware Reset Function

The S-7600A operates to be synchronous to the CLK signal(clock input). When the RESETX pin set to
low level in two clock period minimum, the S-7600A accept hardware reset input and starts initializing
internal circuit at positive edge timing of forth clock. After the RESETX pin return to high level, the S-
7600A maintains initialized state and turns normal state at positive edge timing of forth clock.

See the Figure 9-1.

Figure 9-1

Hardware Reset Timing

9.1.2. Software Reset Function

The S-7600A is able to initialize the internal circuit by the General Control Register(0x01). Show the reset
timing in case of x80 Family MPU mode. See the Figure 9-2.

Figure 9-2

Software Reset Timing

initialized

2nd

1st

3rd

4th

3rd

2nd

1st

CLK

RESETX

Min. 2 clock

normal

normal state

CLK

BUSYX

WRITEX

SD7 to 0

Address

Data h01

initialized state

x80 Family MPU mode

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

10-1

10. Application Examples

10.1.1. In Case of x80 Family MPU with LCD Controller

Figure 10-1

Example for x80 Family MPU

LCD Controller

(S-4592,etc.)

S-7600A

x80 Family
MPU

-Personal
Computer
-MODEM
-PDC
-PIAFS

Driver/

Receiver

Decoder

WRITEX

READX

SD0 to SD7

RES

D0 to D7

IORQ

A1 to A7

RESET

C86

PSX

D0 to D7

RES

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

10-2

Seiko Instruments Inc.

10.1.2. In Case of 68k Family MPU with LCD Controller

Figure 10-2

Example for 68k Family MPU

LCD Controller

(S-4592,etc.)

S-7600A

68k Family
MPU

-Personal
Computer
-MODEM
-PDC
-PIAFS

Driver/

Receiver

Decoder

R/WX (WRITEX)

E (READX)

SD0 to SD7

RES

R/W

D0 to D7

VMA

A1 to A7

RESET

C86

PSX

D0 to D7

RES

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

10-3

10.1.3. In Case of Serial Interface with LCD Controller

Figure 10-3

Example for Serial Interface

LCD Controller

(S-4592,etc.)

S-7600A

MPU

-Personal
Computer
-MODEM
-PDC
-PIAFS

Driver/

Receiver

SCL (SD6)

SO (SD5)

SI (SD7)

RES

SCLK

SCL

SIN

SOUT

PORT2

PORT1

RESET

C86

READX

RES

PSX

PORT3

BUSY

TCP/IP Network Stack LSI

S-7600A

Hardware Specification Revision 1.3

10-4

Seiko Instruments Inc.

The S7600A TCP/IP Network Stack LSI is based upon iReady's Internet Tuner� technology.
The URL for iReady

s Web site is,

http://www.iready.com

�

The information herein is subject to change without notice.

�

Seiko Instruments Inc. is not responsible for any problems caused by circuits or other diagrams

described herein whose industrial properties, patents or other rights belong to third parties.

�

When the products described herein include Regulated Products subject to The Wassenaar

Arrangement etc., they may not be exported without authorization form the appropriate governmental
authority.

�

The products described herein cannot be used as part of any device or equipment which influences

the human body, such as physical exercise equipment, medical equipment, security system, gas
equipment, vehicle or airplane, without prior written permission of Seiko Instruments Inc.

Seiko Instruments Inc.
1-8, Nakase, Mihama-ku, Chiba-shi, Chiba 261, Japan
Components Sales Div.
Telephone : +81-43-211-1196 Facsimile : +81-43-211-8032
E-mail :

component@sii.co.jp

http://www.sii.co.jp/compo/s7600a/S7600A_TOP.html

Seiko Instruments USA Inc.
Electronic Components Div.
2990 W. Lomita Blvd, Torrance, CA 90505, USA
Telephone : +1-909-934-9334 Facsimile : +1-909-975-5699
E-mail : seiko-ecd@salessupport.com
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