Document Outline
- S-8233C Series
- Cover
- Features
- Applications
- Package
- Block Diagram
- Product Name Structure
- Pin Configurations
- Absolute Maximum Ratings
- Electrical Characteristics
- Measurement Circuits
- Description
- Operation Timing Charts
- Battery Protection IC Connection Example
- Precautions
- Characteristics (typical characteristics)
- Package Drawing
Rev.4.0
_00
BATTERY PROTECTION IC
FOR 3-SERIAL-CELL PACK
S-8233C Series
Seiko Instruments Inc.
1
The S-8233C Series is a series of lithium-ion rechargeable battery
protection ICs incorporating high-accuracy voltage detection circuits and
delay circuits.
The S-8233C series includes the function to measure the status of
battery pack.
It is suitable for a 3-serial-cell lithium-ion battery pack.
Features
(1) Internal high-accuracy voltage detection circuit
Over charge detection voltage
3.80
0.05 V to 4.40 0.05 V
5 mV - step
Over charge release voltage
3.45
0.10 V to 4.40 0.10 V
5 mV - step
(The over charge release voltage can be selected within the range where a difference from over
charge detection voltage is 0 to 0.35 V at 50 mV - Step)
Over discharge detection voltage
2.00
0.08 V to 2.80 0.08 V
50 mV - step
Over discharge release voltage
2.00
0.10 V to 4.00 0.10 V
50 mV - step
(The over discharge release voltage can be selected within the range where a difference from over
discharge detection voltage is 0 to 1.2 V at 50 mV - Step)
Over current detection voltage 1
0.15
0.015 V to 0.50 0.05 V
50 mV - step
(2) High input-voltage device (absolute maximum rating: 26 V)
(3) Indicates Li-ion battery state.
(4) Wide operating voltage range:
2 V to 24 V
(5) The delay time for every detection can be set via an external capacitor.
(6) Three over current detection levels (protection for short-circuiting)
(7) Internal charge/discharge prohibition circuit via the control terminal
(8) The function for charging batteries from 0 V is available.
(9) Low current consumption
Operation 50
A max. (+25 C)
Power-down 0.1
A max. (+25 C)
(10) Lead-free products
Applications
Lithium-ion rechargeable battery packs
Package
Drawing Code
Package Name
Package Tape Reel
16-Pin TSSOP
FT016-A
FT016-A
FT016-A
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
2
Block Diagram
Battery 1
Over charge
Battery 3
Over discharge
Battery 3
Over charge
Battery 2
Over charge
Battery 2
Over discharge
Over charge
delay circuit
Battery 1
Over discharge
Reference
voltage 3
Reference
voltage 2
Reference
voltage 1
Control
Logic
Over current
detection
circuit
Over discharge
delay circuit
Over current1,
delay circuit
Over current
2,3 delay
circuit
-
+
-
+
-
+
-
+
-
+
-
+
DOP
VMP
COVT
CDT
CCT
COP
CTL
VSS
DSO
VC2
ISO
CSO
VC1
VCC
Floating
detection circuit
Over
charge
Over
current
Over
discharge
Figure 1
The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot
be changed via an external capacitor.
If one of the battery voltages becomes higher than the over charge detection voltage (V
CU
), the CSO
terminal goes high.
If one of the battery voltages becomes lower than the over discharge detection voltage (V
DD
), the DSO
terminal goes high.
If S-8233C series detect over current, the ISO terminal goes high.
In normal state each terminal output `Low'.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
3
Product Name Structure
1. Product name
S
-8233C x FT - TB - G
IC direction in tape specifications
*1
Package name (abbreviation)
FT: 16-Pin TSSOP
Serial code
Assigned from A to Z in alphabetical order
*1. Refer to the taping specifications.
2. Product name list
Table1
Model/Item
Over charge
detection
voltage
(V
CU
)
Over charge
release voltage
(V
CD
)
Over discharge
detection
voltage
(V
DD
)
Over discharge
release voltage
(V
DU
)
Over current
detection
voltage1
(V
IOV1
)
0V battery charging
function
S-8233CAFT-TB-G 4.250.05 V 4.050.10 V
2.000.08 V
2.300.10 V
0.250.025 V
-
Remark Please contact the SII marketing department for the products with the detection voltage value other
than those specified above.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
4
Pin Configurations
Table2
No. Name
Description
1
DOP
Connects FET gate for discharge control (CMOS output)
2 NC Non
connect
*1
3
COP
Connects FET gate for charge control (Nch open-drain output)
4
VMP
Detects voltage between VCC to VMP(Over current detection pin)
5
COVT
Connects capacitor for over current detection 1 delay circuit
6
CDT
Connects capacitor for over discharge detection delay circuit
7
CCT
Connects capacitor for over charge detection delay circuit
8
VSS
Negative power input, and connects negative voltage for battery 3
9
CTL
Charge/discharge control signal input
10 DSO Over
discharge
condition signal output
11
VC2
Connects battery 2 negative voltage and battery 3 positive voltage
12
ISO
Over current condition signal output
13
VC1
Connects battery 1 negative voltage and battery 2 positive voltage
14 CSO Over voltage condition signal output
15 NC Non
connect
*1
16 VCC Positive power input and connects battery 1 positive voltage
*1. The NC pin is electrically open. The NC pin can be connected to VCC or VSS
.
16-Pin TSSOP
Top View
COVT
8
7
6
5
3
2
4
1
11
16
9
10
12
14
15
13
DOP
NC
COP
VMP
CDT
CCT
VSS
VCC
NC
CSO
VC1
ISO
VC2
DSO
CTL
Figure 2
Absolute Maximum Ratings
Table3
(Ta
= 25 C unless otherwise specified)
Item Sym.
Applied
Pins Rating
Unit
Input voltage between VCC and VSS
V
DS
-
V
SS
-0.3 to V
SS
+26 V
Input terminal voltage
V
IN
VC1,VC2,CTL,CCT,CDT,COVT
V
SS
-0.3 to V
CC
+0.3 V
VMP Input terminal voltage
V
VMP
VMP V
SS
-0.3 to V
SS
+26 V
CSO,ISO,DSO output terminal voltage
V
OUT
CSO,ISO,DSO V
SS
-0.3 to V
CC
+0.3 V
DOP output terminal voltage
V
DOP
DOP V
SS
-0.3 to V
CC
+0.3 V
COP output terminal voltage
V
COP
COP V
SS
-0.3 to V
VMP
+0.3 V
Power dissipation
P
D
- 300
mW
Operating temperature range
Topr
-
-20 to +70
C
Storage temperature range
Tstg
-
-40 to +125
C
Caution The absolute maximum ratings are rated values exceeding which the product could
suffer physical damage. These values must therefore not be exceeded under any
conditions.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
5
Electrical Characteristics
Table 4 (1 / 2)
(Ta
= 25 C unless otherwise specified)
Item Symbol
Condition Min.
Typ.
Max.
Unit
Measure-
ment
condition
Measure-
ment
circuit
Detection voltage
Over charge detection voltage 1
V
CU1
3.80 to 4.40 Adjustment V
CU1
-0.05 V
CU1
V
CU1
+0.05 V 1
1
Over charge release voltage 1
V
CD1
3.45 to 4.40 Adjustment V
CD1
-0.10 V
CD1
V
CD1
+0.10 V 1
1
Over discharge detection voltage 1
V
DD1
2.00 to 2.80 Adjustment V
DD1
-0.08 V
DD1
V
DD1
+0.08 V 1
1
Over discharge release voltage 1
V
DU1
2.00 to 4.00 Adjustment V
DU1
-0.10 V
DU1
V
DU1
+0.10 V 1
1
Over charge detection voltage 2
V
CU2
3.80 to 4.40 Adjustment V
CU2
-0.05 V
CU2
V
CU2
+0.05 V 2
1
Over charge release voltage 2
V
CD2
3.45 to 4.40 Adjustment V
CD2
-0.10 V
CD2
V
CD2
+0.10 V 2
1
Over discharge detection voltage 2
V
DD2
2.00 to 2.80 Adjustment V
DD2
-0.08 V
DD2
V
DD2
+0.08 V 2
1
Over discharge release voltage 2
V
DU2
2.00 to 4.00 Adjustment V
DU2
-0.10 V
DU2
V
DU2
+0.10 V 2
1
Over charge detection voltage 3
V
CU3
3.80 to 4.40 Adjustment V
CU3
-0.05 V
CU3
V
CU3
+0.05 V 3
1
Over charge release voltage 3
V
CD3
3.45 to 4.40 Adjustment V
CD3
-0.10 V
CD3
V
CD3
+0.10 V 3
1
Over discharge detection voltage 3
V
DD3
2.00 to 2.80 Adjustment V
DD3
-0.08 V
DD3
V
DD3
+0.08 V 3
1
Over discharge release voltage 3
V
DU3
2.00 to 4.00 Adjustment V
DU3
-0.10 V
DU3
V
DU3
+0.10 V 3
1
Over current detection voltage 1
*1
V
IOV1
0.15 to 0.50V Adjustment V
IOV1
0.9 V
IOV1
V
IOV1
1.1 V 4 2
Over current detection voltage 2
V
IOV2
V
CC
Reference
0.54
0.6
0.66
V
4
2
Over current detection voltage 3
V
IOV3
V
SS
Reference
1.0
2.0
3.0
V
4
2
Voltage temperature factor 1
*2
T
COE1
Ta=-20 to 70C
-1.0 0 1.0 mV/C
-
-
Voltage temperature factor 2
*3
T
COE2
Ta=-20 to 70C
-0.5 0 0.5 mV/C
-
-
Delay time
Over charge detection delay time 1
t
CU1
C
CCT
=0.47
F
0.5 1.0 1.5 s 9 6
Over charge detection delay time 2
t
CU2
C
CCT
=0.47
F
0.5 1.0 1.5 s 10 6
Over charge detection delay time 3
t
CU3
C
CCT
=0.47
F
0.5 1.0 1.5 s 11 6
Over discharge detection delay time 1 t
DD1
C
CDT
=0.1
F
20 40 60 ms 9 6
Over discharge detection delay time 2 t
DD2
C
CDT
=0.1
F
20 40 60 ms 10 6
Over discharge detection delay time 3 t
DD3
C
CDT
=0.1
F
20 40 60 ms 11 6
Over current detection delay time 1
t
IOV1
C
COVT
=0.1
F
10 20 30 ms 12 7
Over current detection delay time 2
t
IOV2
-
2 4 8 ms
12 7
Over current detection delay time 3
t
IOV3
FET gate capacitor
=2000 pF
100 300 550
s
12
7
Operating voltage
Operating voltage between VCC and
VSS
*4
V
DSOP
-
2.0
-
24 V -
-
Current consumption
Current consumption (during normal
operation)
I
OPE
V1=V2=V3=3.5
V
-
20 50
A
5 3
Current consumption for cell 1
I
CELL1
V1=V2=V3=3.5
V
-300
0 300 nA 5 3
Current consumption for cell 2
I
CELL2
V1=V2=V3=3.5
V
-300
0 300 nA 5 3
Current consumption for cell 3
I
CELL3
V1=V2=V3=3.5
V
-300
0 300 nA 5 3
Current consumption at power down
I
PDN
V1=V2=V3=1.5
V
-
-
0.1
A
5
3
Internal resistance with 0V battery charging function type
Resistance between VCC and VMP
R
VCM
V1=V2=V3=3.5
V 0.20 0.50 0.80 M
6 3
Resistance between VSS and VMP
R
VSM
V1=V2=V3=1.5
V 0.20 0.50 0.80 M
6 3
Internal resistance without 0V battery charging function type.
Resistance between VCC and VMP
R
VCM
V1=V2=V3=3.5
V 0.40 0.90 1.40 M
6 3
Resistance between VSS and VMP
R
VSM
V1=V2=V3=1.5
V 0.40 0.90 1.40 M
6 3
Input voltage
CTL"H" Input voltage
V
CTL(H)
-
V
CC
x 0.8
-
-
V
-
-
CTL"L" Input voltage
V
CTL(L)
-
-
-
V
CC
x 0.2
V
-
-
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
6
Table 4 (2 / 2)
(Ta
= 25 C unless otherwise specified)
Item Symbol
Condition Min.
Typ.
Max.
Unit
Measure-
ment
condition
Measure-
ment
circuit
Output voltage
DOP"H" voltage
V
DO(H)
I
OUT
=10
A
V
CC
-0.5
-
-
V
7
4
DOP"L" voltage
V
DO(L)
I
OUT
=10
A
-
-
V
SS
+0.1 V
7
4
COP"L" voltage
V
CO(L)
I
OUT
=10
A
-
-
V
SS
+0.1 V
8
5
COP OFF LEAK current
I
COL
V1=V2=V3=4.5
V
-
-
100 nA
14
9
CSO"H" voltage
V
CSO(H)
I
OUT
=0.1
A
V
CC
-0.5
-
-
V
13
8
CSO"L" voltage
V
CSO(L)
I
OUT
=10
A
-
-
V
SS
+0.1 V
13
8
ISO"H" voltage
V
ISO(H)
I
OUT
=0.1
A
V
CC
-0.5
-
-
V
13
8
ISO"L" voltage
V
ISO(L)
I
OUT
=10
A
-
-
V
SS
+0.1 V
13
8
DSO"H" voltage
V
DSO(H)
I
OUT
=0.1
A
V
CC
-0.5
-
-
V
13
8
DSO"L" voltage
V
DSO(L)
I
OUT
=10
A
-
-
V
SS
+0.1 V
13
8
0 V battery charging function
*5
0 V charging start voltage
V
0CHAR
V1=V2=V3=0
V
-
-
1.4 V
15
10
*1. If over current detection voltage 1 is 0.50 V, both over current detection voltages 1 and 2 are 0.54 V to 0.55
V, but V
IOV2
> V
IOV1
.
*2. Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over
discharge detection voltage, and over discharge release voltage.
*3. Voltage temperature factor 2 indicates over current detection voltage.
*4. The DOP and COP logic must be established for the operating voltage.
*5. This spec applies for only 0 V battery charging function available type.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
7
Measurement Circuits
(1) Measurement 1 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V1 from 3.5 V gradually. The V1 voltage
when COP = 'H' is over charge detection voltage 1 (V
CU1
). Decrease V1 gradually. The V1 voltage when
COP = 'L' is over charge release voltage 1 (V
CD1
). Further decrease V1. The V1 voltage when DOP = 'H'
is over discharge voltage 1 (V
DD1
). Increase V1 gradually. The V1 voltage when DOP = 'L' is over
discharge release voltage 1 (V
DU1
).
Remark The voltage change rate is 150 V/s or less.
(2) Measurement 2 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V2 from 3.5 V gradually. The V2 voltage
when COP = 'H' is over charge detection voltage 2 (V
CU2
). Decrease V2 gradually. The V2 voltage when
COP = 'L' is over charge release voltage 2 (V
CD2
). Further decrease V2. The V2 voltage when DOP = 'H'
is over discharge voltage 2 (V
DD2
). Increase V2 gradually. The V2 voltage when DOP = 'L' is over
discharge release voltage 2 (V
DU2
).
Remark The voltage change rate is 150 V/s or less.
(3) Measurement 3 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V3 from 3.5 V gradually. The V3 voltage
when COP = 'H' is over charge detection voltage 3 (V
CU3
). Decrease V3 gradually. The V3 voltage when
COP = 'L' is over charge release voltage 3 (V
CD3
). Further decrease V3. The V3 voltage when DOP = 'H'
is over discharge voltage 3 (V
DD3
). Increase V3 gradually. The V3 voltage when DOP = 'L' is over
discharge release voltage 3 (V
DU3
).
Remark The voltage change rate is 150 V/s or less.
(4) Measurement 4 Measurement circuit 2
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V4 from 0 V gradually. The V4
voltage when DOP = 'H' and COP = 'H, is over current detection voltage 1 (V
IOV1
).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at V
SS
,
increase V4 from 0 V gradually. The V4 voltage when DOP = 'H" and COP = 'H' is over current detection
voltage 2 (V
IOV2
).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at V
SS
,
increase V4 gradually from 0 V at 400
s to 2 ms. The V4 voltage when DOP = 'H" and COP = 'H' is over
current detection voltage 3 (V
IOV3
).
(5) Measurement 5 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition and measure current
consumption. I1 is the normal condition current consumption (I
OPE
), I2, the cell 2 current consumption
(I
CELL2
), and I3, the cell 3 current consumption (I
CELL3
).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.5 V under over discharge condition. Current
consumption I1 is power-down current consumption (I
PDN
).
(6) Measurement 6 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 10.5 V under normal condition. V4/I4 is the internal
resistance between VCC and VMP (R
VCM
).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.1 V under over discharge condition. (4.5-V4)/I4 is the
internal resistance between VSS and VMP (R
VSM
).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
8
(7) Measurement 7 Measurement circuit 4
Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition. Increase V5
from 0 V gradually. The V5 voltage when I5 = 10
A is DOP'L' voltage (V
DO (L)
).
Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V4 to V
IOV2
+0.1 V under over current condition.
Increase V6 from 0 V gradually. The V6 voltage when I6 = 10
A is the DOP'H' voltage (V
DO (H)
).
(8) Measurement 8 Measurement circuit 5
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5
voltage when I5 = 10
A is the COP'L' voltage (V
CO (L)
).
(9) Measurement 9 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V1 from 3.5 V to 4.5 V immediately (within 10
s). The time after V1 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 1 (t
CU1
).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V1 from 3.5 V to 1.9 V immediately (within 10
s). The time after V1 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 1
(t
DD1
).
(10) Measurement 10 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V2 from 3.5 V to 4.5 V immediately (within 10
s). The time after V2 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 2 (t
CU2
).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V2 from 3.5 V to 1.9 V immediately (within 10
s). The time after V2 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 2
(t
DD2
).
(11) Measurement 11 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V3 from 3.5 V to 4.5 V immediately (within 10
s). The time after V3 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 3 (t
CU3
).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V3 from 3.5 V to 1.9 V immediately (within 10
s). The time after V3 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 3
(t
DD3
).
(12) Measurement 12 Measurement circuit 7
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.55 V
immediately (within 10
s). The time after V4 becomes 0.55 V until DOP goes 'H' is the over current
detection delay time 1 (t
IOV1
).
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.75 V
immediately (within 10
s). The time after V4 becomes 0.75 V until DOP goes 'H' is the over current
detection delay time 2 (t
IOV2
)
Set S1 to ON to inhibit over discharge detection. Set V1, V2, V3 to 4.0 V and increase V4 from 0 V to 6.0
V immediately (within 1
s) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V4 becomes
6.0 V until DOP goes 'H' is the over current detection delay time 3 (t
IOV3
).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
9
(13) Measurement 13 Measurement circuit 8
Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V ,and V4, V6, to 0 V under normal
condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10
A is the CSO'L' voltage
(V
CSO(L)
)
Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V4, V6 to 0 V under normal
condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10
A is the ISO'L' voltage (V
ISO(L)
).
Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V4, V6 to 0 V under normal
condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10
A is the DSO'L' voltage
(V
DSO(L)
).
Set S1 to ON, S2, S3, S4,S5, and S6 to OFF, V1 to 4.5V, V2, and V3 to 3.5 V, V5, and V6 to 0 V under
over voltage condition. Increase V4 from 0 V gradually. The V4 voltage when I4 = 0.1
A is the CSO'H'
voltage (V
CSO(H)
).
Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V1, V2 and V3 to 3.5 V, V5 to 0 V, V6 to V
IOV2
+0.1V under
over current condition. Increase V4 from 0 V gradually. The V4 voltage when I4 = 0.1
A is the ISO'H'
voltage (V
ISO(H)
).
Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V1 to 1.9V,V2 and V3 to 3.5 V, V5 and V6 to 0 V under
over discharge condition. Increase V4 from 0 V gradually. The V4 voltage when I4 = 0.1
A is the
DSO'H' voltage (V
DSO(H)
).
(14) Measurement 14 Measurement circuit 9
Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is COP
OFF LEAK current (I
COL
).
(15) Measurement 15 Measurement circuit 10
Set V1, V2, and V3 to 0 V, and V8 to 2 V, and decrease V8 gradually. The V8 voltage when COP = 'H'
(V
SS
+ 0.1 V or higher) is the 0 V charge start voltage (V
0CHAR
).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
10
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
V1
1M
S-8233C
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
V1
V4
1M
S-8233C
Measurement circuit 1
Measurement circuit 2
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
I2
I3
S1
I1
I4
V1
V4
S-8233C
CCT
VSS
DOP
VC2
COP
VMP
VC1
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
V1
V5
S1
I5
S2
I6
V6
V4
CTL
S-8233C
Measurement circuit 3
Measurement circuit 4
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
V5
I5
V1
V4
S-8233C
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
V1
V3
V2
CSO
C3
C2
C1
1M
C1=0.47
F
C2=0.1
F
C3=0.1
F
S-8233C
Measurement circuit 5
Measurement circuit 6
Figure 3 (1/2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
11
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
V1
V3
V2
CSO
C3
C2
S1
C1
C1=0.47
F
C2=0.1
F
C3=0.1
F
V4
1M
S-8233C
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
CSO
V3
V2
V1
V5
V4
S1
S5
S6
S2
S4
S3
I5
I4
V6
S-8233C
Measurement circuit 7
Measurement circuit 8
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
V1
V3
V2
CSO
I1
S-8233C
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
DSO
ISO
V1
V3
V2
CSO
1M
V4
S-8233C
Measurement circuit 9
Measurement circuit 10
Figure 3 (2/2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
12
Description
Remark Refer to " Battery Protection IC Connection Example".
Normal condition
This IC monitors the voltages of the three serially-connected batteries and the discharge current to control
charging and discharging. If the voltages of all the three batteries are in the range from the over
discharge detection voltage (V
DD
) to the over charge detection voltage (V
CU
), and the current flowing
through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal or
lower than over current detection voltage 1), the charging and discharging FETs turn on. In this condition,
charging and discharging can be carried out freely. This condition is called the normal condition. In this
condition, output voltage of CSO,ISO and DSO go `low'. VCC terminals are shorted by the R
VCM
resistor.
Over current condition
This IC is provided with the three over current detection levels (V
IOV1
,V
IOV2
and V
IOV3
) and the three over
current detection delay time (t
IOV1
,t
IOV2
and t
IOV3
) corresponding to each over current detection level.
If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage is
equal to or higher than the over current detection voltage) during discharging under normal condition and
it continues for the over current detection delay time (t
IOV
) or longer, the discharging FET turns off to stop
discharging. This condition is called an over current condition. The VMP and VCC terminals are shorted
by the R
VCM
resistor at this time. The charging FET turns off.
When the discharging FET is off and a load is connected, the VMP terminal voltage equals the V
SS
potential. In this condition, output voltage of ISO goes `High'.
The over current condition returns to the normal condition when the load is released and the impedance
between the EB- and EB+ terminals (see Figure 8 for a connection example) is 100 M
or higher. When
the load is released, the VMP terminal, which and the VCC terminal are shorted with the R
VCM
resistor,
goes back to the V
CC
potential. The IC detects that the VMP terminal potential returns to over current
detection voltage 1 (V
IOV1
) or lower (or the over current detection voltage 2 (V
IOV2
) or lower if the COVT
terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the normal
condition. At that time, output voltage of ISO goes `Low'.
Over charge condition
If one of the battery voltages becomes higher than the over charge detection voltage (V
CU
) during
charging under normal condition and it continues for the over charge detection delay time (t
CU
) or longer,
the charging FET turns off to stop charging. This condition is called the over charge condition. The 'H'
level signal is output to the conditioning terminal corresponding to the battery which exceeds the over
charge detection voltage until the battery becomes equal to lower than the over charge release voltage
(V
CD
). In this condition, output voltage of CSO is `High'. The VMP and VCC terminals are shorted by the
R
VCM
resistor under the over charge condition.
The over charge condition is released in two cases. The output voltage of CSO terminal changes to `L'
when the over charge condition is released.
1) The battery voltage which exceeded the over charge detection voltage (V
CU
) falls below the over
charge release voltage (V
CD
), the charging FET turns on and the normal condition returns.
2) If the battery voltage which exceeded the over charge detection voltage (V
CU
) is equal or higher than
the over charge release voltage (V
CD
), but the charger is removed, a load is placed, and discharging
starts, the charging FET turns on and the normal condition returns.
The release mechanism is as follows: the discharge current flows through an internal parasitic diode of
the charging FET immediately after a load is installed and discharging starts, and the VMP terminal
voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC detects this
voltage (over current detection voltage 1 or higher), releases the over charge condition and returns to the
normal condition.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
13
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (V
DD
) during discharging
under normal condition and it continues for the over discharge detection delay time (t
DD
) or longer, the
discharging FET turns off and discharging stops. This condition is called the over discharge condition. In
this condition, output voltage of DSO goes `High'. When the discharging FET turns off, the VMP terminal
voltage becomes equal to the V
SS
voltage and the IC's current consumption falls below the power-down
current consumption (I
PDN
). This condition is called the power-down condition. The VMP and VSS
terminals are shorted by the R
VSM
resistor under the over discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
or higher than the over discharge release voltage (V
DU
) in this condition, the over discharge condition
changes to the normal condition. In this condition, output voltage of DSO goes `Low'.
Delay circuits
The over charge detection delay time (t
CU1
to t
CU3
), over discharge detection delay time (t
DD1
to t
DD3
), and
over current detection delay time 1 (t
IOV1
) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min. Typ. Max.
t
CU
[s] =Delay factor ( 1.07, 2.13, 3.19)C4 [uF]
t
DD
[s] =Delay factor ( 0.20, 0.40, 0.60)C5 [uF]
t
IOV1
[s]=Delay factor ( 0.10, 0.20, 0.30)C6 [uF]
Caution The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
delay time cannot be changed via an external capacitor.
CTL terminal
If the CTL terminal is floated under normal condition, it is pulled up to the V
CC
potential in the IC, and both
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the R
VCM
resistor.
When the CTL terminal becomes equal to V
SS
potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin ('L' level) and VSS is generated through the external filter
(R
VSS
and C
VSS
) as a result of input voltage fluctuations.
0 V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V
0CHAR
) or higher is applied to between VMP and VSS by connecting
the charger, the charging FET gate is fixed to V
SS
potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (V
DU
), the normal condition returns.
CAUTION In the products without 0 V battery charging function, the resistance between VCC and
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that over charge detection voltage increases by the drop voltage
of R5 (see Figure 8 for a connection example) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without
0 V battery charging function.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
14
Voltage temperature factor
Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over
discharge detection voltage, and over discharge release voltage.
Voltage temperature factor 2 indicates over current detection voltage.
The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 4.
V
CU25
Ex. Voltage temperature factor of over charge detection voltage
-20 25
+0.1 mV/C
V
CU
[V]
V
CU25
is the over charge detection voltage at 25
C
70
Ta [
C]
-0.1 mV/C
Figure 4
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
15
Operation Timing Charts
1. Over charge detection
&
V1 battery
Hi-z
Hi-z
Hi-z
Hi-z
V2 battery
V3 battery
V
CU
V
CD
V
DU
V
DD
Battery
voltage
DOP
terminal
V
CC
V
SS
V
SS
V
CHA
V
CC
V
IOV1
V
SS
COP
terminal
VMP
terminal
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
CSO
terminal
DSO
terminal
ISO
terminal
Delay
Delay
Delay
Delay
Delay
Charger
connected
Load
connected
Mode
*1
*1. Normal mode, Over charge mode, Over discharge mode, Over current mode
Remark The charger is assumed to charge with a constant current. V
CHA
indicates the open voltage of the charger.
Figure 5
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
16
2. Over discharge detection
Hi-z
V1 battery
V2 battery
V3 battery
V
CU
V
CD
V
DU
V
DD
Battery
voltage
DOP
terminal
V
CC
V
SS
COP
terminal
VMP
terminal
V
CHA
V
CC
V
IOV1
V
SS
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
CSO
terminal
DSO
terminal
ISO
terminal
Charger
connected
Load
connected
Mode*1
Delay
Delay
Delay
Delay
Delay
*1. Normal mode, Over charge mode, Over discharge mode, Over current mode
Remark The charger is assumed to charge with a constant current. V
CHA
indicates the open voltage of the charger.
Figure 6
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
17
3. Over current detection
Hi-z
Delay t
IOV1
CTL terminal
V
SS
V
CC
Charge/discharge
inhibit
Hi-z
Hi-z
Hi-z
CTL terminal
V
CC
V
SS
V1, V2, and V3 batteries
V
CU
V
CD
V
DU
V
DD
Battery
voltage
DOP
terminal
V
CC
V
SS
V
SS
COP
terminal
VMP
terminal
Charger
connected
Load
connected
Mode
*1
V
CC
V
IOV1
V
IOV2
V
IOV3
Delay t
IOV2
Delay t
IOV2
Delay t
IOV3
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
CSO
terminal
DSO
terminal
ISO
terminal
*1. Normal mode, Over charge mode, Over discharge mode, Over current mode
Figure 7
When the S-8233C series detects over current 1 or over current 2, ISO terminal goes `High'.
Delay time from load shorted to ISO terminal goes `High' is Tiov2( at that case delay time isn't Tiov3).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
18
Battery Protection IC Connection Example
Over charge delay
time setting
Over current delay
time setting
Over discharge delay
time setting
CTL terminal voltage
GND: Normal operation
Floating or V
CC
: Inhibit
charging and discharging
High: Inhibit over
discharge detection
FET-C
EB+
EB-
S-8233C series
R1
VSS
DOP
CTL
VC2
VMP
VC1
C6
CCT
COVT
CDT
Battery 1
Battery 3
Battery 2
VCC
CD1
CD3
CD2
R2
C1
C2
C3
COP
Nch open
drain
FET-A
C4
R3
R6
10 k
R5
1 M
C5
FET-B
Over charge
Condition
Over current
Condition
Over discharge
Condition
1 k
R7
Figure 8
[Description of Figure 8]
The over charge detection delay time (t
CU1
to t
CU3
), over discharge detection delay time (t
DD1
to t
DD3
), and
over current detection delay time (t
IOV1
) are changed with external capacitors (C4 to C6). See the electrical
characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100 k
to
1 M
resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 k
to 50 k resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the
over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of battery
voltage when the over current occurs. In this case, a charger must be connected to return to the normal
condition. To prevent this, connect an at least 0.01
F capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS, the
delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1
A or less. If
over discharge is inhibited by using this FET, the current consumption does not fall below 0.1
A even
when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1 k
or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than V
CC
voltage. Connect a 300
to
5 k
resister. If the CTL terminal voltage never greater than the V
CC
voltage (ex. R7 connect to V
SS
),
without R7 resister is allowed.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
19
Caution 1. The above constants may be changed without notice.
2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233C series
with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary.
3. It has not been confirmed whether the operation is normal or not in circuits other than
the above example of connection. In addition, the example of connection shown above
and the constant do not guarantee proper operation. Perform through evaluation using
the actual application to set the constant.
Precautions
If a charger is connected in the over discharge condition and one of the battery voltages becomes
equal to or higher than the over charge release voltage (V
CU
) before the battery voltage which is
below the over discharge detection voltage (V
DD
) becomes equal to or higher than the over discharge
release voltage (V
DU
), the over discharge and over charge conditions are entered and the charging
and discharging FETs turn off. Both charging and discharging are disabled. If the battery voltage
which was higher than the over charge detection voltage (V
CU
) falls to the over charge release voltage
(V
CD
) due to internal discharging, the charging FET turns on.
If the charger is detached in the over charge and over discharge condition, the over charge condition
is released, but the over discharge condition remains. If the charger is connected again, the battery
condition is monitored after that. The charging FET turns off after the over charge detection delay
time, the over charge and over discharge conditions are entered.
If any one of the battery voltages is equal to or lower than the over discharge release voltage (V
DU
)
when they are connected for the first time, the normal condition may not be entered. If the VMP
terminal voltage is made equal to or higher than the V
CC
voltage (if a charger is connected), the
normal condition is entered.
If the CTL terminal floats in power-down mode, it is not pulled up in the IC, charging and discharging
may not be inhibited. However, the over discharge condition becomes effective. If the charger is
connected, the CTL terminal is pulled up, and charging and discharging are inhibited immediately.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
20
Characteristics
(typical characteristics)
1. Detection voltage temperature characteristics
4.15
4.25
4.35
-40
-20
0
20
40
60
80
100
V
CU
=4.25[V]
Ta(C)
V
CU
(V
)
Overcharge detection voltage vs. temperature
4.00
4.10
4.20
-40
-20
0
20
40
60
80
100
V
CD
=4.10[V]
Ta(C)
V
CD
(V
)
Overcharge release voltage vs. temperature
2.25
2.35
2.45
-40
-20
0
20
40
60
80
100
V
DD
=2.35[V]
Ta(C)
V
DD
(V
)
Overdischarge detection voltage vs. temperature
2.75
2.85
2.95
-40
-20
0
20
40
60
80
100
V
DU
=2.85[V]
Ta(C)
V
DU
(V
)
Overdischarge release voltage vs. temperature
0.25
0.30
0.35
-40
-20
0
20
40
60
80
100
V
IOV1
=0.3 [V]
Ta(C)
V
IO
V
1
(V
)
Overcurrent1 detection voltage vs. temperature
0.55
0.60
0.65
-40
-20
0
20
40
60
80
100
V
IOV2
=0.6 [V]
Ta(C)
V
IO
V
2
(V
)
Overcurrent2 detection voltage vs. temperature
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.4.0
_00
S-8233C Series
Seiko Instruments Inc.
21
2. Current consumption temperature characteristics
0
25
50
-40
-20
0
20
40
60
80
100
V
CC
=10.5 [V]
Ta(C)
I
OP
E
(u
A)
Current consumption vs. temperature in normal mode
0.0
0.5
1.0
-40
-20
0
20
40
60
80
100
V
CC
=4.5 [V]
Ta(C)
I
PD
N
(n
A
)
Current consumption vs. temperature in power-down mode
3. Delay time temperature characteristics
0.5
1.0
1.5
-40
-20
0
20
40
60
80
100
C=0.47[uF]
V
CC
=11.5 [V]
Ta(C)
t
CU
(s
)
Overcharge detection time vs. temperature
20
40
60
-40
-20
0
20
40
60
80
100
C=0.1[uF]
V
CC
=8.5 [V]
Ta(C)
t
DD
(m
s
)
Overdischarge detection time vs. temperature
10
20
30
-40
-20
0
20
40
60
80
100
C=0.1[uF]
V
CC
=10.5 [V]
Ta(C)
t
IO
V
1
(m
s
)
Overcurrent1 detection time vs. temperature
2
5
8
-40
-20
0
20
40
60
80
100
V
CC
=10.5 [V]
Ta(C)
t
IO
V2
(m
s
)
Overcurrent2 detection time vs. temperature
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Rev.4.0
_00
Seiko Instruments Inc.
22
0.10
0.25
0.40
-40
-20
0
20
40
60
80
100
V
CC
=6.0 [V]
Ta(C)
t
IO
V
3
(m
s
)
Overcurrent3 (load short) detection time vs. temperature
4. Delay time vs. power supply voltage
0.0
0.5
1.0
3
6
9
12
15
VCC [V]
t
IO
V
3
(m
s
)
Ta=25[
C]
Over current 3 (load short) detection time vs. power supply voltage
Caution Please design all applications of the S-8233C Series with safety in mind.
0.170.05
9
1
8
16
5.10.2
0.220.08
0.65
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
No. FT016-A-P-SD-1.1
FT016-A-P-SD-1.1
TSSOP16-A-PKG Dimensions
4.00.1
2.00.1
1.5
+0.1
-0
1.60.1
8.00.1
4.20.2
6.5
+0.4
-0.2
0.30.05
1.50.1
(7.2)
No.
TITLE
SCALE
UNIT
mm
8
1
9
16
Seiko Instruments Inc.
No. FT016-A-C-SD-1.1
FT016-A-C-SD-1.1
TSSOP16-A-Carrier Tape
Feed direction
No.
TITLE
SCALE
UNIT
mm
17.41.0
21.41.0
17.4
+2.0
-1.5
2.00.5
13.00.2
210.8
Seiko Instruments Inc.
No. FT016-A-R-SD-1.1
FT016-A-R-SD-1.1
TSSOP16-A- Reel
Enlarged drawing in the central part
QTY.
2,000
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
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