Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
SMBus
SPI Bus
5-Chnl
PCA
16 kB
FLASH
1024 Byte
XRAM
VDD
Monitor
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timers
0,1,2
Timer 3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P
1
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
D
r
v
P
3
D
r
v
P
2
D
r
v
C
R
O
S
S
B
A
R
S
W
I
T
C
H
AV+
AV+
VDD
VDD
DGND
DGND
DGND
DGND
AGND
AGND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
256 Byte
RAM
WDT
ADC
100 ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
TEMP
SENSOR
VREF
CP0
CP1
VREF
NC
NC
C8051F019
25 MIPS, 16 kB Flash, 10-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 100 ksps
-
8 external inputs; programmable as single-ended or differential
-
Data-dependent windowed interrupt generator
-
Built-in temperature sensor (3 C)
Two Comparators
-
16 programmable hysteresis values
-
Configurable to generate interrupts or reset
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-
Provides breakpoints, single stepping, watchpoints, stack monitor
-
Inspect/modify memory and registers
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
IEEE1149.1 compliant boundary scan
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
Up to 25 MIPS throughput with 25 MHz system clock
-
Expanded interrupt handler
Memory
-
1280 bytes data RAM
-
16 kB Flash; in system programmamble in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
-
16 port I/O; all are 5 V tolerant
-
Hardware SMBusTM (I2CTM compatible), SPITM, and UART serial ports
available concurrently
-
Programmable 16-bit counter/timer array with five capture/compare
modules
-
4 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
Clock Sources
-
Internal programmable oscillator: 216 MHz
-
External oscillator: Crystal, RC, C, or Clock
-
Can switch between clock sources on-the-fly
Supply Voltage: 2.8 to 3.6 V
-
Typical operating current: 12.5 mA at 25 MHz
-
Multiple power saving sleep and shutdown modes
48-Pin TQFP
Temperature Range: 40 to +85 C
Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F019
25 MIPS, 16 kB Flash, 10-Bit ADC, 48-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T
A
= 40 to +85 C, V
DD
= 2.8 V unless otherwise specified)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Supply
Voltage
2.8 3.6
V
Supply Current
(CPU active)
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
12.5
0.5
20
mA
mA
A
Supply Current
(shutdown)
Oscillator not running
10
A
Clock Frequency Range
DC
25
MHz
A/D CONVERTER
Resolution
10
bits
Integral Nonlinearity
1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Signal-to-Noise Plus
Distortion
59
61
dB
Throughput Rate
100
ksps
Input Voltage Range
0
V
REF
V
COMPARATORS
Supply Current
(each comparator)
1.5
A
Response Time
(CP+) (CP-) = 100 mV
4
s
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
1.00
0.22
9.00
7.00
0.50
9.00
7.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
E
E1
D
D1
48
1
A1
e
b
PIN 1
IDENTIFIER
A2
A
C8051F005DK Development Kit
PDF 
ZIP