General Purpose
Copyright 2004 by Silicon Laboratories
6.15.2004
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
8 kB FLASH
256 byte
RAM
VDD
Monitor
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timer 0
Timer 1
Timer 2
CP0
CP1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
P
1
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P
0
D
r
v
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P
3
D
r
v
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7
P
2
D
r
v
CP0+
CP0-
CP1+
CP1-
P
0
M
U
X
VDD
VDD
GND
GND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Internal
Oscillator
Analog/Digital
Power
Debug HW
P
1
M
U
X
CP0
CP1
P
2
M
U
X
SPI
NC
NC
NC
NC
1024 byte
XRAM
MONEN
WDT
SYSCLK
C8051F236
25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU
Analog Peripherals
Two comparators
-
Programmable hysteresis
-
Configurable to generate interrupts or reset
V
DD
Monitor and Brown-out Detector
On-Chip JTAG Debug
-
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
-
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
Fully compliant with IEEE 1149.1 specification
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 9 mA at 25 MHz
-
Typical stop mode current: <0.1 uA
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
Up to 25 MIPS throughput with 25 MHz system clock
-
Expanded interrupt handler; up to 21 interrupt sources
Memory
-
1280 bytes data RAM
-
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digital Peripherals
-
32 port I/O; all are 5 V tolerant
-
Hardware SPITM and UART serial ports available concurrently
-
3 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
Clock Sources
-
Internal programmable oscillator: 216 MHz
-
External oscillator: Crystal, RC, C, or Clock
-
Can switch between clock sources on-the-fly
48-Pin TQFP
-
Temperature Range: 40 to +85 C
General Purpose
Copyright 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F236
25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T
A
= 40 to +85 C, V
DD
= 2.7 V unless otherwise specified unless otherwise specified)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Supply
Voltage
2.7 3.6
V
Supply Current (CPU
active)
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz; V
DD
Monitor Disabled
9
0.4
11
mA
mA
A
Supply Current
(shutdown)
Oscillator not running; V
DD
Monitor
Enabled
Oscillator not running; V
DD
Monitor
Disabled
10
0.1
A
A
Clock Frequency Range
DC
25
MHz
COMPARATORS
Supply Current
(each comparator)
1.5
A
Response Time
(CP+) (CP-) = 100 mV
4.0
s
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
1.00
0.22
9.00
7.00
0.50
9.00
7.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
E
E1
D
D1
48
1
A1
e
b
PIN 1
IDENTIFIER
A2
A
C8051F226DK Development Kit
PDF 
ZIP