1
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
s
99.9% Voltage Conversion Efficiency
s
+1.15V to +5.3V Input Voltage Range
s
+1.15 V
IN
Guaranteed Start-up
s
Inverts Input Supply Voltage
s
700
A Quiescent Current
s
25mA Output Current
s
500kHz Operating Frequency
s
Ideal for +3.6V Lithium Ion Battery
Applications
s
Reverse Battery Protection
s
5-pin SOT23 Package
s
19
Output Resistance
s
0.1 or 0.33
F Capacitors
High Speed, High Efficiency Voltage Inverter
SP6832
DESCRIPTION
The SP6832 device is a CMOS Charge Pump Voltage Inverter that can be implemented
in designs requiring a negative voltage from a positive source as low as 1.15V. The SP6832
device is ideal for both battery-powered and board level voltage conversion applications
with a typical operating current of 700mA at a 5V supply. The SP6832 can output 25mA with
a voltage drop of 500mV. These devices combine a low quiescent current with high efficiency
of 85-90% over most of its load range. Applications include cell phones, PDAs, medical
instruments and other portable equipment. The SP6832 is available in a space-saving 5-pin
SOT23 Package.
C1-
V
OUT
V
IN
C1+
GND
SP6832
5
3
2
1
4
2
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
SPECIFICATIONS FOR THE SP6832
V
IN
= +5.0V, C1 = C2 = C3 = 0.33
F and T
AMB
= 25
o
C unless otherwise noted. The circuit found in
Figure 14 was
used to obtain the following typical performance characteristics (unless otherwise noted).
NOTE 1: V
OUT
= -V
IN
+200mV
NOTE 2: Capacitors are approximately 20% of the output impedance where ESR =
NOTE 3: Power Efficiency (Ideal) =
V
OUT
x I
OUT
-V
IN
x (-V
IN
/R
L
)
NOTE 4: Power Efficiency (Actual) =
V
OUT
x I
OUT
V
IN
x I
IN
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
V
IN
.....................................................................................-0.3V to +5.6V
V
OUT
...................................................................................-5.6V to +0.3V
V
OUT
Short Circuit to GND.................................................Indefinite
I
OUT
...................................................................................................50mA
Storage Temperature.....................................................-65C to +150C
Power Dissipation per Package
5-pin SOT (derate 4.35mW/
o
C above +70
o
C).............................400mW
Lead Temperature (Soldering)....................................................300
o
C
ESD Rating...............................................2kV Human Body Model
R
E
T
E
M
A
R
A
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S
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6
8
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3
.
5
V
R
L
k
0
1
=
T
,
B
M
A
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o
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,
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5
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=
R
L
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,
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C
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8
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C
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=
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r
r
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y
l
p
p
u
S
7
.
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4
.
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A
m
T
B
M
A
0
4
-
=
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5
8
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o
t
C
o
=
L
R
,
C
e
c
n
a
t
s
i
s
e
R
t
u
p
t
u
O
9
1
5
4
I
T
U
O
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e
t
o
N
,
A
m
5
2
o
t
A
m
5
=
y
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u
q
e
r
F
r
o
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s
O
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.
9
9
%
R
L
=
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r
e
w
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9
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O
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e
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,
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m
5
=
)
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a
u
t
c
A
(
y
c
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e
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O
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e
t
o
N
,
A
m
5
=
1
f
OSC
x C
3
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
PIN ASSIGNMENTS
Pin 1-- V
OUT
-- Inverting charge pump output.
Pin 2 -- V
IN
-- Input to the positive power
supply.
Pin 3 -- C1- -- Negative terminal to the charge
pump capacitor.
Pin 4 -- GND -- Ground reference.
Pin 5 -- C1+ -- Positive terminal to the charge
pump capacitor.
PINOUT
C1-
V
OUT
V
IN
C1+
GND
SP6832
5
3
2
1
4
Figure 1. Output Resistance vs. Supply Voltage with
a 5mA load
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= +5.0V, C1 = C2 = C3 = 0.33
F and T
AMB
= 25
o
C unless otherwise noted. The circuit found in
Figure 14 was
used to obtain the following typical performance characteristics (unless otherwise noted).
45
50
0
5
10
15
20
25
30
35
40
1.5 2 2.5 3 3.5 4
4.5 5 5.5
(V)
R
OUT
(
)
Figure 2. Output Resistance vs. Temperature with
a 25mA load
0
5
10
15
20
25
30
-60 -40 -20 0
20 40 60 80 100
temperature
O
C
R
OUT
(
)
4
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Figure 6. Output Voltage Ripple vs. Capacitance
Figure 3. Charge Pump Frequency vs. Supply Voltage
Figure 4. Charge Pump Frequency vs. Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= +5.0V, C1 = C2 = C3 = 0.33
F and T
AMB
= 25
o
C unless otherwise noted. The circuit found in
Figure 14 was
used to obtain the following typical performance characteristics (unless otherwise noted).
Figure 5. Output Current vs. Capacitance
0
100
200
300
400
500
600
700
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
IN
(V)
fpump (kHz)
0
100
200
300
400
500
600
700
-60 -40 -20 0
20 40 60 80 100
temperature
O
C
fpump (kHz)
0
100
200
300
400
500
600
700
0
0.1
0.2
0.3
Capacitance (
F)
Vripple (mV p-p)
V
IN
= 5V, V
OUT
= -3.7V
V
IN
= 4.2, V
OUT
= -3.2
V
IN
= 2V, V
OUT
= -1.5V
0
10
20
30
40
50
60
70
80
0
0.1
0.2
0.3
Capacitance (
F)
I
OUT
(mA)
V
IN
= 5V, V
OUT
= -3.7V
V
IN
= 4.2, V
OUT
= -3.2
V
IN
= 2V, V
OUT
= -1.5V
5
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Figure 10. Voltage Efficiency vs. Output Current with
0.1
F Capacitors
Figure 8. Output Voltage vs. Output Current with
0.1
F Capacitors
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= +5.0V, C1 = C2 = C3 = 0.33
F and T
AMB
= 25
o
C unless otherwise noted. The circuit found in
Figure 14 was
used to obtain the following typical performance characteristics (unless otherwise noted).
Figure 7. Supply Current vs. Supply Voltage
Figure 9. Power Efficiency vs. Output Current with
0.1
F Capacitors
0
100
200
300
400
500
600
700
800
900
1,000
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
IN
(V)
V
IN
(
A)
-6
-5
-4
-3
-2
-1
0
0
10
20
30
40
50
I
OUT
(mA)
V
OUT
(V)
V
IN
= 2V
V
IN
= 3V
V
IN
= 5V
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
I
OUT
(mA)
P
o
wer efficienc
y (%)
V
IN
= 5V
V
IN
= 3V
V
IN
= 2V
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
I
OUT
(mA)
V
eff (%)
V
IN
= 5V
V
IN
= 3V
V
IN
= 2V
6
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Figure 11. Power Efficiency vs. Supply Voltage with
a 5mA load
Figure 12. Voltage efficiency vs. Supply Voltage without
a Load with 0.1
F Capacitors
Figure 13. Output Noise and Ripple
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= +5.0V, C1 = C2 = C3 = 0.33
F and T
AMB
= 25
o
C unless otherwise noted. The circuit found in
Figure 14 was
used to obtain the following typical performance characteristics (unless otherwise noted).
V
IN
= 3.3V
V
OUT
= -3.2V
I
LOAD
= 5mA
0
10
20
30
40
50
60
70
80
90
100
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
IN
(V)
P
eff (%)
0
20
40
60
80
100
120
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
IN
(V)
V
eff (%)
7
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Figure 15. SP6832 Connected as a Voltage Inverter with the load from V
OUT
to V
IN
Figure 14. SP6832 in its Typical Operating Circuit as a Negative Voltage Converter; this Circuit Was Used to Obtain the
Typical Performance Characteristics Found in Figures 1 Through 13 (unless otherwise noted)
C1-
V
IN
C1+
GND
SP6832
5
3
2
1
4
R
L
C3
C2
V
OUT
C1
C1-
V
IN
C1+
GND
SP6832
5
3
2
1
4
C2
V
OUT
C1
R
L
C3
+
8
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
DESCRIPTION
The SP6832 is a CMOS Charge Pump Voltage
Converter that can be used to invert a +1.15V
to +5.3V input voltage. These devices are ideal
for designs involving battery-powered and/or
board level voltage conversion applications.
The typical operating frequency of the SP6832
is 500kHz. The SP6832 has a typical operating
current of 800
A. The device can output 25mA
with a voltage drop of 500mV. The devices are
ideal for designs using +3.3V or +3.6V lithium
ion batteries such as cell phones, PDAs, medical
instruments, and other portable equipment.
The SP6832 combines a high efficiency with
a low quiescent current.
THEORY OF OPERATION
The SP6832 should theoretically produce an
inverted input voltage. In real world applications,
there are small voltage drops at the output that
reduce efficiency. The circuit of an ideal voltage
inverter can be found in Figure 16. The voltage
inverters require two external capacitors to
store the charge. A description of the two
phases follows:
Phase 1
In the first phase of the clock cycle, switches S1
and S3 are opened and S2 and S4 are closed.
This connects the flying capacitor, C1, from V
IN
to ground. C1 charges up to the input voltage
applied at V
IN
.
Phase 2
In the second phase of the clock cycle, switches
S1 and S3 are opened and S2 and S4 are closed.
This connects the flying capacitor, C1, in parallel
with the output capacitor, C2. The charge stored
in C1 is now transferred to C2. Simultaneously,
the negative side of C2 is connected to V
OUT
and
the positive side is connected to ground. With
the voltage across C2 smaller than the voltage
across C1, the charge flows from C1 to C2 until
the voltage at the V
OUT
equals -V
IN
.
Charge-Pump Output
The output of the SP6832 is not regulated and
therefore is dependent on the output resistance
and the amount of load current. As the load
current increases, losses may slightly increase
at the output and the voltage may become
slightly more positive. The loss at the negative
output, V
LOSS
, equals the current draw, I
OUT
, from
V
OUT
times the negative converter's source
resistance, R
S
:
V
LOSS
= I
OUT
x R
S
.
The actual inverted output voltage at V
OUT
will
equal the inverted voltage difference of V
IN
and
V
LOSS
:
V
OUT
= -(V
IN
- V
LOSS
).
Efficiency
Theoretically, the total power loss of a switched
capacitor voltage converter can be summed up as
follows:
P
LOSS
= P
INT
+ P
CAP
+ P
CONV
,
where P
LOSS
is the total power loss, P
INT
is the total
internal loss in the IC including any losses in the
MOSFET switches, P
CAP
is the resistive loss of
Figure 16. Circuit for an Ideal Voltage Inverter
C1
C2
S1
S3
S4
S2
V
OUT
V
IN
V
OUT
= -V
IN
9
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
the charge pump capacitors, and P
CONV
is the total
conversion loss during charge transfer between
the flying and output capacitors. These are the
three theoretical factors that may effect the power
efficiency of the SP6832 in designs.
Internal losses come from the power dissipated
in the IC's internal circuitry.
Losses in the charge pump capacitors will be
induced by the capacitors' ESR. The effects of
the ESR losses and the output resistance can be
found in the following equation:
I
OUT
2
x R
OUT
= P
CAP
+ P
CONV
and
R
OUT
4 x (2 x R
SWITCHES
+ ESR
C1
) +
ESR
C2
+
1
f
OSC
x C1
,
where I
OUT
is the output current, R
OUT
is the
circuit's output resistance, R
SWITCHES
is the internal
resistance of the MOSFET switches, ESR
C1
and
ESR
C2
are the ESR of their respective capacitors,
and f
OSC
is the oscillator frequency. This term
with f
OSC
is derived from an ideal switched-
capacitor circuit as seen in Figure 17.
Conversion losses will happen during the charge
transfer between the flying capacitor, C1, and
the output capacitor, C2, when there is a voltage
difference between them. P
CONV
can be determined
by the following equation:
P
CONV
= f
OSC
x [
1
/
2
x C1 x (V
IN
2
- V
OUT
2
) +
1
/
2
x C2 x (V
RIPPLE
2
- 2 x V
OUT
x V
RIPPLE
) ].
Actual Efficiency
To determine the actual efficiency of the
SP6832 device operation, a designer can use the
following equation:
Efficiency (ACTUAL) = x 100%
P
OUT
P
IN
,
where
P
OUT
= V
OUT
x I
OUT
and
P
IN
= V
IN
x I
IN
where P
OUT
is the power output, V
OUT
is the
output voltage, I
OUT
is the output current, P
IN
is
the power from the supply driving the SP6832,
V
IN
is the supply input voltage, and I
IN
is the
supply input current.
Ideal Efficiency
The ideal efficiency is not the true power
efficiency because it is not calculated relative to
the input power which includes the input current
losses in the charge pump. The ideal efficiency
can be determined with the following equation:
Efficiency (IDEAL) = x 100%
P
OUT
P
OUT (IDEAL)
,
where
P
OUT (IDEAL)
= -V
IN
x
-V
IN
R
L
,
and P
OUT
is the measured power output. Both
efficiencies are provided to designers for
comparison.
Figure 17. Equivalent Circuit for an Ideal Switched
Capacitor
V+
C2
R
L
V
OUT
C1
f
V+
C2
R
L
V
OUT
R
equivalent
=
1
f x C1
R
equivalent
10
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Negative Voltage Converter
The typical operating circuit for the SP6832
devices is a negative voltage converter. Refer to
Figure 14. This circuit is used to obtain the
Typical Performance Characteristics found in
Figures 1 to 13 (unless otherwise noted).
Voltage Inverter with the Load from
V
OUT
to V
IN
A designer can find the most common application
for the SP6832 devices in Figure 15 as a voltage
inverter. The only external components needed
are 3 capacitors: the flying capacitor, C1, the
output capacitor, C2, and the bypass capacitor,
C3 (if necessary).
Driving Excessive Loads
The output should never be pulled above ground.
A designer should implement a Schottky diode
(1N5817) from OUT to GND when driving
heavy loads where a higher supply is sourcing
current into OUT. Refer to Figure 18 for this
circuit connection.
APPLICATION INFORMATION
For the following applications, C1 = C2 = 0.1
F
Capacitor Selection
Low ESR capacitors are needed to obtain low
output resistance. Refer to Table 1 for some
suggested low ESR capacitors. The output
resistance of the SP6832 is a function of the
ESR of C1 and C2. This output resistance can
be determined by the equation previously
provided in the Efficiency
section:
R
OUT
4 x (2 x R
SWITCHES
+ ESR
C1
) +
ESR
C2
+
1
f
OSC
x C1
,
where R
OUT
is the circuit output resistance,
R
SWITCHES
is the internal resistance of the MOSFET
switches, ESR
C1
and ESR
C2
are the ESR of their
respective capacitors, and f
OSC
is the oscillator
frequency. This term with f
OSC
is derived from an
ideal switched-capacitor circuit as seen in
Figure 21.
Minimizing the ESR of C1 and C2 will minimize
the total output resistance and will improve the
efficiency.
Flying Capacitor
Decreasing flying capacitor, C1, values will
increase the output resistance of the SP6832
while increasing C1 will reduce the output
resistance. There is a point where increasing
C1 will have a negligible effect on the
output resistance due to the domination of
the output resistance by the internal MOSFET
switch resistance and the total capacitor ESR.
Output Capacitor
Increasing output capacitor, C2, values will
decrease the output ripple voltage. Reducing the
ESR of C2 will reduce both output ripple voltage
and output resistance. If higher output ripple can
be tolerated in designs, smaller capacitance values
for C2 should be used with light loads. The
following equation can be used to calculate the
peak-to-peak ripple voltage:
V
RIPPLE
= 2 x I
OUT
x ESR
C2
+
I
OUT
f
OSC
x C2
.
Input Bypass Capacitor
The bypass capacitor at the input pin will reduce
AC impedance and the impact of any of
the SP6832 devices' switching noise. It is
recommended that for heavy loads a bypass
capacitor approximately equal to the flying
capacitor, C1, be used. For light loads, the value
of the bypass capacitor can be reduced.
When loading the SP6832 devices from IN to
OUT, the input current remains constant
(disregarding any spikes due to internal
switching). Implementing a 0.1
F bypass
capacitor should be sufficient.
When loading the SP6832 devices from OUT to
GND, the current from the supply will flow
into the input for half of the cycle and will be
zero for the other half of the cycle. Designers
should implement a large bypass capacitor
if the supply has a high AC impedance.
11
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
OUT
SP6832
C1
1
5
3
C2
C1+
C1-
GND
2
4
C4
C3
IN
D1
D2
+V
IN
V
OUT1
= (2 x V
IN
) - V
FD1
- V
FD2
V
OUT2
= -V
IN
V
OUT1
V
OUT2
where
V
OUT1
= positive doubled output voltage,
V
IN
= input voltage,
V
FD1
= forward bias voltage across D1,
V
FD2
= forward bias voltage across D2, and
V
OUT2
= inverted output voltage.
D1 = D2 = 1N4148
Figure 19. SP6832 Device Connected in a Doubler/Inverter Combination Circuit
Figure 18. Protection for Heavy Loads
SP6832
1
4
OUT
GND
1N5817
12
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
Combining a Doubler and Inverter Circuit
A designer can connect a SP6832 device in a
combination doubler/inverter circuit as seen in
Figure 19. The doubler uses capacitors C3 and
C4 while the inverter uses C1 and C2. Loading
either output decreases both output voltages to
GND because both the doubler and the inverter
circuits use the charge pump. Designers should
not allow the total current output from the
doubler and the inverter to exceed 40mA.
Implementing Shutdown
If shutdown control of the SP6832 devices is
necessary, the circuit found in Figure 20 can be
implemented. The 0.1
F capacitor at IN absorbs
transient input currents. The output resistance of
the devices can be determined by the following
equation:
R
OUT
= 20 + 2 x R
BUFFER
,
where R
OUT
is the output resistance and R
BUFFER
is the output resistance of the buffer driving IN.
R
BUFFER
can be reduced by connecting multiple
buffers in parallel at IN. The polarity of the
SHUTDOWN signal can be changed by using a
noninverting buffer to drive IN.
Connecting in Parallel
A designer can parallel a number of SP6832
devices to reduce the output resistance for
specific designs. All devices will need their own
flying capacitor, C1, but a single output capacitor
will serve all of the devices connected in
parallel by increasing the capacitance of C2 by
a factor of n where n equals the total number
of devices connected. This connection can be
found in Figure 21.
Cascading Devices
A designer can cascade SP6832 devices to
produce a larger inverted voltage output. Refer
to Figure 22 for this circuit connection. With
two cascaded devices, the unloaded output
voltage is decreased by the output resistance of
the first device multiplied by the quiescent
current of the second device connected. The total
output resistance is greatly increased when
more than two devices are cascaded.
Layout and Grounding
Designers should make an effort to minimize
noise by paying special attention to the
circuit layout with the SP6832 devices.
External components should be connected in
close proximity to the device and a ground
plane should be implemented. This will keep
electrical traces short minimizing parasitic
inductance and capacitance.
Figure 20. SP6832 Device with Shutdown Control
OUT
SP6832
C1
1
5
3
C2
C1+
C1-
GND
2
4
IN
+V
IN
V
OUT
C
IN
0.1
F
Shutdown
Logic
OFF
ON
13
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
OUT
SP6832
+V
IN
C1
5
5
3
C2
C1+
C1-
GND
2
4
OUT
SP6832
IN
C1
1
5
3
C2
C1+
C1-
GND
2
4
OUT
SP6832
IN
C1
1
3
5
C2
C1+
C1-
GND
2
4
V
OUT
"n"
"1"
"2"
V
OUT
= -n x V
IN
where V
OUT
= output voltage,
V
IN
= input voltage, and
n = the total number of devices connected.
IN
Figure 22. SP6832 Devices Cascaded to Increase Output Voltage
OUT
SP6832
+V
IN
C1
1
5
3
C1+
C1-
GND
2
4
OUT
SP6832
IN
C1
1
5
3
C1+
C1-
GND
2
4
OUT
SP6832
IN
C1
1
5
3
C2 x n
C1+
C1-
GND
2
4
R
L
"n"
"1"
"2"
where V
OUT
= output voltage
,
V
IN
= input voltage,
R
TOT
= total resistance of the devices connected in parallel,
R
OUT
= the output resistance of a single device, and
n = the total number of devices connected in parallel.
IN
R
TOT
=
R
OUT
n
V
OUT
= -V
IN
V
OUT
Figure 21. SP6832 Devices Connected in Parallel to Reduce Total Output Resistance
Table 1. Suggested Low ESR SM Ceramic Capacitors
/
R
E
R
U
T
C
A
F
U
N
A
M
#
E
N
O
H
P
E
L
E
T
R
E
B
M
U
N
T
R
A
P
/
E
C
N
A
T
I
C
A
P
A
C
E
G
A
T
L
O
V
@
R
S
E
z
H
k
0
0
5
E
P
Y
T
/
E
Z
I
S
0
0
1
6
-
3
0
8
-
7
4
8
K
4
0
1
J
0
R
5
X
5
0
0
1
C
1
.
0
V
3
.
6
/
F
8
0
.
0
R
5
X
/
2
0
4
0
/
K
D
T
0
0
1
6
-
3
0
8
-
7
4
8
K
4
3
3
J
0
R
5
X
8
0
6
1
C
3
3
.
0
V
3
.
6
/
F
4
0
.
0
R
5
X
/
3
0
6
0
N
E
D
U
Y
/
O
Y
I
A
T
8
8
8
0
-
5
2
9
-
7
4
8
V
K
4
0
1
J
B
5
0
1
K
M
L
1
.
0
V
0
1
/
F
1
.
0
R
5
X
/
2
0
4
0
8
8
8
0
-
5
2
9
-
7
4
8
A
K
4
3
3
J
B
7
0
1
K
M
L
3
3
.
0
V
0
1
/
F
5
0
.
0
R
7
X
/
3
0
6
0
TDK/
TAIYO/YUDEN
CAPACITOR
14
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
PACKAGE: SOT23-5
SYMBOL
A
A1
A2
b
C
D
E
E1
L
e
e1
a
1.45
0.15
1.30
0.50
0.20
3.10
3.00
1.75
0.55
10
O
0.90
0.00
0.90
0.25
0.09
2.80
2.60
1.50
0.35
0
O
MIN
MAX
0.95ref
1.90ref
E
A
e
C
L
b
e1
D
C
L
A2
A1
A
A
.10
C
L
E1
L
2
0.20
DATUM 'A
'
C
a
15
SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter Copyright 2000 Sipex Corporation
ORDERING INFORMATION
Model
Temperature Range
Package Type
SP6832EK . ............................................ -40C to +85C ............................................... SOT23-5
SP6832EK/TR ......................................... -40C to +85C ............................................... SOT23-5
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Corporation
SIGNAL PROCESSING EXCELLENCE
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