SP7651 Powerblox Wide Input Voltage Range, 3A 900kHz buck Regulator
1
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
FEATURES
2.5V to 20V Step Down Achieved Using Dual Input
Output Voltage down to 0.8V
3A Output Capability (Up to 5A with Air Flow)
Built in Low R
DSON
Power FETs (40 m typ)
Highly Integrated Design, Minimal Components
900 kHz Fixed Frequency Operation
UVLO Detects Both V
CC
and V
IN
Over Temperature Protection
Short Circuit Protection with Auto-Restart
Wide BW Amp Allows Type II or III Compensation
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than 92% Possible
Asynchronous Start-Up into a Pre-Charged Output
Small 7mm x 4mm DFN Package
U.S. Patent #6,922,041
The SP7651 is a high voltage synchronous step-down switching regulator optimized for high efficiency. The part is
designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower V
CC
voltage minimizes power dissipation in the part. The SP7651 is designed to provide a fully integrated buck regulator
solution using a fixed 900kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal
shutdown and output short circuit protection. The SP7651 is available in the space saving 7mm X 4mm DFN package
.
TYPICAL APPLICATION CIRCUIT
Now Available in Lead Free Packaging
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
2 2
23
24
25
26
BOTTOM VIEW
Heatsink Pad 1
Connect to Lx
Heatsink pad 2
Connect to GND
Heatsink pad 3
Connect to V
IN
P
GND
P
GND
GND
V
FB
COMP
UVIN
GND
SS
V
IN
LX
LX
LX
LX
V
CC
GND
GND
GND
BST
NC
LX
LX
LX
DFN PACKAGE
7mm x 4mm
SP7651
P
GND
V
IN
V
IN
V
IN
CBST
6800pF
L1
4.7uH, Irate=3.87A
C1
22uF
CVCC
2.2uF
U1
SP7651
PGND
1
PGND
2
PGND
3
GND
4
VFB
5
COMP
6
UVIN
7
GND
8
SS
9
VIN
10
VIN
11
VIN
12
VIN
13
LX
14
LX
15
LX
16
NC
17
BST
18
GND
19
GND
20
GND
21
VCC
22
LX
23
LX
24
LX
25
LX
26
DBST
CSS
15nF
CP1
22pF
3.3V
0-3A
RSET
21.5k,1%
GND
C3
22uF
Notes:
12V
VIN
1. U1 Bottom-Side Layout should
have three contacts isolated from
one another: Vin, SWNODE, and GND.
SD101AWS
VOUT
RZ3
7.15k,
1%
CZ3
150pF
CZ2
1,000pF
R1
68.1k,1%
RZ2
15k,1%
CF1
100pF
fs=900Khz
+5V
VCC
ENABLE
2. RSET=54.48/(Vout-0.8V) (KOhm)
6.3V
(note 2)
16V
SP7651
Wide Input Voltage Range 3Amp
900kHz Buck Regulator
Power
Blox
Blox
TM
2
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
Unless otherwise specified: -40C < T
AMB
< 85C, -40C< Tj <125C, 4.5V < V
CC
< 5.5V, 3V< Vin < 20V, BST=LX
+ 5V,
LX = GND = 0.0V, UVIN = 3.0V, CV
CC
= 1F, C
COMP
= 0.1F, C
SS
= 50nF, Typical measured at V
CC
= 5V.
The denotes the specifications which apply over the full temperature range, unless otherwise specified.
V
CC
.................................................................................................. 7V
V
IN ...........................................................................................................................................
22V
I
LX ...............................................................................................................................................
5A
BST ............................................................................................... 35V
LX-BST ............................................................................. -0.3V to 7V
LX ....................................................................................... -1V to 20V
All other pins .......................................................... -0.3V to V
CC
+0.3V
Storage Temperature .................................................. -65C to 150C
Power Dissipation .................................................... Internally Limited
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance
JC ....................................................................................
5C/W
ABSOLUTE MAXIMUM RATINGS
R
E
T
E
M
A
R
A
P
.
N
I
M
.
P
Y
T
.
X
A
M
S
T
I
N
U
S
N
O
I
T
I
D
N
O
C
T
N
E
R
R
U
C
T
N
E
C
S
E
I
U
Q
V
C
C
)
g
n
i
h
c
t
i
w
s
o
N
(
t
n
e
r
r
u
C
y
l
p
p
u
S
5
.
1
3
A
m
V
B
F
V
9
.
0
=
V
C
C
)
g
n
i
h
c
t
i
w
s
(
t
n
e
r
r
u
C
y
l
p
p
u
S
8
2
1
A
m
)
g
n
i
h
c
t
i
w
s
o
N
(
t
n
e
r
r
u
C
y
l
p
p
u
S
T
S
B
2
.
0
4
.
0
A
m
V
B
F
V
9
.
0
=
)
g
n
i
h
c
t
i
w
s
(
t
n
e
r
r
u
C
y
l
p
p
u
S
T
S
B
4
6
A
m
O
L
V
U
:
N
O
I
T
C
E
T
O
R
P
V
C
C
d
l
o
h
s
e
r
h
T
t
r
a
t
S
O
L
V
U
0
0
.
4
5
2
.
4
5
.
4
V
V
C
C
s
i
s
e
r
e
t
s
y
H
O
L
V
U
0
0
1
0
0
2
0
0
3
V
m
d
l
o
h
s
e
r
h
T
t
r
a
t
S
N
I
V
U
3
.
2
5
.
2
5
6
.
2
V
s
i
s
e
r
e
t
s
y
H
N
I
V
U
0
0
2
0
0
3
0
0
4
V
m
t
n
e
r
r
u
C
t
u
p
n
I
N
I
V
U
1
A
V
0
.
3
=
N
I
V
U
E
C
N
E
R
E
F
E
R
R
E
I
F
I
L
P
M
A
R
O
R
R
E
e
c
n
e
r
e
f
e
R
r
e
i
f
il
p
m
A
r
o
r
r
E
2
9
7
.
0
0
0
8
.
0
8
0
8
.
0
V
e
r
u
s
a
e
M
,
.
g
i
f
n
o
C
n
i
a
G
X
2
V
B
F
V
;
C
C
C
5
2
=
T
,
V
5
=
e
c
n
e
r
e
f
e
R
r
e
i
f
il
p
m
A
r
o
r
r
E
e
r
u
t
a
r
e
p
m
e
T
d
n
a
e
n
i
L
r
e
v
O
8
8
7
.
0
0
0
8
.
0
2
1
8
.
0
V
e
c
n
a
t
c
u
d
n
o
c
s
n
a
r
T
r
e
i
f
il
p
m
A
r
o
r
r
E
6
V
/
A
m
n
i
a
G
r
e
i
f
il
p
m
A
r
o
r
r
E
0
6
B
d
d
a
o
L
o
N
t
n
e
r
r
u
C
k
n
i
S
P
M
O
C
0
5
1
A
V
B
F
V
9
.
0
=
P
M
O
C
,
V
9
.
0
=
t
n
e
r
r
u
C
e
c
r
u
o
S
P
M
O
C
0
5
1
A
V
B
F
V
2
.
2
=
P
M
O
C
,
V
7
.
0
=
V
B
F
t
n
e
r
r
u
C
s
a
i
B
t
u
p
n
I
0
5
0
0
2
A
n
V
B
F
V
8
.
0
=
e
l
o
P
l
a
n
r
e
t
n
I
4
z
H
M
p
m
a
l
C
P
M
O
C
5
.
2
V
V
B
F
C
5
2
=
A
T
,
V
7
.
0
=
t
n
e
i
c
i
f
f
e
o
C
.
p
m
e
T
p
m
a
l
C
P
M
O
C
2
-
C
/
V
m
ELECTRICAL SPECIFICATIONS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
3
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40C < T
AMB
< 85C, -40C<Tj<125C, 4.5V < V
CC
< 5.5V, 3V<Vin<20V, BST=LX
+ 5V, LX =
GND = 0.0V, UVIN = 3.0V, CV
CC
= 1F, C
COMP
= 0.1F, C
SS
= 50nF, Typical measured at V
CC
= 5V.
The denotes the specifications which apply over the full temperature range, unless otherwise specified.
R
E
T
E
M
A
R
A
P
.
N
I
M
.
P
Y
T
.
X
A
M
S
T
I
N
U
S
N
O
I
T
I
D
N
O
C
H
T
A
P
Y
A
L
E
D
P
O
O
L
&
P
M
A
R
,
R
O
T
A
R
A
P
M
O
C
M
W
P
:
P
O
O
L
L
O
R
T
N
O
C
e
d
u
t
il
p
m
A
p
m
a
R
2
9
.
0
1
.
1
8
2
.
1
V
t
e
s
f
f
O
P
M
A
R
1
.
1
V
T
A
P
M
O
C
P
M
A
R
,
C
5
2
=
g
n
i
h
c
t
i
w
S
s
t
r
a
t
s
H
G
li
t
n
u
t
n
e
i
c
i
f
f
e
o
C
.
p
m
e
T
t
e
s
f
f
O
P
M
A
R
2
-
C
/
V
m
h
t
d
i
W
e
s
l
u
P
m
u
m
i
n
i
M
H
G
0
9
0
8
1
s
n
o
i
t
a
R
y
t
u
D
e
l
b
a
ll
o
r
t
n
o
C
m
u
m
i
x
a
M
2
9
7
9
%
o
i
t
a
R
y
t
u
D
m
u
m
i
x
a
M
e
r
o
f
e
b
t
s
u
j
d
e
r
u
s
a
e
M
s
n
i
g
e
b
g
n
i
s
l
u
p
o
i
t
a
R
y
t
u
D
m
u
m
i
x
a
M
0
0
1
%
s
e
l
c
y
c
0
2
r
o
f
d
il
a
V
o
i
t
a
R
r
o
t
a
ll
i
c
s
O
l
a
n
r
e
t
n
I
0
1
8
0
0
9
0
9
9
z
H
k
T
R
A
T
S
T
F
O
S
:
S
R
E
M
I
T
:
t
n
e
r
r
u
C
e
g
r
a
h
C
S
S
0
1
A
:
t
n
e
r
r
u
C
e
g
r
a
h
c
s
i
D
S
S
1
A
m
V
2
.
0
=
S
S
,
t
n
e
s
e
r
P
t
l
u
a
F
l
a
m
r
e
h
T
&
t
i
u
c
r
i
C
t
r
o
h
S
:
N
O
I
T
C
E
T
O
R
P
e
g
a
t
l
o
V
d
l
o
h
s
e
r
h
T
t
i
u
c
r
i
C
t
r
o
h
S
2
.
0
5
2
.
0
3
.
0
V
V
d
e
r
u
s
a
e
M
F
E
R
-
)
V
8
.
0
(
V
B
F
t
u
o
e
m
i
T
p
u
c
c
i
H
0
0
2
s
m
V
B
F
V
5
.
0
=
s
e
l
c
y
C
k
c
o
l
C
e
l
b
a
w
o
ll
A
f
o
r
e
b
m
u
N
e
l
c
y
C
y
t
u
D
%
0
0
1
t
a
0
2
s
e
l
c
y
C
s
e
l
c
y
C
0
2
r
e
t
f
A
e
s
l
u
P
L
G
m
u
m
i
n
i
M
5
.
0
s
e
l
c
y
C
V
B
F
V
7
.
0
=
e
r
u
t
a
r
e
p
m
e
T
n
w
o
d
t
u
h
S
l
a
m
r
e
h
T
5
4
1
C
V
B
F
V
7
.
0
=
e
r
u
t
a
r
e
p
m
e
T
y
r
e
v
o
c
e
R
l
a
m
r
e
h
T
5
3
1
C
s
i
s
e
r
e
t
s
y
H
l
a
m
r
e
h
T
0
1
C
E
G
A
T
S
R
E
W
O
P
:
T
U
P
T
U
O
R
e
d
i
S
h
g
i
H
N
O
S
D
0
4
m
V
C
C
I
;
V
5
=
T
U
O
A
3
=
T
B
M
A
C
5
2
=
R
T
E
F
s
u
o
n
o
r
h
c
n
y
S
N
O
S
D
0
4
m
V
C
C
I
;
V
5
=
T
U
O
A
3
=
T
B
M
A
C
5
2
=
t
n
e
r
r
u
C
t
u
p
t
u
O
m
u
m
i
x
a
M
3
A
4
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
General Overview
The SP7651 is a fixed frequency, voltage mode,
synchronous PWM regulator optimized for high
efficiency. The part has been designed to be
especially attractive for split plane applications
utilizing 5V to power the controller and 2.5V to
28V for step down conversion.
The heart of the SP7651 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. A precision 0.8V reference, present on
the positive terminal of the error amplifier,
permits the programming of the output voltage
down to 0.8V via the V
FB
pin. The output of the
error amplifier, COMP, which is compared to a
1.1V peak-to-peak ramp, is responsible for trail-
ing edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM fre-
quency to 900kHz.
THEORY OF OPERATION
The SP7651 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during startup, to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The SP7651 also contains a number of valuable
protection features. Programmable UVLO al-
lows the user to set the exact V
IN
value at which
the conversion voltage can safely begin down
conversion, and an internal V
CC
UVLO ensures
that the controller itself has enough voltage to
properly operate. Other protection features in-
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
P
GND
Ground connection for the synchronous rectifier
4,8,19-21
GND
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of Cout.
5
V
FB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of
the Error Amplifier and serves as the output voltage feedback point for the
Buck Converter. The output voltage is sensed and can be adjusted through
an external resistor divider. Whenever V
FB
drops 0.25V below the positive
reference, a short circuit fault is detected and the IC enters hiccup mode.
6
COMP
Output of the Error Amplifier. It is internally connected to the inverting input of
the PWM comparator. An optimal filter combination is chosen and connected
to this pin and either ground or V
FB
to stabilize the voltage mode loop.
7
UVIN
UVLO input for Vin voltage. Connect a resistor divider between V
IN
and UV
IN
to set minimum operating voltage.
9
SS
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10A source current. The SS pin is held low via a
1mA (min) current during all fault conditions.
10-13
V
IN
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and PGND.
14-16,23-26
LX
Connect an inductor between this pinand V
OUT
17
NC
No Connect
18
BST
High side driver supply pin. Connect BST to the external boost diode and
capacitor as shown in the Typical Application Circuit on page 1. High side
driver is connected between BST pin and SWN pin.
22
Vcc
Input for external 5V bias supply
5
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
clude thermal shutdown and short-circuit detec-
tion. In the event that either a thermal, short-
circuit, or UVLO fault is detected, the SP7651 is
forced into an idle state where the output drivers
are held off for a finite period before a re-start is
attempted.
Soft Start
"Soft Start" is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source cur-
rent. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor.
I
VIN
= C
OUT
* (
V
OUT
/
T
SOFT-START
)
The SP7651 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10
A pullup current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
I
VIN
= C
OUT
* (
V
OUT
*10
A / (C
SS
* 0.8V)
Under Voltage Lock Out (UVLO)
The SP7651 contains two separate UVLO com-
parators to monitor the internal bias (V
CC
) and
conversion (V
IN
) voltages independently. The
V
CC
UVLO threshold is internally set to 4.25V,
whereas the V
IN
UVLO threshold is program-
mable through the UVIN pin. When the UVIN
pin is greater than 2.5V, the SP7651 is permitted
to start up pending the removal of all other
faults. Both the V
CC
and V
IN
UVLO compara-
tors have been designed with hysteresis to pre-
vent noise from resetting a fault.
Thermal and Short-Circuit
Protection
Because the SP7651 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145
C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
A short-circuit detection comparator has also
been included in the SP7651 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the V
FB
pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overrides the internal 0.8V reference during soft
start, the SP7651 is capable of detecting short-
circuit faults throughout the duration of soft
start as well as in regular operation.
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7651 is forced into
an idle state where the SS and COMP pins are
pulled low and the NFETS are held off. In the
event of UVLO fault, the SP7651 remains in this
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a re-start is at-
tempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is de-
tected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
Error Amplifier and Voltage Loop
Since the heart of the SP7651 voltage error loop
is a high performance, wide bandwidth
transconductance amplifier, great care should
be taken to select the optimal compensation
network. Because of the amplifier's current-
limited (+/-150
A) transconductance, there are
many ways to compensate the voltage loop or to
THEORY OF OPERATION
6
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
THEORY OF OPERATION
control the COMP pin externally. If a simple,
single pole, single zero response is desired, then
compensation can be as simple as an RC circuit
to Ground. If a more complex compensation is
required, then the amplifier has enough band-
width (45
at 4 MHz) and enough gain (60dB) to
run Type III compensation schemes with ad-
equate gain and phase margins at crossover
frequencies greater than 50kHz.
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is asynchronous startup
mode. Basically, the synchronous rectifier can-
not turn on unless the high side NFET has
attempted to turn on or the SS pin has exceeded
1.7V. This feature prevents the controller from
"dragging down" the output voltage during
startup or in fault modes. The second feature is
a 100% duty cycle timeout that ensures synchro-
nized refreshing of the BST capacitor at very
high duty ratios. In the event that the high side
NFET is on for 20 continuous clock cycles, a
reset is given to the PWM flip-flop half way
through the 21st cycle. This forces GL to rise for
the cycle, in turn refreshing the BST capacitor.
Power MOSFETs
The SP7651 contains a pair of integrated low
resistance N MOSFETs designed to drive up to
3A of output current. Maximum output current
could be limited by thermal limitations of a
particular application. The SP7651 incorpo-
rates a built-in over-temperature protection to
prevent internal overheating.
GH
Voltage
GL
Voltage
V(VIN)
0V
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
TIME
SWN
Voltage
VBST
VSWN
V(VCC)
The SP7651 can be set to different output volt-
ages. The relationship in the following formula
is based on a voltage divider from the output to
the feedback pin V
FB
, which is set to an internal
reference voltage of 0.80V. Standard 1% metal
film resistors of surface mount size 0603 are
recommended.
Vout = 0.80V ( R1 / R2 + 1 ) =>
R2 = R1
.
[
( Vout / 0.80V ) 1
]
Where R1 = 68.1K
and for Vout = 0.80V
setting, simply remove R2 from the board. Fur-
thermore, one could select the value of the R1
and R2 combination to meet the exact output
voltage setting by restricting R1 resistance range
such that 50K
< R1 < 100K for overall
system loop stability.
Setting Output Voltages
7
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Inductor Selection
There are many factors to consider in selecting
the inductor, including: core material, induc-
tance vs. frequency, current handling capabil-
ity, efficiency, size and EMI. In a typical
SP7651 circuit, the inductor is chosen primarily
by operating frequency, saturation current and
DC resistance. Increasing the inductor value
will decrease output voltage ripple, but degrade
transient response. Low inductor values provide
the smallest size, but cause large ripple currents,
poor efficiency and require more output capaci-
tance to smooth out the larger ripple current.
The inductor must be able to handle the peak
current at the switching frequency without satu-
rating, and the copper resistance in the winding
should be kept as low as possible to minimize
resistive power loss. A good compromise be-
tween size, loss and cost is to set the inductor
ripple current to be within 20% to 40% of the
maximum output current.
The switching frequency and the inductor oper-
ating point determine the inductor value as fol-
lows:
( max)
(max )
(max)
)
(
OUT
r
S
IN
OUT
IN
OUT
I
K
F
V
V
V
V
L
-
=
where:
Fs = switching frequency
Kr = ratio of the AC inductor ripple current to
the maximum output current
The peak-to-peak inductor ripple current is:
L
F
V
V
V
V
I
S
I N
OUT
IN
OUT
PP
(max)
(max)
)
(
-
=
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency require-
ments. The core must be large enough not to
saturate at the peak inductor current...
2
(max)
P P
OUT
PEAK
I
I
I
+
=
...and provide low core loss at the high switch-
ing frequency. Low cost powdered-iron cores
are inappropriate for 900kHz operation.
Gapped ferrite inductors are widely available
for consideration. Select devices that have oper-
ating data shown up to 1MHz. Ferrite materials,
on the other hand, are more expensive and have
an abrupt saturation characteristic with the in-
ductance dropping sharply when the peak de-
sign current is exceeded. Nevertheless, they are
preferred at high switching frequencies because
they present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials will be used
with the SP7651.
Optimizing Efficiency
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To mini-
mize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of using a larger inductor. Core losses
have a more significant contribution at low
output current where the copper losses are at a
minimum, and can typically be neglected at
higher output currents where the copper losses
dominate. Core loss information is usually
available from the magnetics vendor. Proper
inductor selection can affect the resulting power
supply efficiency by more than 15-20%!
The copper loss in the inductor can be calculated
using the following equation:
WINDING
RMS
L
Cu
L
R
I
P
2
)
(
)
(
=
where I
L(RMS)
is the RMS inductor current that
can be calculated as follows:
I
L(RMS)
= I
OUT(max)
1 + 1
(
I
PP
)
2
3 I
OUT(max)
8
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
Output Capacitor Selection
The required ESR (Equivalent Series Resis-
tance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resis-
tive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the addi-
tional current demanded by the load until the
SP7651 adjusts the inductor current to the new
value.
In order to maintain V
OUT,
the capacitance must
be large enough so that the output voltage is held
up while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitor causes a step in the output voltage
equal to the current. Because of the fast tran-
sient response and inherent 100% to 0% duty
cycle capability provided by the SP7651 when
exposed to an output load transient, the output
capacitor is typically chosen for ESR, not for
capacitance value.
The ESR of the output capacitor, combined with
the inductor ripple current, is typically the main
contributor to output voltage ripple. The maxi-
mum allowable ESR required to maintain a speci-
fied output voltage ripple can be calculated by:
R
ESR
V
OUT
I
PK-PK
where:
V
OUT
= Peak-to-Peak Output Voltage Ripple
I
PK-PK
= Peak-to-Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
V
OUT
=
(
I
PP
(1 D)
)
2
+ (I
PP
R
ESR
)
2
C
OUT
F
S
F
S
= Switching Frequency
D = Duty Cycle
C
OUT
= Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source cur-
rent of the high-side MOSFET is approximately
a square wave of duty cycle V
OUT
/V
IN
. Most of
this current is supplied by the input bypass
capacitors. The RMS value of input capacitor
current is determined at the maximum output
current and under the assumption that the peak-
to-peak inductor ripple current is low; it is given by:
I
CIN(rms)
= I
OUT(max)
D(1 - D)
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
I
OUT
/2. Select input capacitors with adequate
ripple current rating to ensure reliable opera-
tion.
The power dissipated in the input capacitor is:
)
(
2
)
(
CIN
ESR
rms
CIN
CIN
R
I
P
=
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be deter-
mined by:
2
)
(
)
(
(max)
)
(
IN
IN
S
OUT
I N
OUT
MAX
OUT
CIN
E SR
out
IN
V
C
F
V
V
V
I
R
I
V
-
+
=
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
APPLICATIONS INFORMATION
9
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
capacitors are used. Tantalum capacitors are known
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
"live" to low impedance power sources.
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the selected frequency FCO, the gain of
the error amplifier compensates for the attenua-
tion caused by the rest of the loop at this fre-
quency. The goal of loop compensation is to
manipulate loop frequency response such that
its gain crosses over 0db at a slope of -20db/dec.
The first step of compensation design is to pick
the loop crossover frequency.
High crossover frequency is desirable for fast
transient response, but often jeopardizes the
SP7651 Voltage Mode Control Loop with Loop Dynamic
(SRz2Cz2+1)(SR1Cz3+1)
(SR
ESR
C
OUT
+ 1)
[S^2LC
OUT
+S(R
ESR
+R
DC
) C
OUT
+1]
V
IN
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
V
RAMP_PP
V
OUT
(Volts)
+
_
V
REF
(Volts)
Notes: R
ESR
= Output Capacitor Equivalent Series Resistance.
R
DC
= Output Inductor DC Resistance.
V
RAMP_PP
= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R
ESR
& R
DC
R
2
V
REF
(R
1
+ R
2
)
or
V
OUT
V
FBK
(Volts)
Type III Voltage Loop
Compensation
G
AMP
(s) Gain Block
PWM Stage
G
PWM
Gain
Block
Output Stage
G
OUT
(s) Gain
Block
Voltage Feedback
G
FBK
Gain Block
Definitions:
R
ESR
= Output Capacitor Equivalent Series Resistance
R
DC
= Output Inductor DC Resistance
R
RAMP_PP
= SP7651 internal RAMP Amplitude Peak-to-Peak Voltage
system stability. Crossover frequency should be
higher than the ESR zero but less than 1/5 of the
switching frequency. The ESR zero is contrib-
uted by the ESR associated with the output
capacitors and can be determined by:
Z(ESR)
=
1
.
2
C
OUT
R
ESR
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
P(LC)
=
1
.
2
L C
OUT
When the output capacitors are Ceramic type,
the SP7651 Evaluation Board requires a Type
III compensation circuit to give a phase boost of
180
in order to counteract the effects of an
underdamped resonance of the output filter at
the double pole frequency.
10
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ2
CZ2
-
+
6
5
VFB
COMP
+
- 0.8V
CF1
V
OUT
R1
68.1k, 1%
R
SET
CZ3
RZ3
R
SET
=54.48/ (VOUT -0.8) (k)
Type III Error Amplifier Compensation Circuit
APPLICATIONS INFORMATION
Frequency
(Hz)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Gain
(dB)
1/6.28(R22) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28 (R1) (CZ2)
1/6.28 (RZ2) (CP1)
1/6.28 (RZ3) (CZ3)
11
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with different
copper area and thermal resistance has been
measured. The layouts were done on 4 layer
FR4 PCB with the top and bottom layers using
3oz copper and the power and ground layers
using 1oz copper.
For the Minimum footprint, only about 0.1
square inch (of 3 ounces of) Copper was used
on the top or footprint layer, and this layer had
no vias to connect to the 3 other layers. For the
Medium footprint, about 0.7 square inches (of
3 ounces of) Copper was used on the top layer,
but vias were used to connect to the other 3
layers. For the Maximum footprint, about 1.0
square inch (of 3 ounces of) Copper was used
on the top layer and many vias were used to
connect to the 3 other layers.
The results show that only about 0.7 square
inches (of 3 ounces of) Copper on the top layer
and vias connecting to the 3 other layers are
needed to get the best thermal resistance of
36
C/W. Adding area on the top beyond the 0.7
square inches did not reduce thermal resis-
tance.
SP765X Thermal Resistance
4 Layer Board:
Top Layer 3ounces Copper
GND Layer 1ounce Copper
Power Layer 1ounce Copper
Bottom Layer 3ounces Copper
Minimum Footprint: 44C/W
Top Layer: 0.1 square inch
No Vias to other 3 Layers
Medium Footprint: 36C/W
Top Layer: 0.7 square inch
Vias to other 3 Layers
Maximum Footprint: 36C/W
Top Layer: 1.0 square inch
Vias to other 3 Layers
APPLICATIONS INFORMATION
Using a minimum of 0.1 square inches of
(3 ounces of) Copper on the top layer with
no vias connecting to the 3 other layers
produced a thermal resistance of 44
C/W.
This thermal impedance is only 22% higher
than the medium and large footprint lay-
outs, indicating that space constrained
designs can still benefit thermally from
the Powerblox family of ICs. This indi-
cates that a minimum footprint of 0.1
square inch, if used on a 4 layer board, can
produce 44
C/W thermal resistance. This
approach is still very worthwhile if used in
a space constrained design.
The following page shows the footprint
layouts from an ORCAD file. The ther-
mal data was taken for still air, not with
forced air. If forced air is used, some
improvement in thermal resistance would
be seen.
12
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
13
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISITICS
SP7651 Effi. v.s Iout Plots @
Vin=12V, and Vout=3.3V
70.0
75.0
80.0
85.0
90.0
95.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Efficiency (%)
SP7651 Vout v.s Iout Plots @
Vin=12V, and Vout=3.3V
3.295
3.3
3.305
3.31
3.315
0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Output Voltage (V)
SP7651 Effi. v.s Iout Plots @
Vin=12V, and Vout=5.0V
90.0
90.5
91.0
91.5
92.0
92.5
93.0
93.5
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Efficiency (%)
SP7651 Vout v.s Iout Plots @
Vin=12V, and Vout=5.0V
5.00
5.02
5.04
5.06
5.08
5.10
0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Output Voltage (V)
14
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
PACKAGE: 26 PIN DFN
TOP VIEW
D
E
(7 x 4 mm)
Pin #1
Identification
Note: Fused Pin Area for pins 1-3 and
pins 14-16 = (2e+b)xL - 2x(e-b) x L/2
= 0.376mm
2
or 0.0148 in
2
BOTTOM VIEW
A
SIDE VIEW
A3
A1
(K)
b
e
L
E2
D3
D2
D2
J
J1
J1
5 4 3 2 1
1 4 1 5 1 6 1 7 1 8
1 3
2 6
L/2
L
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
A
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.000
-
0.050
0.0000
-
0.0020
A3
0.178
0.203
0.228
0.0070
0.0080
0.0090
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D2
2.000
2.050
2.100
0.0787
0.0807
0.0827
D3
1.780
1.830
1.880
0.0701
0.0720
0.0740
e
E
3.950
4.000
4.050
0.1555
0.1575
0.1594
E2
2.730
2.780
2.830
0.1075
0.1094
0.1114
J
0.200
0.250
0.300
0.0079
0.0098
0.0118
J1
0.250
0.300
0.350
0.0098
0.0118
0.0138
K
0.340
0.390
0.440
0.0134
0.0154
0.0173
L
0.350
0.400
0.450
0.0138
0.0157
0.0177
26 Pin DFN
Dimensions in Millimeters:
Controlling Dimension
Dimensions in Inches
Conversion Factor:
1 Inch = 25.40 mm
SIPEX Pkg Signoff Date/Rev: JL Feb16-06 / RevB
0.500 BSC
0.0197 BSC
15
Date: 2/14/06
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator Copyright 2006 Sipex Corporation
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
ORDERING INFORMATION
Part Number
Temperature
Package
SP7651ER ................................................. -40C to +85C ................................. 26 Pin 7 X 4 DFN
SP7651ER-L .............................................. -40C to +85C ............. (Lead Free) 26 Pin 7 X 4 DFN
SP7651ER/TR ........................................... -40C to +85C ................................. 26 Pin 7 X 4 DFN
SP7651ER-L/TR ........................................ -40C to +85C ............. (Lead Free) 26 Pin 7 X 4 DFN
Bulk Pack minimum quantity is 500.
/TR = Tape and Reel. Pack quantity is 3,000 DFN.
Solved By Sipex
TM
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
PDF 
ZIP