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43
s
3
s, 5
s or 10
s Sample/Conversion
Time
s
Standard
10V and
5V Input
s
No Missing Codes Over Temperature
s
AC Performance Over Temperature
71.5dB SignaltoNoise Ratio at Nyquist
85dB Spuriousfree Dynamic Range
at 49kHz
81dB Total Harmonic Distortion at 49kHz
s
Internal Sample/Hold, Reference,
Clock, and 3-State Outputs
s
Low Power Dissipation: 90mW
s
28Pin Narrow PDIP and SOIC
DESCRIPTION...
The SP85XX Series are complete 12-bit sampling A/D converters using stateoftheart
CMOS structures. They contain a complete 12bit successive approximation A/D converter
with internal sample/hold, reference, clock, digital interface for microprocessor control, and
threestate output drivers. Power dissipation is only 90mW. AC and DC performance are
completely specified. Sampling/conversion rates of 3
s, 5
s and 10
s are offered.
.....
.....
.....
.....
10V
CS
R/C HBE
IBIP
IN
5V
IN
Internal
Ref
Control
Logic
Clock
Comparator
Three
State
Parallel
Output
Data
Bus
BUSY
CDAC
V
REF
Out
(1.2043V)
SAR
Output
Latches
And
Three
State
Drivers
SP8503, SP8505, SP8510
12-Bit Sampling A/D Converters
44
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
S
to Digital Common ............................................................... +7V
Pin 26 (V
SO
) to Pin 27 (V
SA
) ....................................................
0.3V
Analog Common to Digital Common ......................................
0.3V
Control Inputs to Digital Common ....................... 0.3 to V
S
+ 0.3 V
Analog Input Voltage ...........................................................
16.5V
Maximum Junction Temperature ........................................... 160
C
Internal Power Dissipation .................................................. 750mW
Lead Temperature (soldering, 10s) ..................................... +300
C
Thermal Resistance.
JA
:
Plastic DIP ....................................................................... 50
C/W
SOIC .............................................................................. 100
C/W
SPECIFICATIONS
(T
A
= 25
C; Sampling Frequency, F
S
, = 333kHz for SP8503, 200kHz for SP8505, 100kHz for SP8510, V
S
= +5V, unless otherwise specified.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
ANALOG INPUT
Voltage Ranges
10V/
5V
V
Impedance
10V Range
4.7
6.7
8.7
k
T
MIN
T
A
T
MAX
5V Range
2.7
3.9
5.1
k
T
MIN
T
A
T
MAX
DC PERFORMANCE
Full Scale Error
Externally adjustable to zero;
K
0.1
0.50
%
T
MIN
T
A
T
MAX
Integral Linearity Error
Note 1
K
0.35
0.75
LSB
Differential Linearity Error
K
0.35
0.95
LSB
No Missing Codes
Guaranteed
Bipolar Zero
Externally adjustable to zero
K
1
5
LSB
T
MIN
T
A
T
MAX
VOLTAGE REFERENCE
Voltage Output
1.1440
1.2043
1.2645
V
Output Source Current
100
A
Output Resistance
280
AC PERFORMANCE
T
MIN
T
A
T
MAX
SP8503
Conversion Time
2.6
s
Complete Cycle
3.0
s
Throughput Rate
333
kHz
Spurious-Free Dynamic Range
Note 2
@ 49kHz
85
dB
@ 161kHz
72
dB
Total Harmonic Distortion
Note 2
@ 49kHz
81
dB
@ 161kHz
71
dB
Signal to Noise Ratio (SNR)
Note 2
@ 49kHz
71.5
dB
@ 161kHz
71.5
dB
Signal to (Noise + Distortion) Ratio
Note 2
@ 49kHz
71
dB
@ 161kHz
68
dB
SP8505
Conversion Time
4.5
s
Complete Cycle
5.0
s
Throughput Rate
200
kHz
Spurious-Free Dynamic Range
Note 2
@ 49kHz
85
dB
@ 97kHz
77
dB
45
SPECIFICATIONS
(continued)
(T
A
= 25
C; Sampling Frequency, F
S
, = 333kHz for SP8503, 200kHz for SP8505, 100kHz for SP8510, V
S
= +5V, unless otherwise specified.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
AC PERFORMANCE
T
MIN
T
A
T
MAX
SP8505
Total Harmonic Distortion
Note 2
@ 49kHz
81
dB
@ 97kHz
76
dB
Signal to Noise Ratio (SNR)
Note 2
@ 49kHz
71.5
dB
@ 97kHz
71.5
dB
Signal to (Noise + Distortion) Ratio
Note 2
@ 49kHz
71
dB
@ 97kHz
70
dB
SP8510
Conversion Time
9.5
s
Complete Cycle
10.0
s
Throughput Rate
100
kHz
Spurious-Free Dynamic Range
85
dB
@ 49kHz; Note 2
Total Harmonic Distortion
81
dB
@ 49kHz; Note 2
Signal to Noise Ratio (SNR)
71.5
dB
@ 49kHz; Note 2
Signal to (Noise + Distortion) Ratio
71
dB
@ 49kHz; Note 2
SAMPLING DYNAMICS
Aperture Delay
13
ns
Aperture Jitter
150
ps, rms
Transient Response
Note 3
K
150
ns
Overvoltage Recovery
150
ns
Note 4
DIGITAL INPUTS
Logic Levels
V
IL
0.3
+0.8
V
V
IH
+2.4
+5.3
V
I
IL
0.1
50
A
I
IH
5
A
DIGITAL OUTPUTS
Resolution
12
Bits
Data Format
Parallel; 12-bit or 8-bit/4-bit
Data Coding
Offset Binary
V
OL
0.0
+0.4
V
I
SINK
= 1.6mA
V
OH
+2.4
V
DD
V
I
SOURCE
= 1.6mA
I
LEAKAGE
(High-Z State)
0.1
5
A
POWER SUPPLY REQUIREMENTS
Rated Voltage
+4.75
+5.0
+5.25
V
V
S
(V
SA
and V
SD
)
Current
18
21
mA
I
S
Power Consumption
90
mW
ENVIRONMENTAL AND MECHANICAL
Specification
K
0
+70
C
Storage
65
+150
C
Package
KN
28pin Narrow DIP
KS
28pin SOIC
NOTES
1.
LSB means Least Significant Bit. For SP85XX Series, 1LSB = 2.44mV for
5V range, 1 LSB =
4.88mV for
10V range.
2.
All specifications in dB are referred to a full-scale input, either
10V or
5V.
3.
For full-scale step input, 12-bit accuracy attained in specified time.
4.
Recovers to specified performance in specified time after 2 x F
S
input overvoltage.
46
PINOUT
Pin 12 -- D
5
-- Data Bit 5 if HBE is LOW; LOW if
HBE is HIGH.
Pin 13 -- D
4
-- Data Bit 4 if HBE is LOW; LOW if
HBE is HIGH.
Pin 14 --N.C.--This pin is not internally connected.
Pin 15 --N.C.--This pin is not internally connected.
Pin 16-- DGND -- Digital Ground. Connect
to pin 5, at the device.
Pin 17 -- D
3
-- Data Bit 3 if HBE is LOW; Data Bit
11 if HBE is HIGH.
Pin 18 -- D
2
-- Data Bit 2 if HBE is LOW; Data Bit
10 if HBE is HIGH.
Pin 19-- D
1
-- Data Bit 1 if HBE is LOW; Data Bit
9 if HBE is HIGH.
Pin 20 -- D
0
-- Data Bit 0 if HBE is LOW. Least
Significant Bit (LSB). Data Bit 8 if HBE is HIGH.
Pin 21 -- HBE -- High Byte Enable, When held
LOW, data output as 12-bits in parallel. When held
HIGH, four MSBs presented on pins 1720, pins
10 13 output LOWs. Must be LOW to initiate
conversion.
Pin 22-- R/C -- Read/Convert. Falling edge initiates
conversion when CS is LOW, HBE is LOW, and
BUSY is HIGH.
Pin 23 -- CS -- Chip Select. Outputs in Hi-Z state
when HIGH. Must be LOW to initiate conversion or
read data.
Pin 24 -- BUSY. Output LOW during conver-
sion. Data valid on rising edge in Convert
Mode.
Pin 25 -- N.C. -- This pin is not internally connected.
Pin 26 -- V
SD
-- Positive Digital Power Supply, +5V.
Connect to pin 27, and bypass to DGND.
Pin 27 -- V
SA
-- Positive Analog Power Supply.
+5V. Connect to pin 26, and bypass to AGND.
Pin 28 -- N.C. -- This pin is not internally connected.
N.C. 1
10V IN 2
5V IN 3
VREF 4
AGND 5
D
11
6
D
10
7
D
9
8
D
8
9
D
7
10
D
6
11
D
5
12
D
4
13
N.C. 14
28 N.C.
27 V
SA
26 V
SD
25 N.C.
24 BUSY
23 CS
22 R/C
21 HBE
20 D
0
19 D
1
18 D
2
17 D
3
16 DGND
15 N.C.
SP8503
SP8505
SP8510
PIN ASSIGNMENT
Pin 1 --No Connection --This pin is not internally
connected.
Pin 2 -- IN
1
--
10V Analog Input. Connected to
AGND for
5V range.
Pin 3 -- IN
2
--
5V Analog Input. Connected to
AGND for
10V range.
Pin 4 -- V
REF
Internal Voltage. Reference Output.
Pin 5 -- AGND -- Analog Ground. Connect
to pin 16 at the device.
Pin 6 -- D
11
-- Data Bit 11. Most Significant Bit
(MSB).
Pin 7 -- D
10
-- Data Bit 10.
Pin 8-- D
9
-- Data Bit 9.
Pin 9 -- D
8
-- Data Bit 8.
Pin 10 -- D
7
-- Data Bit 7 if HBE is LOW; LOW if
HBE is HIGH.
Pin 11 -- D
6
-- Data Bit 6 if HBE is LOW; LOW if
HBE is HIGH.
47
edge can be used to read the data from the conver-
sion. Also, during conversion, the BUSY signal
puts the output data lines in Hi-Z states and inhibits
the input lines. This means that pulses on R/C are
ignored, so that new conversions cannot be initi-
ated during a conversion, either as a result of
spurious signals or to short-cycle the SP85XX
Series.
In the Read Mode, the input to R/C is kept nor-
mally LOW, and a HIGH pulse is used to read data
and initiate a conversion. In this mode, the rising
edge of R/C will enable the output data pins, and
the data from the previous conversion becomes
valid. The falling edge then puts the SP85XX
Series in a hold mode, and initiates a new conver-
sion.
The SP85XX Series will begin acquiring a new
sample just prior to the BUSY output rising, and
will track the input signal until the next conversion
is started.
For use with an 8-bit bus, the data can be read out in two
bytes under the control of HBE. With a LOW input
on HBE, at the end of a conversion, the 8 LSBs of data
are loaded into the output drivers on D
7
through D
4
and
D
3
through D
0
. Taking HBE HIGH then loads the 4
MSBs on D
3
through D
0
, with D
7
through D
4
being
forced LOW.
Analog Input Ranges
The SP85XX Series offers two standard bipolar
input ranges:
10V and
5V. If a
10V range is
required, the analog input signal should be con-
nected to pin 2. A signal requiring a
5V range
should be connected to pin 3. In either case, the
other pin of the two must be grounded or connected
to the adjustment circuits described in the section
on calibration.
Controlling The SP85XX Series
The SP85XX Series can be easily interfaced to most
microprocessor-based and other digital systems. The
microprocessor may take full control of each conver-
sion, or the SP85XX Series may operate in a stand-
alone mode, controlled only by the R/C input. Full
control consists of initiating the conversion and read-
ing the output data at user command, transmitting data
either all 12-bits in one parallel word, or in two 8-bit
bytes. The three control inputs (CS, R/C and HBE) are
FEATURES...
The SP85XX Series are specified at sampling
rates of 333kHz (SP8503), 200kHz (SP8505) or
100kHz (SP8510). Conversion times are factory
set for 2.70
s, 4.7
s and 9.7
s maximum, re-
spectively, over temperature, and the high-
speed sampling input stage insures a total acqui-
sition and conversion time of 3
s, 5
s and 10
s
maximum, respectively, over temperature. Pre-
cision, laser-trimmed scaling resistors provide
industrystandard input ranges of
5V or
10V.
The 28-pin SP85XX Series are available in
narrow body plastic DIP, and SOIC packages
and it operates from a single +5V supply.
The SP85XX Series are available in grades
specified over the 0
C to +70
C commercial
temperature ranges.
OPERATION
Basic Operation
Figure 1 shows the simple hookup circuit required
to operate the SP85XX Series in a
10V range in
the Convert Mode. A convert command arriving
on R/C puts the SP85XX Series in the HOLD
mode, and a conversion is started. This pulse must
be LOW for a minimum of 40ns. Because this
pulse establishes the sampling instant of the A/D,
it must have very low jitter. BUSY will be held
LOW during the conversion, and rises only after
the conversion is completed and the data has been
transferred to the output drivers. Thus, the rising
Figure 1. Basic
10V Operation
2
3
4
5
6
7
8
9
10
11
12
13
27
26
25
24
23
22
21
20
19
18
17
16
D0
(LSB)
Busy
Convert
Command
0.1F
6.8F +
+5V
+5V
+5V
N.C.
BUSY
CS
R/C
HBE
D0 (LSB)
D1
D2
D3
DGND
IN 1
IN 2
V
REF
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D11
(MSB)
Data
Out
Input
1
28
N.C.
N.C.
N.C.
N.C.
14
15
48
CS
R/C
HBE
BUSY
OPERATION
1
X
X
1
None outputs in Hi-Z state.
0
1
0
0
1
Holds signal and initiates conversion.
0
1
0
1
Output three-state buffers enabled once
conversion has finished.
0
1
1
1
Enable hi-byte in 8-bit bus mode.
0
1
0
1
1
Inhibit start of conversion.
0
0
1
1
None outputs in Hi-Z state.
X
X
X
0
Conversion in progress. Outputs Hi-Z
state. New conversion inhibited until
present conversion has finished.
Table 1. Control Line Functions
in Table 2. No other combination of states or transi-
tions will initiate a conversion. Conversion is inhibited
if either CS or HBE are HIGH, or if BUSY is LOW.
CS and HBE should be stable a minimum of 25ns
prior to the transition on R/C. Timing relationships for
start of conversion are illustrated in Figure 7.
The BUSY output indicates the current state of the
converter by being LOW only during conversion.
During this time the three-state output buffers remain
in a Hi-Z state, and therefore data cannot be read
during conversion. During this period, additional
transitions on the three digital inputs (CS, R/C and
HBE) will be ignored, so that conversion cannot be
prematurely terminated or restarted.
Internal Clock
The SP85XX Series has an internal clock that is
factory trimmed to achieve the typical conversion
times given in the specifications, and a maximum
conversion time over the full operating tempera-
ture range of 2.7
s, 4.7
s or 9.7
s, depending on
the model. No external adjustments are required,
and with the guaranteed maximum acquisition
time of 300ns, throughput performance is assured
with convert pulses as close as 3
s for the SP8503.
Reading Data
After conversion is initiated, the output buffers remain
in a Hi-Z state until the following three logic condi-
tions are simultaneously met: R/C is HIGH, BUSY is
HIGH and CS is LOW. Upon satisfying these condi-
tions, the data lines are enabled according to the state
of HBE. See Figure 7 for timing relationships and
specifications.
CALIBRATION...
Optional External Gain And Offset Trim
Offset and full-scale errors may be trimmed to zero
using external offset and full-scale trim potenti-
ometers connected to the SP85XX Series as shown
in Figure 3.
If adjustment of offset and full scale is not required,
connections as shown in Figure 2 should be used.
all TTL/CMOS compatible. The functions of the
control lines are shown in Table 1.
For stand-alone operation, control of the SP85XX
Series is accomplished by a single control line
connected to R/C. In this mode, CS and HBE are
connected to GND. The output data are presented
as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do
not require full bus interface capability.
Conversion is initiated by a HIGH-to-LOW transition
on R/C. The three-state data output buffers are enabled
when R/C is HIGH and BUSY is HIGH. Thus, there
are two possible modes of operation: conversion can
be initiated with either positive or negative pulses. In
either case, the R/C pulse must remain LOW a
minimum of 40ns.
Figure 5 illustrates timing when conversion is initi-
ated by an R/C pulse which goes LOW and returns
HIGH during the conversion. In this case (Convert
Mode), the three-state outputs go into the Hi-Z state in
response to the falling edge of R/C, and are enabled for
external access to the data after completion of the
conversion.
Figure 6 illustrates the timing when conversion is
initiated by a positive R/C pulse. In this mode (Read
Mode), the output data from the previous conversion
is enabled during the HIGH portion of R/C. A new
conversion starts on the falling edge of R/C, and the
three-state outputs return to the Hi-Z state until the next
occurrence of a HIGH on R/C.
Conversion Start
A conversion is initiated on the SP85XX Series only
by a negative transition occurring on R/C, as shown
Figure 2. a)
10V Range b)
5V Range -- Without Trims
2
3
10V
Input
SP8503/05/10
2
3
5V
Input
SP8503/05/10
49
INPUT VOLTAGE RANGE AND LSB VALUES
Input Voltage Range Defined As:
10V
5V
Analog Input Connected to Pin
2
3
Pin Connected to AGND
3
2
One Least Significant Bit (LSB)
FSR/2
12
20V/2
12
10V/2
12
4.88mV
2.44mV
OUTPUT TRANSITION VALUES
FFEH TO FFFH
+ FULL SCALE
+10V3/2LSB
+5V3/2LSB
+9.9927V
+4.9963V
7FFH TO 800H
Mid Scale
0V1/2LSB
0V1/2LSB
(Bipolar Zero)
2.44mV
1.22mV
000H to 001H
Full Scale
10V+1/2LSB
5V+1/2LSB
-9.9976V
-4.9988V
Table 2. Input Voltages, Transition Voltages and LSB Values
toggles on and off at code 1111 1111 1110
BIN
=
FFE
H
= 4094
DEC
.
10V Range Offset and Gain
Offset -- Apply 1.2622V to the
10V input at
pin 2. Adjust the offset potentiometer until the
LSB toggles on and off at code 1001 0000
0010
BIN
= 902
H
= 2306
DEC
.
Gain -- Apply 9.9927V to the
10V input at pin
2. Adjust the gain potentiometer until the LSB
toggles on and off at code 1111 1111 1110
BIN
=
FFE
H
= 4094
DEC
.
Layout Considerations
Because of the high resolution and linearity of
the SP85XX Series, system design problems
such as ground path resistance and contact resis-
tance become very important.
Calibration Procedure
Apply a precision input voltage source to your
chosen input range (
10V range at pin 2 or
5V
at pin 3). Set the A/D to convert continuously.
Monitor the output code. Trim the offset first,
then gain. Use the appropriate input voltages
and output target codes for your chosen input
range as follows. The recommended offset cali-
bration voltage values eliminate interaction be-
tween the offset and gain calibration
5V Range Offset and Gain
Offset -- Apply 1.5637V to the
5V input at pin
3. Adjust the offset potentiometer until the LSB
toggles on and off at code 1010 1000 0000
BIN
=
A80
H
= 2688
DEC
.
Gain -- Apply 4.9963V to the
5V input at pin
3. Adjust the gain potentiometer until the LSB
Figure 3. a)
10V Range b)
5V Range -- With External Trims
a)
b)
SP85XX
1
2
3
4
5
6
7
R
2
=100
10V
Input
GAIN ADJUST
100
10K
BIPOLAR ZERO ADJUST
R
1
=10K
499
15V
+5V
SP85XX
1
2
3
4
5
6
7
GAIN ADJUST
R
2
=100
5V
Input
R
1
=10KW
+5V
15V
1K
30.1K
301
50
The input resistance of the SP85XX Series is
6.3k
or 4.2K
(for the
10V and
5V ranges
respectively). To avoid introducing distortion, the
source resistance must be very low, or constant
with signal level. The output impedance provided
by most op amps is ideal. Pins 26 Digital Supply
Voltage (V
SD
) and 27 Analog Supply Voltage
(V
SA
) are brought out to separate pins to maximize
accuracy on the chip. They should be connected
together as close as possible to the unit. Pin 27 may
be slightly more sensitive than pin 26 to supply
variations, but to maintain maximum system accu-
racy, both should be wellisolated from digital
supplies with wide load variations.
To limit the effects of digital switching elsewhere
in a system on the analog performance of the
system, it often makes sense to run a separate +5V
supply conductor from the supply regulator to any
analog components requiring +5V, including the
SP85XX Series. If the SP85XX Series traces
cannot be separated back to the power supply
terminals, and therefore share the same trace as the
logic supply currents, then a 10 Ohm isolating
resistor should be used between the board supply
and pin 24 (V
DA
) and its bypass capacitors, to keep
V
DA
glitchfree. The V
S
pins (26 and 27) should be
connected together and bypassed with a parallel
combination of a 6.8
F Tantalum capacitor and a
0.1
F ceramic capacitor located close to the con-
verter to obtain noise-free operation. (See Figure
1). Noise on the power supply lines can degrade
converter performance, especially noise and spikes
from a switching power supply. Appropriate sup-
plies or filters must be used.
The GND pins (5 and 16) are also separated internally,
and should be directly connected to a ground plane
under the converter. A ground plane is usually the best
solution for preserving dynamic performance and
reducing noise coupling into sensitive converter cir-
cuits. Where any compromises must be made, the
common return of the analog input signal should be
referenced to pin 5, AGND, on the SP85XX Series,
which prevents any voltage drops that might occur in
the power supply common returns from appearing in
series with the input signal.
Coupling between analog input and digital lines should
be minimized by careful layout. For instance, if the
lines must cross, they should do so at right angles.
Parallel analog and digital lines should be separated
from each other by a pattern connected to common.
If external full scale and offset potentiometers are
used, the potentiometers and related resistors should
be located as close to the SP85XX Series as possible.
"Hot Socket" Precaution
Two separate +5V V
S
pins, 26 and 27, are used to
minimize noise caused by digital transients. If one
pin is powered and the other is not, the SP85XX
Figure 4. Acquisition and Conversion Timing
R/C
BUSY
Converter
Mode
Acquisition
Conversion
Acquisition
Conversion
t
AP
Hold Time
t
C
t
DBC
t
B
SYMBOL/PARAMETER
MIN.
TYP.
MAX.
UNITS
t
DBC
BUSY delay from R/C
80
150
ns
t
B
BUSY Low
2.5
2.7
s
SP8503
4.5
4.7
s
SP8505
9.5
9.7
s
SP8510
t
AP
Aperture Delay
13
ns
t
AP
Aperture Jitter
150
ps, rms
t
C
Conversion Time
2.47
2.70
s
SP8503
4.47
4.70
s
SP8505
9.47
9.70
s
SP8510
51
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data Valid
Hi-Z State
Hi-Z State
Data Valid
t
W
t
DBC
t
B
t
DBE
t
A
t
C
t
AP
t
HDR
and t
HL
t
DB
Figure 5. Convert Mode Timing -- R/C Pulse LOW, Outputs Enabled After Conversion
Series may draw excessive current. In normal
operation, this is not a problem because both pins
will be soldered together. However, during evalu-
ation, incoming inspection, repair, etc., where the
potential of a "Hot Socket" exists, care should be
taken to apply power to the SP85XX Series only
after it has been socketed.
Minimizing "Glitches"
Coupling of external transients into an analog-to-
digital converter can cause errors which are difficult to
debug. In addition to the discussions earlier on layout
considerations for supplies, bypassing and grounding,
there are several other useful steps that can be taken to
get the best analog performance out of a system using
the SP85XX Series. These potential system problem
sources are particularly important to consider when
developing a new system, and looking for the causes
of errors in breadboards.
First, care should be taken to avoid glitches during
critical times in the sampling and conversion process.
Since the SP85XX Series has an internal sample/hold
function, the signal that puts it into the hold state (R/C
going LOW) is critical, as it would be on any sample/
hold amplifier. The R/C falling edge should have a 5
to 10ns transition time, low jitter, and have minimal
ringing, especially during the 20ns after it falls.
R/C
BUSY
Converter
Mode
Data
BUS
Acquire
Convert
Acquire
Convert
Data
Valid
Hi-Z State
Hi-Z State
t
W
t
DBC
t
B
t
DBE
t
A
t
C
t
AP
t
HDR
and t
HL
t
AP
Data
Valid
Hi-Z State
t
DD
Figure 6. Read Mode Timing -- R/C Pulse HIGH, Outputs Enabled Only When R/C is High
52
AC DYNAMIC TIMING DATA
Naturally, transients on the analog input signal are to
be avoided, especially at times within
20ns of R/C
going LOW, when they may be trapped as part of the
charge on the capacitor array. This requires careful
layout of the circuit in front of the SP85XX Series.
Finally, in multiplexed systems, the timing relative to
when the multiplexer is switched may affect the
analog performance of the system. In most applica-
tions, the multiplexer can be switched as soon as R/C
goes LOW (with appropriate delays), but this may
affect the conversion if the switched signal shows
glitches or significant ringing at the SP85XX Series
input. Whenever possible, it is safer to wait until the
conversion is completed before switching and multi-
plexer. The extremely fast acquisition time and con-
version time of the SP85XX Series make this practi-
cal in many applications.
Although not normally required, it is also good prac-
tice to avoid glitches from coupling to the SP85XX
Series while bit decisions are being made. Since the
above discussion calls for a fast, clean rise and fall on
R/C, it makes sense to keep the rising edge of the
convert pulse outside the time when bit decisions are
being made. In other words, the convert pulse should
either be short (under 100ns so that it transitions before
the MSB decision), or relatively long (over 2.75
s to
transition after the LSB decision).
Next, although the data outputs are forced into a Hi-Z
state during conversion, fast bus transients can still be
capacitively coupled into the SP85XX Series. If the
data bus experiences fast transients during conver-
sion, these transients can be attenuated by adding a
logic buffer to the data outputs. The BUSY output can
be used to enable the buffer.
SYMBOL/PARAMETER
MIN .
TYP.
MAX.
UNITS
t
W
R/C Pulse Width
40
ns
t
DBC
BUSY delay from R/C
80
150
ns
t
B
BUSY LOW
2.47
2.7
s
t
AP
Aperture Delay
13
ns
t
AP
Aperture Jitter
150
ps, rms
t
C
Conversion Time
2.5
2.70
s
t
DBE
BUSY from End of Conversion
100
ns
t
DB
BUSY Delay after Data Valid
25
75
200
ns
t
A
Acquisition Time
130
300
ns
t
A
+ t
C
Throughput Time
SP8503
3.0
s
SP8505
5.0
s
SP8510
10.0
s
t
HDR
Valid Data Held After R/C LOW
20
50
ns
t
S
CS or HBE LOW before R/C Falls
25
5
ns
t
H
CS or HBE LOW after R/C Falls
25
0
ns
t
DD
Data Valid from CS LOW, R/C HIGH, and HBE
65
150
ns
in Desired State (Load = 100pF)
t
HL
Delay to Hi-Z State after R/C Falls or
50
150
ns
CS Rises (3K
Pullup or Pulldown
All parameters Guaranteed By Design.
53
Figure 7. Conversion Start Timing
R/C
BUSY
Data
BUS
CS or
HBE
Data Valid
Hi-Z State
t
S
t
H
t
W
t
DBC
t
HDR
and t
HL
ORDERING INFORMATION
0
C to +70
C
Model
Throughput
Package
SP8503KN .................................................................... 333kHz ................................................................................................ 28pin 0.3" Plastic DIP
SP8503KS .................................................................... 333kHz ........................................................................................................ 28pin, 0.3" SOIC
SP8505KN .................................................................... 200kHz ................................................................................................ 28pin 0.3" Plastic DIP
SP8505KS .................................................................... 200kHz ........................................................................................................ 28pin, 0.3" SOIC
SP8510KN .................................................................... 100kHz ................................................................................................ 28pin 0.3" Plastic DIP
SP8510KS .................................................................... 100kHz ........................................................................................................ 28pin, 0.3" SOIC
54
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