SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
1
SP9500
12Bit, Voltage Output D/A Converter
s
Low Power 1.1mW
s
Voltage Output, 0.5V to 4.5V Range
s
Single +5 Volt Supply
s
1.4 MHz Multiplying Bandwidth
(2-Quadrant)
s
Standard 3-Wire Serial Interface
s
8pin (0.15") SOIC and Plastic DIP
Packages
DESCRIPTION...
The SP9500 is a low power 12-Bit Digital-to-Analog Converter. It features 0.5 to 4.5V output
swing when using +5volt supply. The converter uses a standard 3wire serial interface
compatible with SPI
TM
, QSPI
TM
and Microwire
TM
. The output settling-time is specified at 7.5
s. The
SP9500 is available in 8pin 0.15" SOIC and DIP packages, specified over commercial and
industrial temperature ranges.
V
OUT
V
REF
DAC
SHIFT
REGISTER
D
IN
+
LATCH
AGND
SCLK
CS
DAC
REGISTER
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
- DGND .................................................................. -0.3V,+6.0V
V
REF
................................................................................ DGND, V
DD
AGND .......................................................................... DGND, V
REF
D
IN
.................................................................................. DGND, V
DD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/
C above +70
C)
Small Outline ...................................................................... 375mW
(derate 7mW/C above +70C)
SPECIFICATIONS
(Typical at 25C; T
MIN
T
A
T
MAX
; V
DD
= +5V, DGND = 0V, V
REF
= +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUTS
Logic Levels
V
IH
2.4
Volts
V
IL
0.8
Volts
2 Quad, Input Coding
Binary
REFERENCE INPUTS
Note 5
V
REF
Voltage Range
0.5
4.5
Volts
AGND Voltage Range
0.5
4.5
Volts
Input Resistance
11
13.9
k
D
IN
= 1365; code dependent
ANALOG OUTPUT
Gain
B, K
0.5
2.0
LSB
Note 3
A, J
1.0
4.0
LSB
Note 3
1.0
5.0
LSB
V
REF
= 4.5V; AGND = 0.5V
Initial Offset Bipolar
0.25
3.0
LSB
D
IN
= 0
Voltage Range
0.5
4.5
Volts
Output Current
1.0
mA
STATIC PERFORMANCE
Resolution
12
Bits
Integral Linearity
B, K
0.25
0.5
LSB
Note 3
A, J
0.5
1.0
LSB
Note 3
0.5
LSB
V
REF
= 4.5V; AGND = 0.5V
Differential Linearity
B, K
0.25
0.75
LSB
A, J
0.25
1.0
LSB
Monotonicity
Guaranteed
DYNAMIC PERFORMANCE
Settling Time
Small Signal
1
s
to 0.012%
Full Scale
7.5
s
to 0.012%, V
OUT
= 0.5 to 4.5V
Slew Rate
0.6
V/
s
Multiplying Bandwidth
1.4
MHz
STABILITY
Gain
15
ppm/C
t
MIN
to t
MAX
Scale Zero
15
ppm/C
t
MIN
to t
MAX
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
3
SPECIFICATIONS (continued)
(Typical at 25C; T
MIN
T
A
T
MAX
; V
DD
= +5V, DGND = 0V, V
REF
= +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
POWER REQUIREMENTS
Note 5
V
DD
+5V,
3%; Note 4, 5
J, K
0.22
0.34
mA
A, B
0.22
0.50
mA
Power Dissipation
1.1
mW
SWITCHING
CHARACTERISTICS
CS Setup Time
(t
CSS
)
25
ns
SCLK Fall to CS Fall
Hold Time
(t
CSH0
)
20
ns
SCLK Fall to CS Rise
Hold Time
(t
CSH1
)
0
ns
SCLK High Width
(t
CH
)
40
ns
SCLK Low Width
(t
CL
)
40
ns
DIN Setup Time
(t
DS
)
50
ns
DIN Hold Time
(t
DH
)
0
ns
CS High Pulse Width
(t
CSW
)
30
ns
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
J, K
0
+70
C
A, B
40
+85
C
Storage
60
+150
C
Package
_N
8-pin Plastic DIP
_S
8-pin 0.15" SOIC
Notes:
1.
Integral Linearity, for the SP9500, is measured as the arithmetic mean value of the magnitudes of the
greatest positive deviation and the greatest negative deviation from the theoretical value for any given
input condition.
2.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
3.
1 LSB = (V
REF
-AGND)/4,096.
4.
V
REF
= AGND = 2.5V.
5.
The following Power up sequence is recommended: V
DD
(+5V), V
REF
.
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
4
THEORY OF OPERATION
The SP9500 consists of four main functional
blocks the input shift register, DAC register,
12-Bit D/A converter and a output buffer
amplifier, Figure 1.
The input shift register is used to convert the
serial input data stream to a parallel 12Bit
digital word. The input data is shifted on posi-
tive clock (SCLK) edges when the Chip Select
(CS) signal is in the "low" state. The MSB is
loaded first and LSB last. No shifting of the
input data occurs when the Chip Select (CS)
signal is in the "high" state.
The DAC register is used to store the digital
word which is sent to the R2R DAC. Its value
is updated on the positive transition of the Chip
Select (CS) signal.
The 12Bit D/A converter is an "inverted" R-2R
ladder network. The DAC itself is implemented
with precision thin-film resistors and CMOS
transmission gate switches. The resistor net-
work is laser-trimmed to achieve better than 12
Bit accuracy. The D/A converter is used to
convert the 12-bit input word to a precision
voltage.
The operational amplifier is a rail-to-rail input,
rail-to-rail output CMOS amplifier. It is capable
of supplying 1mA of load current in the 1.5 to
3.5 output voltage range. The initial offset volt-
age is laser-trimmed to improve accuracy. Set-
tling time is 7.5
s for a full scale output transi-
tion to 0.012% accuracy.
INPUT
OUTPUT
MSB
LSB
1111
1111
1111
V
REF
- 1 LSB
1111
1111
1110
V
REF
- 2 LSB
0000
0000
0001
AGND + 1 LSB
0000
0000
0000
AGND
(V
REF
-AGND)
2
12
1 LSB =
Table 1. Binary Coding
FEATURES...
The SP9500 is a low power 12Bit Digital-to-
Analog Converter. The converter features 0.5 to
4.5 volt output swings with a single +5V supply.
The input coding format used is standard binary,
Table 1.
This Digital-to Analog Converter uses a stan-
dard 3wire interface compatible with SPI
TM
,
QSPI
TM
and Microwire
TM
. The output settling
time is specified at 7.5
s to full 12-bit accuracy
when driving a 10K
, 10pF load combination.
The SP9500 Digital-to-Analog Converter is
ideally suited for applications such as ATE,
process controllers, robotics and instrumenta-
tion. The SP9500 is available in an 8-pin 0.15"
SOIC and 0.3" PDIP packages, specified over
commercial and industrial temperature ranges.
PIN ASSIGNMENTS
Pin 1- V
OUT
- Voltage Output.
Pin 2- V
DD
- +5V Power Supply Input.
Pin 3- SCLK - Serial Clock Input.
Pin 4- D
IN
- Serial Data Input.
Pin 5- CS - Chip Select Input.
Pin 6 - DGND - Digital Ground
Pin 7- AGND - Analog Ground.
Pin 8- V
REF
- Reference Input.
V
OUT
1
2
3
4
8
7
6
5
V
DD
D
IN
V
REF
DGND
CS
AGND
SCLK
SP9500
PINOUT 8-PIN PLASTIC DIP & SOIC
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
5
V
OUT
V
REF
DAC
12
1
SHIFT
REGISTER
D
IN
+
+
D
IN
V
REF
V
OUT
V
DAC
V
OUT
V
DAC
V
DAC
D
IN
WHERE...
=
=
4096
x (V
REF
- AGND) + AGND
(
)
LATCH
12
AGND
AGND
DAC
REGISTER
DAC
REGISTER
Figure 1. Detailed Block Diagram
USING THE SP9500
External Reference
The R-2R DAC input resistance is code depen-
dent and is minimum (11k
) at code 1365 and
2731. And, it is nearly infinite at code 0. Be-
cause of the code-dependent nature of the refer-
ence inputs, a high quality, low output imped-
ance amplifier should be used to drive the V
REF
and AGND inputs.
Serial Clock and Update Rate
The SP9500 maximum serial clock rate (SCLK)
is given by 1/(t
CH
+t
CL
) which is approximately
12.5 MHz. The digital word update rate is lim-
ited by the chip select period, which is 12 X
Figure 2. Transfer Function
SCLK periods plus the CS high pulse width t
CSW
.
This is equal to a 1
s or 1 MHz update rate.
However, the DAC settling time to 12Bits is 7.5
s, which for full scale output transitions would
limit the update rate to 125 kHz.
Logic Interface
The SP9500 is designed to be compatible with
TTL and CMOS logic levels. However, driving
the digital inputs with TTL level signals will
increase the power consumption of the part by
300
A. In order to achieve the lowest power
consumption use rail-to-rail CMOS levels to
drive the digital inputs.
+0.5 lsb
DNLE
-0.5 lsb
+0.5 lsb
INLE
-0.5 lsb
0
CODE
4095
DNLE, INLE Plots
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
6
Figure 3. Timing Diagram
SCLK
DIN
CS
SK
SO
I/O
SI
N/C
SP9500
MICROWIRE
PORT
Figure 4. Microwire Connection
SCLK
DIN
CS
SK
MOSI
I/O
MISO
N/C
SPI
PORT
CPOL = 0, CPHA = 0
SP9500
Figure 5. SPI Connection
t
CSW
t
CSH1
t
CSS
t
CL
t
CH
t
CSHO
t
DS
t
DH
CS
SCLK
DIN
DB11
DB10
DB9
DB8
DB0
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
7
D
ALTERNATE
END PINS
(BOTH ENDS)
D1 = 0.005" min.
(0.127 min.)
E
PACKAGE: PLASTIC
DUALINLINE
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
A = 0.210" max.
(5.334 max).
E1
C
L
A2
A1 = 0.015" min.
(0.381min.)
B
B1
e = 0.100 BSC
(2.540 BSC)
e
A
= 0.300 BSC
(7.620 BSC)
A2
B
B1
C
D
E
E1
L
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.735/0.775
(18.669/19.685)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.355/0.400
(9.017/10.160)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
22PIN
8PIN
14PIN
16PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
1.145/1.155
(29.083/29.337)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.780/0.800
(19.812/20.320)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
18PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.880/0.920
(22.352/23.368)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
20PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.980/1.060
(24.892/26.924)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
8
D
E
H
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
8PIN
A
A1
L
B
e
h x 45
A
A1
B
D
E
e
H
h
L
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249
0.014/0.019
(0.35/0.49)
0.189/0.197
(4.80/5.00)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
14PIN
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249)
0.013/0.020
(0.330/0.508)
0.337/0.344
(8.552/8.748)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
16PIN
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249)
0.013/0.020
(0.330/0.508)
0.386/0.394
(9.802/10.000)
0.150/0.157
(3.802/3.988)
0.050 BSC
(1.270 BSC)
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
9
ORDERING INFORMATION
Model .................................................................................. Temperature Range ....................................................................................... Package
Monolithic 12-Bit DAC Voltage Output:
SP9500JN ................................................................................ 0C to +70C .......................................................................... 8-pin, 0.3" Plastic DIP
SP9500KN ............................................................................... 0C to +70C .......................................................................... 8-pin, 0.3" Plastic DIP
SP9500JS ................................................................................ 0C to +70C ................................................................................. 8pin, 0.15" SOIC
SP9500KS ............................................................................... 0C to +70C ................................................................................. 8pin, 0.15" SOIC
SP9500AN ............................................................................... 40C to +85C ...................................................................... 8-pin, 0.3" Plastic DIP
SP9500BN ............................................................................... 40C to +85C ...................................................................... 8-pin, 0.3" Plastic DIP
SP9500AS ............................................................................... 40C to +85C ............................................................................. 8pin, 0.15" SOIC
SP9500BS ............................................................................... 40C to +85C ............................................................................. 8pin, 0.15" SOIC
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
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