SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
1
s
Low Cost
s
Two 12-bit DAC's on a Single Chip
s
Low Power -- 40 mW (20mW/DAC)
s
Double-Buffered Inputs
s
5V Supply Operation
s
Voltage Outputs,
4.5V Range
s
Midscale Preset, Zero Volts Out
s
Guaranteed +0.5 LSB Max INL
s
Guaranteed +0.75 LSB Max DNL
s
2 MHz 4-Quadrant Multiplying Bandwidth
s
Separate Reference Inputs
s
28pin SOIC and Plastic DIP
Packages
s
Either 12 or 8 bit
p bus
DESCRIPTION
The SP9502 is a low power, dual version of the popular SP9345, Quad 12-Bit Digital-to-Analog
Converter. It features
4.5V output swings when using
5 volt supplies. The converter is double-
buffered for easy microprocessor interface. Each 12-bit DAC is independently addressable and
both DACS may be simultaneously updated using a single transfer command. The output
settling-time is specified at 4
s. The SP9502 is available in 28pin SOIC and DIP packages,
specified over commercial temperature range.
DAC
DAC
LATCH
LATCH
LATCH
LATCH
8 MSB's
4 LSB's
Ref In
1
Ref In
2
+
+
VOUT1
VOUT2
A
CS
WR1 B1/B2 WR2 XFER CLR
CONTROL LOGIC
INPUT
REGISTERS
DAC
REGISTERS
DATA
INPUTS
SP9502
Dual, 12Bit, Voltage Output D/A Converter
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
- GND ..................................................................... -0.3V,+6.0V
V
SS
- GND .................................................................... +0.3V, -6.0V
V
DD
- V
SS
......................................................................................................................
-0.3V, +12.0V
V
REF
..................................................................................... V
SS
, V
DD
D
IN
....................................................................................... V
SS
, V
DD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/
C above +70
C)
Small Outline ...................................................................... 375mW
(derate 7mW/C above +70C)
SPECIFICATIONS
(Typical at 25C, T
MIN
T
A
T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUTS
Logic Levels
V
IH
2.4
Volts
V
IL
0.8
Volts
4 Quad, Bipolar Coding
Offset Binary
REFERENCE INPUT
Voltage Range
+3
+4.5
Volts
Note 5
Input Resistance
6
8.8
k
D
IN
= 1877, code dependent
ANALOG OUTPUT
Gain
-K
+0.5
+2.0
LSB
V
REF
=
3V; Note 3
-J
+1.0
+4.0
LSB
V
REF
=
3V; Note 3
+1.0
+5.0
LSB
V
REF
=
4.5V; Note 3
Initial Offset Bipolar
+0.25
+3.0
LSB
D
IN
= 2,048
Voltage Range Bipolar
+3.0
+4.5
Volts
Output Current
+5.0
mA
V
REF
=
3V
+0.5
mA
V
REF
=
4.5V
STATIC PERFORMANCE
Resolution
12
Bits
Integral Linearity
-K
+0.25
+0.5
LSB
V
REF
=
3V; Note 3
-J
+0.5
+1.0
LSB
V
REF
=
3V; Note 3
+0.5
+3.0
LSB
V
REF
=
4.5V; Note 3
Differential Linearity
-K
+0.25
+0.75
LSB
-J
+0.25
+1.0
LSB
Monotonicity
Guaranteed
DYNAMIC PERFORMANCE
Settling Time
Small Signal
0.5
s
to 0.012%
Full Scale
4
s
to 0.012%
Slew Rate
4
V/
s
Multiplying Bandwidth
2
MHz
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
3
0
CODE
4095
INLE, DLNE Plots
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
SPECIFICATIONS (continued)
(Typical at 25C, T
MIN
T
A
T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
STABILITY
Gain
15
ppm/C
t
MIN
to t
MAX
Bipolar Zero
15
ppm/C
t
MIN
to t
MAX
SWITCHING CHARACTERISTICS
t
DS
Data Set Up Time
140
100
ns
to rising edge of WR1,
t
DN
Data Hold Time
0
ns
Figure 4
t
WR
Write Pulse Width
140
100
ns
t
XFER
Transfer Pulse Width
140
100
ns
t
WC
Total Write Command
280
200
ns
POWER REQUIREMENTS
Note 5
V
DD
+5V,
3%; Note 4, 5
J, K
4
6
mA
V
SS
-5V,
3%; Note 4, 5
J, K
4
6
mA
Power Dissipation
40
mW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-J, -K
0
+70
C
Storage
-60
+150
C
Package
_N
28pin Plastic DIP
_S
28pin SOIC
Notes:
1.
Integral Linearity, for the SP9502, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
2.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
3.
1 LSB = 2*V
REF
/4,096.
4.
V
REF
= 0V.
5.
The following power up sequence is recommended to avoid latch up: V
SS
(-5V), V
DD
(+5V), REFIN.
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
4
are forced to 1000 0000 0000 and the DAC outputs
will settle to OV. Active low.
Pin 13 -- WR1 -- Write Input1 -- In conjunction
with CS (pin 14), enables input register selection,
and controls the transfer of data from the input bus
to the input registers. Active low.
Pin 14 -- CS -- Chip Select -- Enables writing
data to input registers and/or transferring data from
input bus to DAC registers.
Pin 15 -- V
OUT1
-- Voltage Output from DAC1.
Pin 16 -- DB
11
-- Data Bit 11; most significant bit.
Pin 17 -- DB
10
-- Data Bit 10.
Pin 18 -- DB
9
-- Data Bit 9.
Pin 19 -- DB
8
-- Data Bit 8.
Pin 20 -- DB
7
-- Data Bit 7.
Pin 21 -- DB
6
-- Data Bit 6.
Pin 22 -- DB
5
-- Data Bit 5.
Pin 23 -- DB
4
-- Data Bit 4.
Pin 24 -- DB
3
-- Data Bit 3.
Pin 25 -- DB
2
-- Data Bit 2.
Pin 26 -- DB
1
-- Data Bit 1.
Pin 27 -- DB
0
-- Data Bit 0; LSB
Pin 28 -- N.C. -- No Connection.
PINOUT -- 28PIN SOIC & DIP
PIN ASSIGNMENTS
Pin 1 -- N.C. -- No Connection.
Pin 2 -- V
OUT 2
-- Voltage Output from DAC2.
Pin 3 -- V
SS
-- 5V Power Supply Input.
Pin 4 -- V
DD
-- +5V Power Supply Input.
Pin 5 -- CLR -- Clear. Gated with WR2 (pin 12).
Active low. Clears both DAC outputs to 0V.
Pin 6 -- REF IN2 -- Reference Input for DAC2.
Pin 7 -- GND -- Ground.
Pin 8 -- B1/B2 -- Byte 1/Byte 2 -- Selects Data
Input Format. A logic "1" on pin 8 selects the 12
bit mode, and all 12 data bits are presented to the
DAC(s) unchanged; a logic "0" selects the 8bit
mode, and the four LSBs are connected to the four
MSBs, allowing an 8bit MSBjustified interface.
Pin 9 -- A -- Address for DAC Selection -- A
logic "0" selects DAC 1; a logic "1" selects
DAC 2.
Pin 10 -- REF IN1 -- Reference Input for DAC1.
Pin 11 -- XFER -- Transfer. Gated with WR2
(pin 12); loads all DAC registers simultaneously.
Active low.
Pin 12 -- WR2 -- Write Input 2 -- In conjunction
with XFER (pin 11), controls the transfer of data
from the input registers to the DAC registers. In
conjunction with CLR (pin 5), the DAC registers
N.C.
V
OUT2
V
SS
V
DD
CLR
Ref In 2
GND
B1/B2
A
Ref In 1
XFER
WR2
WR1
CS
N.C.
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
V
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SP9502
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
5
most significant bits (MSBs), allowing an 8-bit
MSB-justified interface. All data inputs are
enabled using the CS signal in both modes. The
digital inputs are designed to be both TTL and 5V
CMOS compatible.
In order to reduce the DAC full scale output
sensitivity to the large weighting of the MSB's
found in conventional R-2R resistor ladders, the 3
MSB's are decoded into 8 equally weighted levels.
This reduces the contribution of each bit by a factor
of 4, thus, reducing the output sensitivity to mis-
matches in resistors and switches by the same
amount. Linearity errors and stability are both
improved for the same reasons. Each D/A con-
verter is separated from the data bus by two reg-
isters, each consisting of level-triggered latches,
Figure 1. The first register (input register) is 12-
bits wide. The input register is selected by the
address input A
0
and A
1
and is enabled by the CS
and WR1 signals. In the 8-bit mode, the enable
signal to the 8 MSB's is disabled by a logic low
on B1/B2 to allow the 4 LSB's to be updated. The
second register (DAC register), accepts the de-
coded 3 MSB's plus the 9 LSB's. The two DAC
registers are updated simultaneously for both
DAC's using the XFER and WR2 signals. Using
the CLR and WR2 signals or the power-on-reset,
(enabled when the power is switched on) the DAC
registers are set to 1000 0000 0000 and the DAC
outputs will settle to 0V.
Using the control logic inputs, the user has full
control of address decoding, chip enable, data
transfer and clearing of the DAC's. The control
logic inputs are level triggered, and like the data
inputs, are TTL and CMOS compatible. The truth
table (Table 2) shows the appropriate functions
associated with the states of the control logic
inputs.
The DACs themselves are implemented with a
precision thinfilm resistor network and CMOS
transmission gate switches. Each D/A converter is
used to convert the 12-bit input from its DAC
register to a precision voltage.
The bipolar voltage output of the SP9502 is
created on-chip from the DAC Voltage Output
(V
DAC
) by using an operational amplifier and two
feedback resistors connected as shown in Figure 2.
This configuration produces a
4.5V bipolar output
range with standard offset binary coding. (See Table 1)
THEORY OF OPERATION
The SP9502 consists of five main functional blocks
-- input data multiplexer, data registers, control
logic,12-bit D/A converters, and two bipolar
output voltage amplifiers. The input data multi-
plexer is designed to interface to either 12- or 8-bit
microprocessor data busses. The input data format
is controlled by the B1/B2 signal -- a logic "1"
selects the 12-bit mode, while a logic "0" selects
the 8-bit mode. In the 12-bit mode the data is
transferred to the input registers without changes
in its format. In the 8-bit mode, the four least
significant bits (LSBs) are connected to the four
FEATURES
The SP9502 is a low power, dual version of the
popular SP9345, Quad 12-Bit Digital-to-Analog
Converter. This Dual, Voltage Output, 12-Bit
Digital-to-Analog Converter features
4.5V output
swings when using
5 volt supplies. The input
coding format used is standard offset binary.
(Refer to Table 1 below.)
The converter utilizes double-buffering on each of
the 12 parallel digital inputs, for easy microprocessor
interface. Each 12-bit DAC is independently
addressable and both DACS may be simulta-
neously updated using a single XFER command.
The output settling-time is specified at 4
s to full
12bit accuracy when driving a 5Kohm, 50pf load
combination. The SP9502, Dual 12-Bit Digital-
to-Analog Converter is ideally suited for applica-
tions such as ATE, process controllers, robotics,
and instrumentation. The SP9502 is available in
28pin plastic SOIC and plastic DIP packages,
specified over the commercial (0
C to +70
C)
temperature range.
Table 1. Offset Binary Coding
INPUT
OUTPUT
MSB
LSB
1111
1111
1111
VREF - 1 LSB
1111
1111
1110
VREF - 2 LSB
1000
0000
0001
0 + 1 LSB
1000
0000
0000
0
0000
0000
0001
-VREF + 1 LSB
0000
0000
0000
-VREF
1 LSB =
2V
REF
2
12
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
6
USING THE SP9502 WITH
DOUBLE-BUFFERED INPUTS
Loading Data
To load a 12-bit word to the input register of each
DAC, using a 12-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set A (the DAC address) to the desired
DAC -- 0 = DAC
1
; 1 = DAC
2
.
3) Set D11 (MSB) through D0 (LSB) to the
desired digital input code.
4) Load the word to the selected DAC by
cycling WR1 and CS through the following
sequence:
"1" -- "0" -- "1"
5) Repeat sequence for each input register.
To load a 12-bit word to the input register of each
DAC, using an 8-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set D11 through D4 to the 8 MSB's of the
desired digital input code.
3) Load the 8 MSB's of the digital word to the
selected input register by cycling WR1 and
CS through the "1" -- "0" -- "1" sequence.
4) Reset B1/B2 from "1" ---- "0".
5) Set D11 (MSB) through D8 to the 4 LSB's
of the digital input code.
6) Load the 4 LSB's by cycling WR1 and CS
through the "1" -- "0" -- "1" sequence.
7) Repeat sequence for each input register
TRANSFERRING DATA
To transfer the 12-bit words in the two input
registers to the two DAC registers:
1) Set CLR=1, CS=1, WR1=1.
DAC
3 TO 7
DECODE
&
5 BITS
8BIT
LATCH
4-BIT
LATCH
DB11-DB8
DB7-DB4
Ref In
+
VOUT
4
4
4
4
4
MUX
4
4
4
8
12
DB3-DB0
INPUT
REGISTER
DAC
REGISTER
LATCH
40K 40K
Figure 1. Detailed Block Diagram (only one DAC shown)
2) Cycle WR2 and XFER through the "1" --
"0" -- "1" sequence.
To set the outputs of the two DAC's to 0V, cycle WR2
and CLR through the "1" -- "0" -- "1" sequence,
while keeping XFER=1.
ONE LATCH, OR NO LATCHES
The latches that form the registers can be used in a
"semi-" transparent mode, and a "fully-" transparent
mode. In order to use the SP9502 in either mode the
user must be interfaced to a 12-bit bus only (B1=1).
The semitransparent mode is set up such that the first
set of latches is transparent and the second set is used
to latch the incoming data. Data is latched into the
second set rather than the first set, in order to minimize
glitch energy induced from the data formatting. In this
mode, WR1 and CS are tied low, and WR2 and XFER
are used to strobe the data to the addressed DAC. Each
DAC is addressed using the address line A. After the
appropriate DAC has been selected and the data is
settled at the digital inputs, bringing WR2 and XFER
low will transfer the data to the addressed DAC. The
user should be sure to bring XFER and WR2 high
again so that the next selected DAC will not be
overwritten by the last digital code. This mode of
operation may be useful in applications where
preloading of the input registers is not necessary;
Figure 3, top.
A fully transparent mode is realized by tying WR1,
CS, WR2, and XFER all low. In this mode, anything
that is written on the 12-bit data bus will be passed
directly to the selected DAC. Since both latches are
not being used, the previous digital word will be
overwritten by the new data as soon as the address
changes. This may be useful should the user want
to calibrate a circuit, by taking full scale or zero
scale readings for both DAC's; Figure 3, bottom.
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
7
Figure 2. Transfer Function
ZEROING DAC OUTPUTS
While keeping XFER pin high, the DAC outputs can
be set to zero volts two different ways. The first
involves the CLR and WR2 pins. In normal operation,
the CLR pin is tied high, thus, disabling the clear
function. By cycling WR2 and CLR through "1"--
"0"--"1" sequence, a digital code of 1000 0000 0000
is written to both DAC registers, producing a half scale
output or zero volts. The second utilizes the built in
power-on-reset. Using this feature, the SP9502 can be
configured such that during power-up, the second
register will be digitally "zeroed", producing a zero
volt output at both DAC outputs. This is achieved by
powering the unit up with XFER in a high state. Thus,
with no external circuitry, the SP9502 can be
powered up with the analog outputs at a known,
zero volt output level.
TEMPORARILY FORCING
BOTH DAC OUTPUTS TO OV
Set WR1=1, CS=1, WR2=0, XFER=0. The DAC
registers can be temporarily forced to 1000 0000
0000 by bringing the CLR pin low. This will
cause the DAC outputs to 0V, while the CLR pin
remains low. When the CLR pin is brought back
high, the digital code at the DAC registers will
again appear at the DAC's digital inputs, and the
analog outputs will return to their previous
values.
V
In
+
V
Out
D
V
Out
=
1 x V
In
D
2048
( )
V
DAC
=
x V
In
D
4,096
V
DAC
A
CS
WR1
B1/B2
WR2
XFER
CLR
FUNCTION
0
1
1
X
X
Address DAC 1 and load input register
0
0
1
X
X
Address DAC 1 and load 4 LSBs
1
1
1
X
X
Address DAC 2 and load input register
1
0
1
X
X
Address DAC 2 and load 4 LSBs
X
**
**
X
1
Transfer data from input registers to DAC registers
X
X
X
X
1
Sets all DAC output voltages to 0V
X
1
1
X
0
0
Temporarily force both DAC output voltages to
0V, while CLR is low
X
1
X
X
X
X
X
Invalid state with any other control line active
X
X
1
X
X
X
X
Invalid state with any other control line active
X = Don't care; ** = Don't care; however, CS and WR1 = 1 will inhibit changes to the input registers.
Table 2. Control Logic Truth Table
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
8
H
L
H
L
H
L
CLR
XFER
WR2
140ns, t
H
L
H
L
H
L
WR2
CS
WR1
140ns, t
Data Transfer from
Input Register to DAC's
Loads Input Data to
First Set of Latches
WR
XFER
Figure 4. Timing
Figure 3. Latch Control Options -- (Top) SemiTransparent Latch Mode; (Bottom) FullyTransparent Latch Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
N.C.
V
OUT2
V
SS
V
DD
CLR
REF IN
2
GND
B1/B2
A
REF IN
1
XFER
WR2
WR1
CS
N.C.
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
V
OUT1
SP9502
+5V 5V
12Bit
Data
Bus
V
OUT2
V
OUT1
+3V
References GND
Address
Decode &
Control
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
N.C.
V
OUT2
V
SS
V
DD
CLR
REF IN
2
GND
B1/B2
A
REF IN
1
XFER
WR2
WR1
CS
N.C.
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
V
OUT1
SP9502
+5V 5V
12Bit
Data
Bus
V
OUT2
V
OUT1
+3V
References GND
Address
Decode &
Control
DAC Strobe
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
9
D
ALTERNATE
END PINS
(BOTH ENDS)
D1 = 0.005" min.
(0.127 min.)
E
PACKAGE: PLASTIC
DUALINLINE
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
A = 0.210" max.
(5.334 max).
E1
C
L
A2
A1 = 0.015" min.
(0.381min.)
B
B1
e = 0.100 BSC
(2.540 BSC)
e
A
= 0.300 BSC
(7.620 BSC)
A2
B
B1
C
D
E
E1
L
24PIN
0.115/0.195
(2.921/4.953)
0.014/0.023
(0.356/0.584)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
1.155/1.280
(29.33/32.51)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
28PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
1.385/1.454
(35.17/36.90)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0/ 15
(0/15)
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
10
D
E
H
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
14PIN
A
A1
L
B
e
A
A1
B
D
E
e
H
L
16PIN
0.090/0.104
(2.29/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.398/0.413
(10.10/10.49)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
18PIN
0.090/0.104
(2.29/2.649))
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.447/0.463
(11.35/11.74)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
20PIN
0.090/0.104
(2.29/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.496/0.512
(12.60/13.00)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC))
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
24PIN
0.090/0.104
(2.29/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.599/0.614
(15.20/15.59)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
28PIN
0.090/0.104
(2.29/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.697/0.713
(17.70/18.09)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
0.090/0.104
(2.29/2.649))
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.348/0.363
(8.83/9.22)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0/8
(0/8)
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
11
ORDERING INFORMATION
Model .................................................................................. Temperature Range ....................................................................................... Package
Monolithic 12-Bit Dual DAC Voltage Output:
SP9502JN ................................................................................ 0C to +70C ........................................................................ 28-pin, 0.3" Plastic DIP
SP9502KN ............................................................................... 0C to +70C ........................................................................ 28-pin, 0.3" Plastic DIP
SP9502JS ................................................................................ 0C to +70C ................................................................................. 28pin, 0.3" SOIC
SP9502KS ............................................................................... 0
C to +70
C ................................................................................ 28pin, 0.3" SOIC
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
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