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Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without
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for use in life-support devices and/or systems.
Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-102934 Rev A
Preliminary
The XD010-12S-D4F 10W power module is a
2-stage Class A/AB amplifier module for use in
the driver stages of CDMA RF power amplifiers
for cellular base stations. The power transis-
tors are fabricated using Sirenza's latest, high
performance LDMOS process. This unit oper-
ates from a single voltage and has internal
temperature compensation of the bias voltage
to ensure stable performance over the full tem-
perature range.
Key Specifications
Parameter
Description: Test Conditions
Z
in
= Z
out
= 50
, V
DD
= 28.0V, I
DD1
= 230mA,
I
DD2
= 150mA, T
Flange
= 25C
Unit
Min.
Typ.
Max.
Frequency
Frequency of Operation
MHz
869
894
P
1dB
Output Power at 1dB Compression, 880 MHz
W
16
Gain
Gain at 1W Output Power, 880MHz
dB
32
Gain Flatness
Peak to Peak Gain Variation, 869 - 894MHz
dB
0.2
IRL
Input Return Loss 1W Output Power, 869 - 894MHz
dB
-17
Efficiency
Drain Efficiency at 12W CW
%
33
Drain Efficiency at 2W CDMA (Single Carrier IS-95)
%
12
Drain Efficiency at 1W CDMA (Single Carrier IS-95)
%
7
Linearity
ACPR at 2W CDMA (Single Carrier IS-95)
dB
-51
ALT-1 at 2W CDMA (Single Carrier IS-95)
dB
-70
3
rd
Order IMD at 12W PEP (Two Tone)
dBc
-36
3
rd
Order IMD at 1W PEP (Two Tone)
dBc
-45
Delay
Signal Delay from Pin 1 to Pin 4
nS
2.5
Phase Linearity
Deviation from Linear Phase (Peak to Peak)
Deg
0.5
R
TH, j-l
Thermal Resistance Stage 1 (Junction to Case)
C/W
11
R
TH, j-2
Thermal Resistance Stage 2 (Junction to Case)
C/W
4
Functional Block Diagram
XD010-12S-D4F
869-894 MHz Class AB
10W Power Amplifier Module
Product Features
Applications
50 W RF impedance
10W Output P
1dB
Single Voltage Operation
High Gain: 32 dB Typical
High Efficiency
Advanced, XeMOS II LDMOS FETS
Temperature Compensation
Base Station PA driver
Repeater
CDMA
GSM / EDGE
Product Description
1
RF in
RF out
2
DC
28 V
DC
3
28 V
4
Stage 1
Temperature
Compensation
Stage 2
Case Flange = Ground
Temperature
Compensation
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
2
EDS-102934 Rev A
Preliminary
XD010-12S-D4F 869-894 MHz 10W Amp
Pin Out Description
Pin #
Function
Description
1
RF Input
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads.
Care must be taken to protect against video transients that may damage the active devices.
2
V
DD1
This is the bias feed for the 1
st
stage of the amplifier module. The gate bias is temperature compensated to
maintain constant current over the operating temperature range. See Note 1.
3
V
DD2
This is the bias feed for the 2
nd
stage of the amplifier module. The gate bias is temperature compensated to
maintain constant current over the operating temperature range. See Note 1.
4
RF Output
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads.
Care must be taken to protect against video transients that may damage the active devices.
Flange
Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the
board for optimum thermal and RF performance. See mounting instructions for recommendation.
Simplified Device Schematic
Case Flange = Ground
Q2
Temperature
Compensation
1
RF
in
Temperature
Compensation
Q1
Vdd1
2
RF
out
4
Vdd2
3
Absolute Maximum Ratings
Parameters
Value
Unit
1
st
Stage Bias Voltage (V
DD1
)
35
V
2
nd
Stage Bias Voltage (V
DD2
)
35
V
RF Input Power
+20
dBm
Load Impedance for Continuous Operation
Without Damage
5:1
VSWR
Output Device Channel Temperature
+200
C
Lead Temperature During Solder Reflow
+210
C
Operating Temperature Range
-20 to +90
C
Storage Temperature Range
-40 to +100
C
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation see
typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
The internal generated gate voltage is ther-
mally compensated to maintain constant qui-
escent current over the temperature range
listed in the data sheet. No compensation is
provided for gain changes with temperature.
This can only be provided with AGC external
to the module.
Note 2:
Internal RF decoupling is included on all bias
leads. No additional bypass elements are
required, however some applications may
require energy storage on the drain leads to
accommodate time-varying waveforms.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
3
EDS-102934 Rev A
Preliminary
XD010-12S-D4F 869-894 MHz 10W Amp
Output Power, Gain, Efficiency vs. Input Power
Freq=881 MHz, Vdd=28 V, T
Flange
=25
o
C
0
5
10
15
20
25
30
35
40
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
Input Power (W)
Ou
tp
u
t
P
o
w
e
r
(
W
)
,
Ga
in
(
d
B
)
, E
ffic
i
e
n
c
y
(
%
)
Output Power
Gain
Efficiency
Gain, Efficiency vs. Output Power over Temperature
Freq=881 MHz, Vdd=28 V, T
Flange
=-20
o
C, 25
o
C, 90
o
C
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10
12
14
16
Output Power (W)
Ga
in
(
d
B
)
,E
ffic
i
e
n
c
y
(
%
)
Gain, Temp= -20
Gain, Temp= 25
Gain, Temp= 90
Efficiency, Temp= -20
Efficiency, Temp= 25
Efficiency, Temp= 90
Gain, Efficiency, IRL vs. Frequency
Output Power=1 Watt, Vdd=28 V, T
Flange
=25
o
C
0
5
10
15
20
25
30
35
865
870
875
880
885
890
895
900
Frequency (MHz)
Gain (dB
)
,
E
f
f
i
ciency (%
)
-20
-19
-18
-17
-16
-15
-14
-13
-12
-11
-10
IR
L
(
d
B)
Gain
Efficiency
IRL
Gain, Efficiency, IRL, ACP, ALT1 vs. Frequency
Output Power= 1 Watt Vdd=28 V, T
Flange
=25
o
C
IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @
750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
0
5
10
15
20
25
30
35
865
870
875
880
885
890
895
900
Frequency (MHz)
Gai
n
(
d
B)
, Effi
ci
ency (
%
)
-80
-70
-60
-50
-40
-30
-20
-10
0
IR
L(
dB)
,
AC
P(
dB)
,
ALT
1
(
d
B
)
Gain
Efficiency
IRL
ACP
ALT1
Gain, ACP vs. Output Power over Temperature
Freq=881 MHz, Vdd=28 V, T
Flange
=-20
o
C, 25
o
C, 90
o
C
IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @
750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
10
15
20
25
30
35
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Power (W)
Gain (
d
B)
-70
-60
-50
-40
-30
-20
-10
0
AC
P (
d
B)
Gain @ -20
Gain @ 25
Gain @ 90
ACP @ -20
ACP @ 25
ACP @ 90
Gain, Efficiency, ACP, ALT1 vs. Output Power
Freq=881 MHz, Vdd=28 V, T
Flange
=25
o
C
IS95 standard, channel BW= 1.23 MHz.
ADJ BW= 30 KHz @ 750 KHz spacing.
ALT1 BW= 30 KHz @ 1980 KHz spacing.
0
5
10
15
20
25
30
35
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Power (W)
Ga
i
n
(d
B
)
, E
ffi
c
i
e
n
c
y
(%)
-80
-70
-60
-50
-40
-30
-20
-10
0
AC
P (dB),
ALT1 (dB)
Gain
Efficiency
ACP
ALT1
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
4
EDS-102934 Rev A
Preliminary
XD010-12S-D4F 869-894 MHz 10W Amp
Test Board Schematic with module attachments shown
Test Board Layout and Bill of Materials
Component
Description
Manufacturer
PCB
Rogers 4350, e
r
=3.5
Thickness=30mils
Rogers
J1, J2
SMA, RF, Panel Mount
Tab W / Flange
AMP
J3, J4
MTA Post Header, 5 Pin,
Rectangle, Polarized,
Surface Mount
AMP
C1, C2
Cap, 220mF 50V, -40 to
85
o
C, Electrolytic, G
Panasonic
C4, C6
Cap, 0.01mF, 100V, 10%,
1206
Johanson
C3, C5
Cap, 1000pF, 100V, 10%,
1206
Johanson
JP1 Header
SMT Header, Low Profile,
2mm
Specialty
Electronics
JP1 Shunt
Shunt, Mate to Header,
2mm
Specialty
Electronics
Mounting
Screws
4-40 X 0.250"
Various
To download Gerber files, DXF drawings, a detailed BOM, and
assembly recommendations for the test board with fixture
click here
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
5
EDS-102934 Rev A
Preliminary
XD010-12S-D4F 869-894 MHz 10W Amp
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3: Dimensions are in inches
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