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Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.

522 Almanor Ave., Sunnyvale, CA 94085

Phone: (800) SMI-MMIC

http://www.sirenza.com

EDS-102932 Rev B

Prelimi nary

The XD010-24S-D2F 10W power module is a

2-stage Class A/AB amplifier module for use in

the driver stages of CDMA RF power amplifi-

ers. The power transistors are fabricated using

Sirenza's latest, high performance LDMOS

process. This unit operates from a single volt-

age and has internal temperature compensa-

tion of the bias voltage to ensure consistant

performance over the full temperature range.

Key Specifications

Parameter

Description: Test Conditions

= Z

out

= 50

, V

= 28.0V, I

DD1

= 230mA,

DD2

= 150mA, T

Flange

= 25ºC

Unit

Min.

Typ.

Max.

Frequency

Frequency of Operation

MHz

1930

1990

1dB

Output Power at 1dB Compression

Gain

Gain at 1W Output Power

Gain Flatness

Peak to Peak Gain Variation, 1930-1990MHz

0.4

IRL

Input Return Loss 1W Output Power, 1930-1990MHz

Efficiency

Drain Efficiency at 10W CW output

Drain Efficiency at 2W CDMA (Single Carrier IS-95)

Drain Efficiency at 1W CDMA (Single Carrier IS-95)

6.5

Linearity

ACPR at 1W CDMA Power Output (Single Carrier IS-95)

-58

ALT-1 at 2W CDMA (Single Carrier IS-95)

-70

Order IMD at 10W PEP (Two Tone; 1MHz)

dBc

-32

Delay

Signal Delay from Pin 1 to Pin 5

2.9

Phase Linearity

Deviation from Linear Phase (Peak to Peak)

Deg

0.5

TH, j-l

Thermal Resistance Stage 1 (Junction to Case)

ºC/W

TH, j-2

Thermal Resistance Stage 2 (Junction to Case)

ºC/W

Functional Block Diagram

XD010-24S-D2F

1930-1990 MHz Class A/AB
10W CDMA Driver Amplifier

Product Features

Applications

50 W RF impedance

10W Output P

1dB

Single Voltage Operation

High Gain: 28 dB Typical

High Efficiency

Advanced, XeMOS LDMOS II FETS

Temperature Compensation

Base Station PA driver

Repeater

CDMA

GSM / EDGE

Product Description

Case Flange = Ground

Temperature
Compensation

28 V

RF in

Stage 1

RF out

28 V

Temperature
Compensation

Stage 2

522 Almanor Ave., Sunnyvale, CA 94085

Phone: (800) SMI-MMIC

http://www.sirenza.com

EDS-102932 Rev B

Preliminary

XD010-24S-D2F 1930-1990 MHz 10W

Pin Out Description

Pin #

Function

Description

RF Input

Module RF input. Care must be taken to protect against video transients that may damage the active devices.

DD1

This is the bias feed for the 1

stage of the amplifier module. The gate bias is temperature compensated to

maintain constant current over the operating temperature range. See Note 1.

3,4

DD2

This is the bias feed for the 2

stage of the amplifier module. The gate bias is temperature compensated to

maintain constant current over the operating temperature range. See Note 1.

RF Output

Module RF output. Care must be taken to protect against video transients that may damage the active devices.

Flange

Gnd

Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the

board for optimum thermal and RF performance. See mounting instructions for recommendation.

Simplified Device Schematic

Absolute Maximum Ratings

Parameters

Value

Unit

Stage Bias Voltage (V

DD1

)

Stage Bias Voltage (V

DD2

)

RF Input Power

+20

dBm

Load Impedance for Continuous Operation

Without Damage

5:1

VSWR

Output Device Channel Temperature

+200

ºC

Lead Temperature During Solder Reflow

+210

ºC

Operating Temperature Range

-20 to +90

ºC

Storage Temperature Range

-40 to +100

ºC

Operation of this device beyond any one of these limits may

cause permanent damage. For reliable continuous operation see

typical setup values specified in the table on page one.

Caution: ESD Sensitive

Appropriate precaution in handling, packaging
and testing devices must be observed.

Note 1:

The internal generated gate voltage is ther-
mally compensated to maintain constant qui-
escent current over the temperature range
listed in the data sheet. No compensation is
provided for gain changes with temperature.
This can only be provided with AGC external
to the module.

Note 2:

Internal RF decoupling is included on all bias
leads. No additional bypass elements are
required, however some applications may
require energy storage on the drain leads to
accommodate time-varying waveforms.

Case Flange = Ground

Temperature
Compensation

RF
in

Temperature
Compensation

Vdd1

out

4 Vdd2

522 Almanor Ave., Sunnyvale, CA 94085

Phone: (800) SMI-MMIC

http://www.sirenza.com

EDS-102932 Rev B

Preliminary

XD010-24S-D2F 1930-1990 MHz 10W

Gain and Efficiency vs. Output Power and Voltage

Freq=1960 MHz, Vdd=24V, 28 V, 32 V T

Flange

= 25°C

Output Power (W)

Gain (dB), E

fficiency (%)

Gain @ 24 VDC

Gain @ 28 VDC

Gain @ 32 VDC

Efficiency @ 24 VDC

Efficiency @ 28 VDC

Efficiency @ 32 VDC

ACPR and ALT1 vs. Output Power and Temperature

Freq=1960 MHz IS-95 Vdd=28 V, T

Flange

=-20°C, 25°C, 90°C

ACPR 885 kHz, 30 kHz

ALT1 1.25 MHz, 30 kHz

-70

-60

-50

-40

-30

-20

-10

0.5

1.5

2.5

Output Power (W)

ACPR (d

-100

-90

-80

-70

-60

-50

-40

-30

ACPR @ 25°C
ACPR @-20°C
ACPR @ 90°C
ALT1 @-20°C
ALT1 @ 25°C
ALT1 @ 90°C

Two Tone IMD vs. Output Power and Temperature

Freq=1960, 1961 MHz, Vdd=28 V, T

Flange

=-20

C, 25

C, 90

-60

-50

-40

-30

-20

-10

Output Power, Avg (W)

IMD

Bc)

IMD @ 25 C

IMD @ 90

IMD @ -20

Gain and Efficiency vs. Output Power and Temperature

Freq=1960 MHz, Vdd=28 V, T

Flange

=-20°C, 25°C, 90°C

Output Power (W)

i
n

Efficiency (%)

Gain @-20°C
Gain @ 25°C
Gain @ 90°C
Efficiency @-20°C
Efficiency @ 25°C
Efficiency @ 90°C

Gain, Efficiency and ACPR vs. Frequency

Freq=1960 MHz, Vdd=28 V, T

Flange

= 25°C

Output Power=2 Watts

1920

1930

1940

1950

1960

1970

1980

1990

2000

Frequency (MHz)

Gai

(dB), E

fficiency (%)

-60

-55

-50

-45

-40

-35

-30

-25

ACPR (dB)

Gain

Efficiency

ACPR

Gain, Output Power and Efficiency vs. Input Power

Freq=1960 MHz, Vdd=28 V, T

Flange

= 25°C

0.002

0.004

0.006

0.008

0.01

0.012

Input Power (W)

i
n

B), Ou

t
Po

r (W

), Effi

cy (%)

Pout

Gain

Efficiency

522 Almanor Ave., Sunnyvale, CA 94085

Phone: (800) SMI-MMIC

http://www.sirenza.com

EDS-102932 Rev B

Preliminary

XD010-24S-D2F 1930-1990 MHz 10W

Test Board Schematic with module attachments shown

Test Board Layout and Bill of Materials

Component

Description

Manufacturer

PCB

Rogers 4350, e

=3.5

Thickness=30mils

Rogers

J1, J2

SMA, RF, Panel Mount

Tab W / Flange

AMP

J3, J4

MTA Post Header, 5 Pin,

Rectangle, Polarized,

Surface Mount

AMP

C1, C2

Cap, 220mF 50V, -40 to

C, Electrolytic, G

Panasonic

C4, C6

Cap, 0.01mF, 100V, 10%,

1206

Johanson

C3, C5

Cap, 1000pF, 100V, 10%,

1206

Johanson

JP1 Header

SMT Header, Low Profile,

2mm

Specialty

Electronics

JP1 Shunt

Shunt, Mate to Header,

2mm

Specialty

Electronics

Mounting

Screws

4-40 X 0.250"

Various

To download Gerber files, DXF drawings, a detailed BOM, and
assembly recommendations for the test board with fixture

click here

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