The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1
EDS-102938 Rev C
869-894 MHz Class A
8 W Power Amplifier Module
Sirenza Microdevices' XD010-42S-D4F 8W power module is a robust 2-
stage Class A amplifier module for use in the driver stages of linear RF
power amplifiers of cellular base stations. The power transistors are fabri-
cated using Sirenza's latest, high performance LDMOS process. This unit
operates from a single voltage and has internal temperature compensation
of the bias voltage to ensure stable performance over the full temperature
range. It is internally matched to 50 ohms.
Key Specifications
Symbol
Parameter
Unit
Min.
Typ.
Max.
Frequency
Frequency of Operation
MHz
869
894
P
1dB
Output Power at 1dB Compression, 880 MHz
W
7
8
Gain
Gain at 1W Output Power (CW)
dB
28
30
Gain Flatness
Over Frequency at 1W Output (CW)
dB
0.4
1
IRL
Input Return Loss at 1W Output (CW) (50
Ref)
dB
14
20
Efficiency
Drain Efficiency at 8W CW Output
%
22
24
Drain Efficiency at 1W CDMA (Single Carrier IS-95)
%
3.5
Linearity
ACPR at 1W CDMA Output (Single Carrier IS-95, 9 Ch Fwd,
Offset=750KHz, ACPR Integrated Bandwidth)
dB
-50
ALT-1 at 1W CDMA (Single Carrier IS-95, 9 Ch Fwd,
Offset=1980KHz, ACPR Integrated Bandwidth)
dB
-75
3rd Order IMD at 8W PEP (Two Tone 1MHz Spacing)
dB
-28
-32
3rd Order IMD at 1W PEP (Two Tone 1MHz Spacing)
dBc
-40
-50
Delay
Signal Delay from Pin 1 to Pin 4
nS
3.9
Phase Linearity
Deviation from Linear Phase (Peak to Peak)
Deg
0.5
R
TH, j-l
Thermal Resistance Stage 1 (Junction to Case)
C/W
11
R
TH, j-2
Thermal Resistance Stage 2 (Junction to Case)
C/W
4
XD010-42S-D4F
Product Features
Applications
50 W RF impedance
8W Output P1dB Typical
Single Supply Operation : Nominally 28V
High Gain: 30 dB at 880 MHz
Advanced, XeMOS II LDMOS FETS
Temperature Compensation
Base Station PA driver
Repeater
CDMA
GSM / EDGE
Product Description
Test Conditions: Z
in
= Z
out
= 50
, V
DD
= 28.0V, I
DQ1
= 230mA, I
DQ2
= 700mA, T
Flange
= 25C
Functional Block Diagram
Bias
Network
Temperature
Compensation
V
D2
D1
V
RF out
RF in
Stage 2
Stage 1
1
2
3
4
Case Flange = Ground
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
2
EDS-102938 Rev C
Simplified Device Schematic
Absolute Maximum Ratings
Parameters
Value
Unit
1
st
Stage Bias Voltage (V
D1
)
35
V
2
nd
Stage Bias Voltage (V
D2
)
35
V
RF Input Power
+20
dBm
Load Impedance for Continuous Operation With-
out Damage
5:1
VSWR
Output Device Channel Temperature
+200
C
Base Plate Temperature: Operating with no
RF Present
+90
C
Operating Temperature Range
-20 to +90
C
Storage Temperature Range
-40 to +100
C
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
The internal generated gate voltage is thermally compensated
to maintain constant quiescent current over the temperature
range listed in the data sheet. No compensation is provided for
gain changes with temperature. This can only be provided with
AGC external to the module.
Note 2:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the drain leads to
accommodate time-varying waveforms.
Note 3:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700 C, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation
instructions.
Pin Description
Pin #
Function
Description
1
RF Input
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
2
V
D1
This is the drain voltage for the first stage. Nominally +28Vdc
3
V
D2
This is the drain voltage for the 2
nd
stage of the amplifier module. The 2
nd
stage gate bias is temperature compensated to
maintain constant quiscent drain current over the operating temperature range. See Note 1.
4
RF Output
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
Flange
Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza's web site.
Temperature
Compensation
Bias
Network
V
D2
D1
V
RF
1
Q1
Q2
2
3
4
Case Flange = Ground
in
out
RF
Quality Specifications
Parameter
Unit
Typical
ESD Rating
Human Body Model, JEDEC Document - JESD22-A114-B
V
8000
MTTF
85
o
C Leadframe, 200
o
C Channel
Hours
1.2 X 10
6
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
3
EDS-102938 Rev C
Gain and Input Return Loss vs. Frequency
Output Power=1 Watt, Vdd=28 V, T
Flange
=25
o
C
22
23
24
25
26
27
28
29
30
31
32
865
870
875
880
885
890
895
900
Frequency (MHz)
Ga
i
n
(
d
B
)
-24
-23
-22
-21
-20
-19
-18
-17
-16
-15
-14
I
nput
R
e
t
u
r
n
Los
s
(
d
B
)
Gain
Input Return Loss
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
Output Power (W)
Ga
i
n
(
d
B
)
-80
-70
-60
-50
-40
-30
-20
-10
0
AC
P (d
B),
A
L
T
1
(d
B
)
,
I
M
D
(d
Bc)
Two Tone Gain
IMD 1MHz Spacing
ACP
ALT1
Gain, IMD, ACP, ALT1 vs. Output Power
Freq=881 MHz, Vdd=28V, T
Flange
=25
o
C, IS-95
ADJ BW=30KHz @ 750 KHz spacing
ALT1 BW=30KHz @1980 KHz spacing
IMD @ 1 MHz spacing
Efficiency and Idd vs. Output Pow er and Tem perature
Freq=881 MHz, Vdd=28 V, T
Flange
=-20
o
C, 25
o
C, 90
o
C
0
5
10
15
20
25
30
35
40
0
2
4
6
8
10
12
Output Power (W)
E
f
f
i
ci
e
n
cy (
%
)
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
I
dd (
A
mp
s
)
Efficiency @-20C
Efficiency @25C
Efficiency @90C
Id @-20C
Id @ 25C
Id @ 90C
Two Tone IMD, ACP, ALT1 vs. Frequency
Output Power=1 Watt, Vdd=28 V, T
Flange
=25
o
C IS95 standard,
channel BW= 1.23 MHz, ADJ BW= 30 KHz@ 750 KHz spacing.
ALT1 BW= 30 KHz@1980 KHz spacing. IMD@1 MHz spacing.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
865
870
875
880
885
890
895
900
Frequency (MHz)
Two Tone IMD
ACP
ALT1
AC
P
(
dB
),
AL
T
1
(
dB
),
IM
D
(
dB
c
)
Gain and IMDs vs. Output Power and Voltage
Freq=881 and 882 MHz, Vdd=24 V, 28 V, 32 V
T
Flange
=25
o
C
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
Output Power (W)
Ga
i
n
(
d
B
)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
IM
D (
d
B
c
)
Gain @ 24 Volts
Gain @ 28 Volts
Gain @ 32 Volts
IMD @ 24 Volts
IMD @ 28 Volts
IMD @ 32 Volts
Gain and IMD vs. Output Power and Temperature
Freq=881 MHz, Vdd=28 V, T
Flange
=-20
o
C, 25
o
C, 90
o
C
13
15
17
19
21
23
25
27
29
31
33
0
1
2
3
4
5
6
Output Power (W)
Ga
i
n
(
d
B
)
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
IM
D
(
d
B
c
)
Gain @-20C
Gain @ 25C
Gain @ 90C
IMD @-20C
IMD @ 25C
IMD @ 90C
Typical Performance Curves
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
4
EDS-102938 Rev C
Test Board Schematic with module connections shown
Test Board Layout
To receive Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture, contact applications
support at
support@sirenza.com.
Data sheet for evaluation circuit (XD010-EVAL) available from Sirenza website.
Component
Description
Manufacturer
PCB
Rogers 4350, e
r
=3.5
Thickness=30mils
Rogers
J1, J2
SMA, RF, Panel Mount Tab W /
Flange
Johnson
J3
MTA Post Header, 6 Pin, Rect-
angle, Polarized, Surface
Mount
AMP
C1, C10
Cap, 10mF, 35V, 10%, Tant,
Elect, D
Kemet
C2, C20
Cap, 0.1mF, 100V, 10%, 1206
Johanson
C3, C30
Cap, 1000pF, 100V, 10%, 1206
Johanson
C25, C26
Cap, 68pF, 250V, 5%, 0603
ATC
C21, C22
Cap, 0.1mF, 100V, 10%, 0805
Panasonic
C23, C24
Cap, 1000pF, 100V, 10%, 0603
AVX
Mounting
Screws
4-40 X 0.250"
Various
Test Board Bill of Materials
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
5
EDS-102938 Rev C
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3: Dimensions are in inches
Refer to Application note AN-060 "Installation Instructions for XD Module Series" for additional mounting info. App note availbale at at www.sirenza.com