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Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-105061 Rev B
The XD010-51S-D4F 12.5W power module is
a 2-stage Class A/AB amplifier module for use
as a driver stage in many 900 MHz applica-
tions. This unit operates from a positive single
voltage and has internal temperature compen-
sation of the bias voltage to ensure stable per-
formance over the full temperature range.
Key Specifications
Parameter
Description: Test Conditions
Z
in
= Z
out
= 50
, V
DD
= 28.0V, I
DD1
= 230mA,
I
DD2
= 158mA, T
Flange
= 25C
Unit
Min.
Typ.
Max.
Frequency
Frequency of Operation
MHz
902
928
P
1dB
Output Power at 1dB Compression, 915MHz
W
12.5
15
Gain
Gain at 10W Output Power (CW)
dB
30
32
Gain Flatness
Peak to Peak Gain Variation at 10W (CW)
dB
.7
1.5
IRL
Input Return Loss 10W CW
dB
14
18
Efficiency
Drain Efficiency at 10W CW
%
25
30
Linearity
3
rd
Order IMD at 10W PEP (Two Tone), 1MHz Spacing
dBc
-35
-30
Delay
Signal Delay from Pin 1 to Pin 4
nS
2.5
Phase Linearity
Deviation from Linear Phase (Peak to Peak)
Deg
0.5
R
TH, j-l
Thermal Resistance Stage 1 (Junction to Case)
C/W
11
R
TH, j-2
Thermal Resistance Stage 2 (Junction to Case)
C/W
4
Functional Block Diagram
XD010-51S-D4F
902-928 MHz Class A/AB
10W Power Amplifier Module
Product Features
Applications
50 W RF impedance
12.5W Output P
1dB
Single Voltage Operation
High Gain: 32 dB Typical
Advanced, XeMOS II LDMOS FETS
RFID
Point to Multipoint data radio systems
Product Description
Temperature
Compensation
28 V
DC
2
Case Flange = Ground
RF in
28 V
1
DC
RF out
3
4
Quality Specifications
Parameter
Unit
Min
Typical
Max
ESD Rating
Human Body Model, JEDEC Document - JESD22-A114-B
V
8000
-
-
MTTF
85
o
C Leadframe, 200
o
C Channel
H
-
1.2 X 10
6
-
R
TH, j-l
Thermal Resistance Stage 1 (Junction to Case)
C/W
-
5.5
-
R
TH, j-2
Thermal Resistance Stage 2 (Junction to Case)
C/W
-
2
-
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
2
EDS-105061 Rev B
XD010-51S-D4F 902-928 MHz 10W Amp
Pin Out Description
Pin #
Function
Description
1
RF Input
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads.
Care must be taken to protect against video transients that may damage the active devices.
2
V
DD1
This is the bias feed for the 1
st
stage of the amplifier module.
3
V
DD2
This is the bias feed for the 2
nd
stage of the amplifier module. The gate bias is temperature compensated to
maintain constant current over the operating temperature range. See Note 1.
4
RF Output
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads.
Care must be taken to protect against video transients that may damage the active devices.
Flange
Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the
board for optimum thermal and RF performance. See mounting instructions for recommendation.
Simplified Device Schematic
Absolute Maximum Ratings
Parameters
Value
Unit
1
st
Stage Bias Voltage (V
DD1
)
35
V
2
nd
Stage Bias Voltage (V
DD2
)
35
V
RF Input Power
+20
dBm
Load Impedance for Continuous Operation
Without Damage
5:1
VSWR
Output Device Channel Temperature
+200
C
Lead Temperature During Solder Reflow
+210
C
Operating Temperature Range
-20 to +90
C
Storage Temperature Range
-40 to +100
C
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation see
typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
The internal generated gate voltage is ther-
mally compensated to maintain constant qui-
escent current over the temperature range
listed in the data sheet. No compensation is
provided for gain changes with temperature.
This can only be provided with AGC external
to the module.
Note 2:
Internal RF decoupling is included on all bias
leads. No additional bypass elements are
required, however some applications may
require energy storage on the drain leads to
accommodate time-varying waveforms.
Bias Network
RF
in
1
Q1
Case Flange = Ground
Temperature
Compensation
Q2
Vdd1
2
3
Vdd2
4
RF
out
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
3
EDS-105061 Rev B
XD010-51S-D4F 902-928 MHz 10W Amp
Test Board Schematic with module attachments
Test Board Layout and Bill of Materials
Component
Description
Manufacturer
PCB
Rogers 4350, e
r
=3.5
Thickness=30mils
Rogers
J1, J2
SMA, RF, Panel Mount
Tab W / Flange
Johnson
J3
MTA Post Header, 6 Pin,
Rectangle, Polarized,
Surface Mount
AMP
C1, C10
Cap, 10mF, 35V, 10%,
Tant, Elect, D
Kemet
C2, C20
Cap, 0.1mF, 100V, 10%,
1206
Johanson
C3, C30
Cap, 1000pF, 100V, 10%,
1206
Johanson
C25, C26
Cap, 68pF, 250V, 5%,
0603
ATC
C21, C22
Cap, 0.1mF, 100V, 10%,
0805
Panasonic
C23, C24
Cap, 1000pF, 100V, 10%,
0603
AVX
Mounting
Screws
4-40 X 0.250"
Various
To receive Gerber files, DXF drawings, a detailed BOM, and
assembly recommendations for the test board with fixture,
contact applications support at
support@sirenza.com
. Data
sheet for evaluation circuit (XD010-EVAL) available from
Sirenza website.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
4
EDS-105061 Rev B
XD010-51S-D4F 902-928 MHz 10W Amp
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3: Dimensions are in inches
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