1625-1675The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and
all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1
EDS-105061 Rev C
Sirenza Microdevices' XD010-51S-D4F 15W power module is a robust 2-
stage Class A/AB amplifier module is a driver stage in many 900 MHz
applications. The power transistors are fabricated using Sirenza's latest,
high performance LDMOS process. This unit operates from a single volt-
age supply and has internal temperature compensation of the bias volt-
age to ensure stable performance over the full temperature range. It is a
drop-in, no-tune solution for medium power applications requiring high effi-
ciency, excellent linearity, and unit-to-unit repeatability. It is internally
matched to 50 ohms.
Key Specifications
Symbol
Parameter
Unit
Min.
Typ.
Max.
Frequency
Frequency of Operation
MHz
902
928
P
1dB
Output Power at 1dB Compression, 915MHz
W
12.5
15
Gain
Gain at 10W Output Power (CW)
dB
30
32
Gain Flatness
Peak to Peak Gain Variation at 10W (CW)
dB
0.7
1.5
IRL
Input Return Loss 10W CW
dB
14
18
Efficiency
Drain Efficiency at 10W CW
%
25
30
Linearity
3
rd
Order IMD at 10W PEP (Two Tone), 1MHz Spacing
dBc
-35
-30
Delay
Signal Delay from Pin 1 to Pin 4
nS
2.5
Phase Linearity
Deviation from Linear Phase (Peak to Peak)
Deg
0.5
R
TH, j-l
Thermal Resistance Stage 1 (Junction-to-Case)
C/W
11
R
TH, j-2
Thermal Resistance Stage 2 (Junction-to-Case)
C/W
4
Functional Block Diagram
XD010-51S-D4F
902-928 MHz Class A/AB
15W Power Amplifier Module
Product Features
Applications
50 W RF impedance
15W Output P
1dB
Single Supply Operation : Nominally 28V
High Gain: 32 dB at 915 MHz
High Efficiency: 30% at 915 MHz
Robust 8000V ESD (HBM), Class 3B
XeMOS II LDMOS FETS
Temperature Compensation
RFID
Point to Multipoint data radio systems
Product Description
Test Conditions Z
in
= Z
out
= 50
, V
DD
= 28.0V, I
DQ1
= 230 mA, I
DQ2
=158 mA, T
Flange
= 25C
Bias
Network
Temperature
Compensation
V
D2
D1
V
RF out
RF in
Stage 2
Stage 1
1
2
3
4
Case Flange = Ground
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
2
EDS-105061 Rev C
Pin Description
Pin #
Function
Description
1
RF Input
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
2
V
D1
This is the drain voltage for the first stage. Nominally +28Vdc
3
V
D2
This is the drain voltage for the 2
nd
stage of the amplifier module. The 2
nd
stage gate bias is temperature compensated to
maintain constant quiscent drain current over the operating temperature range. See Note 1.
4
RF Output
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
Flange
Gnd
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza's web site.
Simplified Device Schematic
Absolute Maximum Ratings
Parameters
Value
Unit
1
st
Stage Bias Voltage (V
D1
)
35
V
2
nd
Stage Bias Voltage (V
D2
)
35
V
RF Input Power
+20
dBm
Load Impedance for Continuous Operation With-
out Damage
5:1
VSWR
Output Device Channel Temperature
+200
C
Operating Temperature Range
-20 to +90
C
Storage Temperature Range
-40 to +100
C
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
The internally generated gate voltage is thermally compen-
sated to maintain constant quiescent current over the temper-
ature range listed in the data sheet. No compensation is
provided for gain changes with temperature. This can only be
accomplished with AGC external to the module.
Note 2:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the drain leads to
accommodate time-varying waveforms.
Note 3:
This module was designed to have its leads hand soldered to
an adjacent PCB. The maximum soldering iron tip tempera-
ture should not exceed 700 C, and the soldering iron tip
should not be in direct contact with the lead for longer than 10
seconds. Refer to app note AN060 (www.sirenza.com) for fur-
ther installation instructions.
Temperature
Compensation
Bias
Network
V
D2
D1
V
RF
1
Q1
Q2
2
3
4
Case Flange = Ground
in
out
RF
Quality Specifications
Parameter
Unit
Typical
ESD Rating
Human Body Model, JEDEC Document - JESD22-A114-B
V
8000
MTTF
85
o
C Leadframe, 200
o
C Channel
Hours
1.2 X 10
6
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
3
EDS-105061 Rev C
Typical Performance Curves
2 Tone Gain, Efficiency, Linearity and IRL vs Frequency
Vdd=28V, Pout=10W PEP, Delta F=1 MHz
0
5
10
15
20
25
30
35
40
45
50
880
890
900
910
920
930
940
950
Frequency (MHz)
G
a
i
n
(
d
B
)
,
E
f
f
i
ci
e
n
cy (
%
)
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
IMD
(
d
B
c
)
, IR
L
(
d
B
)
Gain
Efficiency
IM3
IM5
IM7
IRL
2 Tone Gain, Efficiency, Linearity vs Pout
Vdd=28V, Freq=915 MHz, Delta F=1 MHz
0
5
10
15
20
25
30
35
40
45
50
0
2
4
6
8
10
12
14
16
Pout (W PEP)
Ga
i
n
(
d
B
)
,
E
f
f
i
ci
e
n
cy (
%
)
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
IM
D
(
d
B
c
)
Gain
Efficiency
IM3
IM5
IM7
CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Pout=10W
25
27.5
30
32.5
35
37.5
40
880
890
900
910
920
930
940
950
Frequency (MHz)
G
a
i
n
(d
B
)
, E
f
f
i
c
i
e
n
c
y
(
%
)
-30
-27.5
-25
-22.5
-20
-17.5
-15
I
nput
R
e
t
u
r
n
Lo
s
s
(
d
B
)
Gain
Efficiency
IRL
CW Gain, Efficiency vs Pout
Vdd=28V, Freq=915 MHz
30.5
30.75
31
31.25
31.5
31.75
32
32.25
32.5
0
2
4
6
8
10
12
14
16
Pout (W)
Ga
i
n
(
d
B
)
0
10
20
30
40
50
60
E
f
f
i
ci
e
n
c
y (
%
)
Gain
Efficiency
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
4
EDS-105061 Rev C
Test Board Schematic with module connections shown
Test Board Layout
To receive Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture, contact applications sup-
port at
support@sirenza.com.
Data sheet for evaluation circuit (XD010-EVAL) available from Sirenza website.
Component
Description
Manufacturer
PCB
Rogers 4350, e
r
=3.5
Thickness=30mils
Rogers
J1, J2
SMA, RF, Panel Mount Tab W /
Flange
Johnson
J3
MTA Post Header, 6 Pin, Rect-
angle, Polarized, Surface
Mount
AMP
C1, C10
Cap, 10mF, 35V, 10%, Tant,
Elect, D
Kemet
C2, C20
Cap, 0.1mF, 100V, 10%, 1206
Johanson
C3, C30
Cap, 1000pF, 100V, 10%, 1206
Johanson
C25, C26
Cap, 68pF, 250V, 5%, 0603
ATC
C21, C22
Cap, 0.1mF, 100V, 10%, 0805
Panasonic
C23, C24
Cap, 1000pF, 100V, 10%, 0603
AVX
Mounting
Screws
4-40 X 0.250"
Various
Test Board Bill of Materials
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
5
EDS-105061 Rev C
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3: Dimensions are in inches
Refer to Application note AN-060 "Installation Instructions for XD Module Series" for additional mounting info. App note availbale at at www.sirenza.com
Package Outline Drawing
PDF 
ZIP