Sitronix

ST7065C

40CH Segment/Common Driver for Dot Matrix LCD

V1.4a

2001/08/29

1/13

Functions:

Dot matrix LCD driver with two 20 channel

outputs

Selectable function to use common/segment

drivers simultaneously

Bias voltage (V1 ~ V6)

Input/output signals

Input : Serial display data and control

pulse from controller IC

Output : 20 X 2 channels waveform for

LCD driving

Features:

Display driving bias : static to 1/5

Power supply for logic : 2.7V ~ 5.5V

Power supply for LCD voltage (V

) :

3V ~ 11V

64 Pin QFP package and bare chip available

Description:

ST7065C is a segment/common driver for dot

matrix type LCD display. It features 40 channels

with 20 X 2 bits bi-directional shift registers, data

latches, LCD drivers and logic control circuits. It

is fabricated by high voltage CMOS process with

low current consumption.

The ST7065C can convert serial data received

from a LCD controller, such as ST7066U, into

parallel data and send out LCD driving

waveforms to the LCD panel. The ST7065C is

designed for general-purpose LCD drivers. It can

drive both static and dynamic drive LCD. The LSI

can be used as segment/common driver.

The ST7065C has pin function compatibility with

the KS0065B that allows the user easily to

replace it with a ST7065C.

ST7065C

V1.4a

2001/08/29

2/13

ST7065C Specification Revision History

Version Date

Description

1.1 2000/07/31

First

Edition

1.2

2000/11/14 Added QFP Pad Configuration(Page 4)

1.3 2001/04/18

Moved QFP Package Dimensions(Page 13) to Page 4
Change Shift Register Table(Page 8)

1.4

2001/05/04 ST7065 Transition to ST7065C

1.4a

2001/08/29 Added "Substrate connect to VDD"(Page 3)

ST7065C

V1.4a

2001/08/29

3/13

Size : 2310x1830m
Coordinate : center
Min. PAD Pitch : 120m
PAD Size : 85x90m

(0,0)

G798E

"G798E" Marking : Easy to find the PAD

Substrate connect to VDD.

Functional Block Diagram

Pad Arrangement

SEGMENT DRIVER

BIDIRECTIONAL

SHIFTER(20bits)

BIDIRECTIONAL

SHIFTER(20bits)

DATA LATCH(20bits)

CONTOL

V1
V2
V3
V4

CL2

CL1

DL1 SHL1 DR1

DL2 SHL2 DR2

S1...............................S20

S21...............................S40

V5
V6

FCS

ST7065C

V1.4a

2001/08/29

5/13

Pad Configuration(QFP 64)

N
C

S
3
4

S
3
3

S
3
2

3
1

S
3
0

N
C

S
3
5

S
3
6

S
3
7

3
8

S
3
9

S
4
0

S
0
9

S
1
0

S
1
1

S
0
8

0
7

V
D
D

N
C

S
0
6

S
0
5

S
0
4

0
3

S
0
2

S
0
1

6
4

6
3

6
2

6
1

6
0

5
9

5
8

5
7

5
6

5
5

5
4

5
3

5
2

2
0

2
1

2
2

2
3

2
4

2
5

2
6

2
7

2
8

2
9

3
0

3
1

3
2

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

FCS

SHL2

SHL1

DR2

DL2

DR1

DL1

VSS

CL2

CL1

VEE

ST7065C

V1.4a

2001/08/29

6/13

Pad Name and Coordinates

Pad No. Pad Name

1 VEE

-1045

-670

31 S[28]

1040

800

2 CL1

-1040

-805

32 S[27]

910

805

3 CL2

-910

-805

33 S[26]

780

805

4 VSS

-780

-805

34 S[25]

660

805

5 DL1

-660

-805

35 S[24]

540

805

6 DR1 -540 -805

36 S[23] 420 805

7 DL2

-420

-805

37 S[22]

300

805

8 DR2 -300 -805

38 S[21] 180 805

9 M

-180

-805

S[20]

805

10 SHL1 -60 -805

40 S[19] -60 805

11 SHL2 60 -805

41 S[18] -180 805

12 FCS 180 -805

42 S[17] -300 805

13 V1 300 -805

43 S[16] -420 805

14 V2 420 -805

44 S[15] -540 805

15 V3 540 -805

45 S[14] -660 805

16 V4 660 -805

46 S[13] -780 805

17 V5 780 -805

47 S[12] -910 805

18 V6 910

-805

48 S[9]

-1040

800

19 S[40] 1040 -800 49 S[10] -1045 670
20 S[39] 1045 -623 50 S[11] -1045 540
21 S[38] 1045 -488 51 S[8] -1045 420
22 S[37] 1045 -358 52 S[7] -1045 300
23 S[36] 1045 -233 53 VDD -1045 180
24 S[35]

1045

-108

54 S[6] -1045 60

25 S[30]

1045 20

55 S[5] -1045

-60

26 S[31]

1045 145

56 S[4] -1045

-180

27 S[32]

1045 270

57 S[3] -1045

-300

28 S[33]

1045 395

58 S[2] -1045

-420

29 S[34]

1045 525

59 S[1] -1045

-540

30 S[29]

1045 655

ST7065C

V1.4a

2001/08/29

7/13

Pin Description:

Pin Name

Purpose

Description

I/O

VDD POWER

for

logic

N/A

VSS GROUND

for

logic

N/A

VEE

LCD GND

for LCD driving voltage

N/A

V1 V2

LCD output

used as select voltage level

V3 V4

LCD output

Used as non select voltage level for Part I

V5 V6

LCD output

Used as non select voltage level for Part II

S[1]-S[20]

segment

LCD driver output for part 1

SHL1

direction

direction control for part 1 segments

DL1, DR1

data in /out

If SHL1 = 1 then DL1=out, DR1=in
If SHL1 = 0 then DL1=in, DR1=out

I/O

S[21]-S[40]

segment

LCD driver output for part 2

SHL2

direction

direction control for part 2 segments

DL2, DR2

data in/out

If SHL2 = 1 then DL2=out, DR2=in
If SHL2 = 0 then DL2=in, DR2=out

I/O

alternation

Alternate the LCD driving waveform

CL1

latch clock

latch the data after shift is completed

CL2

shift clock

shift the data into the segments

FCS

mode selection

mode select signal for Part II

ST7065C

V1.4a

2001/08/29

8/13

Functional Description:

Shift Registers and Data I/O

The

ST7065C

supplies two sets of shift register, which controls the shift direction by

SHL1 & SHL2. The DL1, DR1, DL2 and DR2 are data input or output option

function.

Shift Direction of Channel 1

SHL1 Shift

Direction DL1 DR1

0 S[1]

$ S[20]

OUT

1 S[20]

$ S[1]

OUT

Clock and Mode Selection

In channel 1 part, the CL1 is the clock to latch data on the falling edge. It latches the

data input from the bi-directional shift register at the falling edge of CL1 and transfers

its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling

edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit

of the register to the latch circuit.

In channel 2 part, the CL1 and CL2 is the clock to latch or shift data on the falling or

rising edge which is depend on FCS value. When FCS is low, the channel 2 function

is the same as channel 1 as a segment driver. When FCS is high, the channel 2

function will become a common driver. Detail functions are show in the following

table:

FCS

Clock Eage

Channel 1

Channel 2

Latch data

Latch Data

CL1

---- ----

Shift data

CL2

---- ----

Latch

data ----

CL1

----

Shift

data

Shift

data ----

CL2

----

Latch

data

Shift Direction of Channel 2

SHL2 Shift

Direction DL2 DR2

0 S[21]

$ S[40]

OUT

1 S[40]

$ S[21]

OUT

ST7065C

V1.4a

2001/08/29

9/13

LCD Output Waveform

The output levels of channel1 and channel2 are decided by the combination of FCS,

M, and latched data. Refer to the following table:

FCS

Latched Data

Channel 1

Channel 2

1 V1 V2

0 V2 V1

1 V3 V6

0 V4 V5

1 V1 V1

0 V2 V2

1 V3 V5

0 V4 V6

Note:

To use the same function of channel 1 and channel 2 as a segment driver, V3 and V5, V4 and V6

need to short respectively.

Output of LATCH

DATA

Channel1 Output

(S[1] ~ S[20])

V1 V1

FCS

Channel2 Output
(S[21] ~ S[40])

ST7065C

V1.4a

2001/08/29

10/13

Channel 1 used as a segment driver and channel 2 as a common driver (FCS=1)

When channel 2 is used as a common driver, FCS is connected to VDD. Channel 2
will shift data on the rising edge of CL1 and latch data on the rising edge of CL2.

Both Channels 1 and 2 used as segment drivers (FCS=0)
When both channels 1 and 2 of the

ST7065C

are used as segment drivers, they will

shift data on the falling edge of CL2 and latch data on the falling edge of CL1.
V3&V5, V4&V6 are shorted in the application circuit as shown in the following
figure.

LCD

Controller

CL1

CL2

DL1
CL1

CL2

V1
V2
V3
V4

V1 V2 V3 V4 V5 V6

S[1] � S[40]

ST7065C

FCS

SHL1

SHL2

VSS

To LCD Segment

DR1

DL2

DR2

LCD

Controller

CL1

CL2

FLM

DL1
CL1

CL2

DL2

V1
V2
V3
V4
V5

V1 V2 V3 V4 V5 V6

S[1] � S[20]

S[21] � S[40]

ST7065C

FCS

SHL1

SHL2

VDD

VSS

To LCD Segment

To LCD Common

ST7065C

V1.4a

2001/08/29

11/13

Both Channels 1 and 2 used as common drivers (FCS=0)

When both channels 1 and 2 of the

ST7065C

are used as common drivers, the FCS is

set low and the signals (CL1, CL2, M) from the controller are connected as shown in
the following figure.

Timing Characteristics

CL2

Data in

(DL1, DL2)
(DR1, DR2)

Data out

(DL1, DL2)
(DR1, DR2)

CL1

WCKH

WCKL

WCKH

LCD

Controller

FLM

CL1

CL2

DL1
CL1

CL2

V1
V2

V1 V2 V3 V4 V5 V6

S[1] � S[40]

ST7065C

FCS

SHL1

SHL2

VSS

To LCD Common

DR1

DL2

DR2

ST7065C

V1.4a

2001/08/29

12/13

D.C Characteristics:

Symbol

Parameter

Test Condition Min. Typ. Max. Unit Applicable pin

VDD Operating

Voltage

2.7 - 5.5

VLCD

Driver Supply Voltage

VDD-VEE

VIH

Input High Voltage

0.7

VDD

- VDD

VIL

Input Low Voltage

0.3

VDD

ILKG

Input Leakage Current

VIN = 0 ~ VDD

-5

CL1,CL2,M,SHL1,S

HL2

DL1,DL2,DR1,DR2

VOH

Output High Voltage

IOH = -0.4mA

VDD

-0.4

- -

VOL

Output Low Voltage

IOL = +0.4mA

0.4

DL1,DL2,DR1,DR2

V1~V6, S[1]~S[40]

IDD

Operating Current

FCL2 = 400KHZ

100

300

VDD,VEE

Leakage Current

VIN = VDD ~ VEE

-10

V1 ~ V6

A.C Characteristics:

Symbol Parameter

Test

Condition

Min. Max. Unit Applicable pin

FCL

Data Shift Frequency

400

KHZ

CL2

TWCKH

Clock High Level Width

800

CL1,CL2

TWCKL

Clock Low Level Width

800

CL2

TSL

Clock Set-up Time

CL2 $ CL1

500

CL1,CL2

TLS

Clock Set-up Time

CL1 $ CL2

500

CL1,CL2

TR/TF

Clock Rise/Fall Time

200

CL1,CL2

TSU

Data Set-up Time

300

DL1,DL2,DR1,DR2

TDH

Data Hold Time

300

DL1,DL2,DR1,DR2

Data Delay Time

CL = 15 PF

500

DL1,DL2,DR1,DR2

Maximum Absolute Ratings:

Symbol Parameters Min.

Max.

Unit

VDD Supply

Voltage -0.3

TOPR Operating

Temperature -20 75

TSTG Storage

Temperature -55 125

ST7065C

V1.4a

2001/08/29

13/13

Application Circuit: (2Line x 24Word)

ST7066U

ST7065C

Dot Matrix LCD Panel

-V or GND

Vcc(+5V)

Regsister

DB0-DB7

To MPU

CL1

CL2

GND

VCC

Seg 1-40

Com 1-16

VEE

VSS

SHL2

SHL1

FCS

VDD

DL1

VEE

VSS

SHL2

SHL1

FCS

VDD

DL1

CL2

CL1

DR1

DL2

DR2

CL2

CL1

DR1

DL2

DR2

Seg 1-40

Note:

Regsister=2.2K~10K ohm

VR=10K~30Kohm

Электронный компонент: ST7065C