Sitronix

ST7093

26 COM / 80 SEG LCD CONTROLLER/DRIVER

Ver 2.1

2003/09/23

FEATURES

CGROM :10240 bits(256chars 5 x 8 dots)
CGRAM :320 bits(8 chars 5 x 8 dots)
DDRAM :64 bytes(16 x 4 )
ICONRAM :80 bits

Low power operation support:
-- 2.4 to 3.6V

Wide range of LCD driver power
-- 3.0 to 7.0V

4-bit or 8-bit MPU interface for both 68 and 80
series

4 pin clock synchronized serial interface

COM/SEG bi-directional setting

Voltage converter/regulator/follower/bias circuit
built in

26 common x 80 segment liquid crystal display
driver

32 steps electronic volume control

Wide range of instruction functions:
return home, display on/off, cursor on/off, display
character blink, double height, line shift, function
set, power and bias control

Hardware reset pin available

Internal oscillator or external clock

Power save mode for low power consumption

Bare Chip available

GENERAL DESCRIPTION

The ST7093 dot-matrix liquid crystal display

controller can drive LSI displays alphanumeric,
Japanese kana characters, and symbols. It can be
configured to drive a dot-matrix liquid crystal display
under the control of a 4bit, 8 bit or 4 pin clock
synchronized serial bus interface. For 4 bit and 8 bit
bus interface both 68 series and 80 series type are
available. Since all the functions such as display RAM,
character generator, liquid crystal driver, oscillator and
voltage control functions required for driving a
dot-matrix liquid crystal display are internally provided

on one chip, a minimal system can be interfaced with
this controller/driver.

The ST7093 character generator ROM is

extended to generate 256 5 x 8 dot character fonts.
The low power supply (2.4V to 3.6V) of the ST7093 is
suitable for any portable battery-driven product
requiring low power dissipation.

The ST7093 LCD driver consists of 26 common

signal drivers and 80 segment signal drivers with COG
gold bump available.

ST7093

Ver 2.1

2003/09/23

RESETB

Reset

Circuit

Instruction

Decoder

Address
Counter

Data

(DR)

MPU

interface

CSB

RW_WR

E_RD

DB4 to DB7

DB0 to DB3

Input/

Output

Buffer

Display data

RAM

(DDRAM)

64X8bits

Character

generator

RAM

320 bits

(CGRAM)

ICON RAM

80 bits

Character

generator

ROM

10,240 bits

(CGROM)

Cursor blink

control

Parallel/Serial Converter

Timing

Generator

CPG

80-bit shift

DIRS

25-bit

shift

registe

Common

Signal
Driver

80-bit

latch

circuit

Segment

Signal
Driver

LCD Drive

Voltage

Selector

SEG1 to
SEG80

COMI1
COMI2

COM1 to
COM24

VDD

GND

V0 V1 V2 V3 V4 VR

Bias Circuit

Vout Vext REF

Voltage regulator

CAP1+ CAP1- CAP2+ CAP2-

Voltage booster

LCD Power Circuit

ST7093

Ver 2.1

2003/09/23

Table 2. PAD Center Coordinates

NO.

PAD

NAME

X Y

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
RS
VSS
RW
VDD
E
CSB
D7
D6
D5
D4
D3
D2
D1
D0
VDD
VDD
VDD
VSS
VSS
VSS
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
V0
V0
VR
VR
VOUT
VOUT
CAP2N
CAP2N
CAP2P
CAP2P
CAP1N
CAP1N
CAP1P
CAP1P
VEXT
VSS
VSS
VSS
VR
DUMMY
REF
DIRS
VDD
VDD
VDD

-3249
-3159
-3069
-2979
-2889
-2799
-2709
-2619
-2529
-2439
-2349
-2259
-2169
-2079
-1989
-1899
-1809
-1719
-1629
-1539
-1449
-1359
-1269

-1179

-1089

-999
-909
-819
-729
-639
-549
-459
-369
-279
-189

-99

-9

171
261
351
441
531
621

711

801
891
981

1071

1161

1251
1341
1431
1521

1611

1701
1791
1881
1971
2061

-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821

NO.

PAD

NAME

X Y

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

CK
VSS
PSB
VDD
IF
VSS
MI
VDD
RESETB
TEST3
TEST2
TEST1
TEST0
COMI1
COM[1]
COM[2]
COM[3]
COM[4]
COM[5]
COM[6]
COM[7]
COM[8]
COM[17]
COM[18]
COM[19]
COM[20]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]

2151

2241
2331
2421

2511

2601
2691
2781
2871
2961
3051
3141
3231
3272
3272
3272
3272
3272
3272
3272
3272
3272
3272
3272
3272
3272
2868
2796
2724
2652
2580
2508
2436
2364
2292
2220
2148
2076
2004

1932

1860
1788
1716
1644
1572
1500
1428
1356
1284
1212

1140

1068

996
924
852
780
708
636
564
492

-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-821
-454
-364
-274
-184

-94

-4

176
266
356
446
536
626

811
811
811
811
811
811
811
811
811
811
811
811
811

811

811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811

811

NO.

PAD

NAME

X Y

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179

SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
COMI2
COM[24]
COM[23]
COM[22]
COM[21]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]

420

348
276
204
132

-12
-84

-156
-228
-300
-372
-444
-516
-588
-660
-732
-804
-876
-948

-1020
-1092

-1164

-1236
-1308
-1380
-1452
-1524
-1596
-1668
-1740
-1812
-1884
-1956
-2028
-2100
-2172
-2244
-2316
-2388
-2460
-2532
-2604
-2676
-2748
-2820
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272
-3272

811

811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811
811

626
536
446
356
266
176

-4

-94

-184
-274
-364
-454

ST7093

Ver 2.1

2003/09/23

NAME I/O Interfaced

FUNCTION

RS I MPU

Select registers.
0: Instruction register (for write)
address counter (for read)
1: Data register (for write and read)

RW_WR I

MPU

Select read or write.
In 68 mode In 80 mode
0: Write 0: Write
1: Read 1: Not active

E_RD I MPU

Starts data read/write.
In 68 mode In 80 mode
0: Not active 0: Read
1: Enable 1: Not active

DB4 to DB7

I/O

MPU

Four high order bi-directional tristate data bus
pins. Used for data transfer and receive
between the MPU and the ST7093. In serial interface mode
DB7 is SI (input data), DB6 is SCL (serial clock).

DB0 to DB3

I/O

MPU

Four low order bi-directional tristate data bus
pins. Used for data transfer and receive
between the MPU and the ST7093.
These pins are not used during 4-bit operation. (Fixed high)

CSB

MPU

Chip select signal. Active low.

RESETB

MPU

Reset signal. Active low.

CK I MPU

External clock input pin. it must be fixed to "Vss" , when the
internal oscillator circuit is used. In case of the external clock
mode, CK is used as the clock and OS bit should be turn off.

MI I MPU

Interface selection
0: 80 mode interface
1: 68 mode interface

DIRS I MPU

SEG direction selection
0: SEG1 SEG80
1: SEG80 SEG1

IF I MPU

Interface selection valid when PS=1
0: 4 bit bus mode
1: 8 bit bus mode

PS I MPU

Interface selection
0: serial mode
1: 4bit/ 8bit bus mode

COM1 to

COM24

COMI1,COMI2

LCD

Common signals. COMI1 and COMI2 are the same signal

SEG1 to SEG80

LCD

Segment signals

CAP1+, CAP1-
CAP2+, CAP2-

Capacitor connection pins for voltage booster

Vout

I/O

Voltage booster output pin

Voltage adjust pin between V0 and VSS

REF I MPU

Reference voltage selection pin
0: internal regulator is selected
1: external reference voltage input to Vext

Vext

I/O

External reference voltage input

V0 to V4

Power supply

Power supply for LCD drive
V

- Vss = 7 V (Max)

VDD

, GND

Power supply

VDD

: 2.4V to 3.6V, GND: 0V

Test 0 to Test3

Test pin. open

Note: 1. V0>=V1>=V2>=V3>=V4>=VSS must be maintained

ST7093

Ver 2.1

2003/09/23

System Interface

This chip has all two kinds of parallel interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is
selected by IF pin.
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading
from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next
DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is
transferred into DDRAM/CGRAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read
instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode and serial mode.

Table 1. Various kinds of operations according to RS and R/W bits for 68 interface.
RS RW_WR Operation
L

Instruction Write operation (MPU writes Instruction code
into IR)

Read address counter (DB0 ~ DB6)

Data Write operation (MPU writes data into DR)

Data Read operation (MPU reads data from DR)

Table 1.1. Various kinds of operations according to RS and R/W bits for 80 interface.
RS RW_WR

E_RD Operation

L H

Instruction Write operation (MPU writes Instruction
code into IR)

H L

Read address counter (DB0 ~ DB6)

L H

Data Write operation (MPU writes data into DR)

H L Data Read operation (MPU reads data from DR)

Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.

DB0-DB7

RW_WR

E_RD

Dummy

read

Instr

Circuit

ite

RAM
read

Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68 Series MPU Mode)

ST7093

Ver 2.1

2003/09/23

Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 64
x 8 bits, or 64 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid
crystal display.

The DDRAM address (A

) is set in the address counter (AC) as hexadecimal.

DDRAM address and corresponding display position

There is 4 line display data stored in DDRAM but only 2 lines are shown at a time. (2 line mode)
Hidden lines can be displayed by issuing line shift instruction.

Figure 1 DDRAM Address

Figure 2 2-Line Mode by 16-Character Display Example

Figure 3 3-Line Mode by 16-Character Display Example

AC AC AC AC AC AC AC

High

Order

bits

Low Order

bits

Example: DDRAM Address 37H

COM1~8

COM9~16

Display

Position

Hidden

32 33

09 0A 0B 0C 0D 0E 0F

13 14

19 1A 1B 1C 1D 1E 1F

29 2A 2B 2C 2D 2E

39 3A 3B

3C 3D

COM1~8

COM9~16

Display

Position

COM17~24

Hidden

09 0A 0B 0C 0D 0E 0F

13 14

19 1A 1B 1C 1D 1E 1F

29 2A 2B 2C 2D 2E

32 33

39 3A 3B

3C 3D

ST7093

Ver 2.1

2003/09/23

Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
256 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM.

Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character
patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.

Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as

DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated
separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no
undesirable interference, such as flickering, in areas other than the display area.

LCD Driver Circuit
LCD Driver circuit has 26 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is
transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 26 bit common register, segment data also output through segment driver from 80 bit segment latch.

Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.

Applicable Panel Size

Font

Display

Duty

Contents of outputs

2 Line X 16 Char

1/17

2x16 characters + 80icons

5X8

3 Line x 16 Char

1/25

3x16 characters + 80icons

ST7093

Ver 2.1

2003/09/23

Table 5

Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data)

Notes:

1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8

line CGRAM address

(b2,b1,b0) = (1,1,1) is the cursor line. Should the cursor position is displayed with CGRAM character the 8

line

output data will become (1,1,1,1,1).
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
"-": Indicates no effect.

Character Code

(DDRAM Data)

CGRAM

Address

Character Patterns

(CGRAM Data)

b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0

1 1 1

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0 0 -

0 0 0

0 0 0 0

0 0 1

1 1 1 0

0 0 1

0 0 0 1

0 0 1

0 0 0 1

0 0 1

1 1 1 0

0 0 1

0 1 0 0

0 0 1

1 0

0 0 1

0 0 0 1

0 0 0 0 -

0 0 1

0 0 0 0

ST7093

Ver 2.1

2003/09/23

Relationship between ICONRAM address and display pattern

When ICONRAM data is filled the corresponding position displayed is described as the following table.

ICONRAM bits

ICONRAM address

D2 D1 D0

00H

- - - S1

01H

- - - S6

S10

02H

- - -

S11 S12 S13

S14

S15

: : : : : : : :

0DH

- - -

S66 S67 S68

S69

S70

0EH

- - -

S71 S72 S73

S74

S75

0FH

- - -

S76 S77 S78

S79

S80

Notes : S1~S80 corresponds to display position of SEG1 ~ SEG80.

Segment data shift direction corresponding to DIRS pin setting

Segment data shift direction can be altered by setting values to the DIRS pin described as the following
table.

DIRS

Segment data shift direction

Low S1

S2 S3 S4 S5 ............... S78 S79 S80

High S80

S79 S78 S77 S76 ............... S3 S2 S1

Common data shift direction corresponding to S

Common data shift direction can be altered by setting the S value through function set instruction. The directions

corresponding to S value is described as the following table.

Common data shift direction

Low COM1

COM2 COM3 ........... COM15 COM24 COMI1(COMI2)

High COMI1(COMI2)

COM24 COM15 .......... COM3 COM2 COM1

ST7093

Ver 2.1

2003/09/23

Instructions

There are four categories of instructions that:

Designate ST7093 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others

Instruction Table:

Instruction Code

Instruction

RS RW

Description

Execution

Time

Return

Home

0 0 0 0 0

0 0 0 1

Set DDRAM address to "00H" from AC and return cursor to its

original position if shifted. The contents of DDRAM are not

changed.

80us

Double

height Mode

Set

0 0 0 0 0

0 1 0

DH2 DH1

Set double height mode

(DH2, DH1) = (0,0) : normal (default)

(0,1) :1)2-line mode

COM1..COM16 is a double height

COM17..COM24 is no use

2) 3-line mode

COM1..COM16 is a double height

COM17..COM24 is normal

(1,0) : 1) 2-line mode normal display

2) 3-line mode

COM1..COM8 is normal

COM9..COM24 is a double height l

(1,1) : normal

80us

Display

control

0 0 0 0 1

0 1 C B

C=0 : cursor off(default) C=1: cursor on

B=0 : blink off (default) B=1: blink on

D=0 : display off(default) D=1: display on

80us

Power save

control

0 0 0 0 0

0 1 1 OS PS

OS=0 : OSC off(default) OS=1 : OSC on

PS=0 : save off(default) PS=1 : save on

80us

Function

Set

0 0 0 0 0

1 0 N S

(Display line mode)

N=0 : 2 line display(default)

N=1 : 3 line display

(Shifting direction of COM)

S=0 : 1) 2-line mode COM1 COM16(default)

2) 3-line mode COM1 COM24(default)

S=1 : 1) 2-line mode COM16 COM1

2) 3-line mode COM24 COM1

(Select CGRAM or CGROM)

CG=0 : CGROM(default) CG=1 : CGRAM

80us

ST7093

Ver 2.1

2003/09/23

Instruction Code

Instruction

RS RW

Description

Execution

Time

Line shift

mode

0 0 0 0 0

1 1 0

LS2 LS1

(LS2,LS1) = (0,0) : DDRAM line 1 on top

(0,1) : DDRAM line 2 on top

(1,0) : DDRAM line 3 on top

(1,1) : DDRAM line 4 on top

80us

Bias

control

0 0 0 0 0

1 1 1 x

BS=0 : 1/5 bias(default) BS=1 : 1/4 bias

80us

Power

control

0 0 0 0 1

0 0 VC

VR VF

VC=0 : voltage booster off(default)

=1 : voltage booster on

VR=0 : voltage regulator off(default)

=1 : voltage regulator on

VF =0 : voltage follower off(default)

=1 : voltage follower on

80us

ICONRAM

address

0 0 0 1 0

Set ICONRAM address in address counter

EV addr : 10H

80us

CGRAM/

DDRAM

address

0 0 1

Set CGRAM/DDRAM address

DDRAM : 00H ~ 3FH

CGRAM : 40H ~ 7FH

80us

Write data

to RAM

1 0 D7 D6 D5 D4 D3 D2 D1 D0

Write data into internal RAM

(DDRAM/CGRAM)

80us

Read data

from RAM

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read data from internal RAM

(DDRAM/CGRAM)

80us

Note:
1. "x" Don't care
2. Make sure to use enough delay time(100us) between instruction

ST7093

Ver 2.1

2003/09/23

INSTRUCTION DESCRIPTION

Return

Home

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to the left edge on first line of display.

Double height mode

Set double height mode

DH2 DH1

Action

Low

Low Normal display (default)

Low High

1) 2-line mode

COM1..COM16 is a double height

COM17..COM24 is no use

2) 3-line mode

COM1..COM16 is a double height

COM17..COM24 is normal

High Low

1) 2-line mode normal display

2) 3-line mode

COM1..COM8 is normal

COM9..COM24 is a double height

High High

Normal

display

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DB0

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DH2 DH

DB0

ST7093

Ver 2.1

2003/09/23

Bias

Control

Bias control instruction will set the internal bias level generator
BS = "Low" (default) : 1/5 bias
= "High" : 1/4 bias

Display control

Control display/cursor/blink ON/OFF 1 bit register.
C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display.

The cursor data performs exclusive OR with any display data on the cursor line.

B : Cursor Blink ON/OFF control bit

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DB0

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DB0

2 line mode normal display (DH2,DH1=0,0)

2 line mode COM1 ..16 is a double height line (DH2,DH1=0,1)

ST7093

Ver 2.1

2003/09/23

When B = "High", C="High" then performs alternate between reverse display character and display

character at the cursor position. If C="Low" then display is normal regardless of B.

When B = "Low", blink is off.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

Function

set

(Display line mode)

N : Number of display lines

="Low" (default) : 2 lines COM1~COM16 are displayed

="High" : 3 lines COM1~COM24 are displayed

(Shifting direction of COM)

S : Common data shift direction
="Low" (default) : 1) 2-line mode COM1 COM16(default)

2) 3-line mode COM1 COM24(default)

="High" : 1) 2-line mode COM16 COM1

2) 3-line mode COM24 COM1

(Select CGRAM or CGROM)

CG: CGRAM enable bit
="Low" (default) : CGRAM is disabled, CGROM data pattern will appear on the display instead.

="High" : CGRAM enabled.

Power save set

OS : Oscillator on/off bit

When OS = "High", internal oscillator is enabled.

When OS = "Low" (default), internal oscillator is disabled

PS : Power save mode

When PS = "Low" (default) Power save mode is disabled.

When PS = "High" , Power save mode is enabled.

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DB0

Code

DB7 DB6 DB5 DB4

DB1

DB2

DB3

OS PS

DB0

ST7093

Ver 2.1

2003/09/23

Set ICONRAM Address

Set ICONRAM address to AC.

Before writing or reading data, set ICONRAM address should be performed. After each write or

read the address counter will increase 1 automatically. 5 bit ICON is stored in each data byte. If

(C,B) = (1,1) then ICON display will blink. ICONRAM address is from 00H to 0FH. Address

10H is reserved for electronic volume level setting.

Set CGRAM/DDRAM Address

Set CGRAM /DDRAM address to AC.

CGRAM and DDRAM share the same address space. Before accessing CGRAM/DDRAM, set

CGRAM/DDRAM address should be performed. Address counter will automatically increase by

1 after each write or read operation. After accessing 7FH the address will reset to 00H.

Addr

0 1 2 3 4 5 6 7 8 9 A

C D E F

00H

DDRAM LINE 1 (00H~0FH)

10H

DDRAM LINE 2 (10H~1FH)

20H

DDRAM LINE 3 (20H~2FH)

30H

DDRAM LINE 4 (30H~3FH)

40H CGRAM

(pattern

CGRAM

(pattern1)

50H

CGRAM (pattern 2)

CGRAM (pattern 3)

60H CGRAM

(pattern

CGRAM

(pattern5)

70H

CGRAM (pattern 6)

CGRAM (pattern 7)

Read Data from CGRAM/DDRAM or ICONRAM

Before RAM data read, address set of either CGRAM/DDRAM or ICONRAM should be performed. The first
read is a dummy read. The data is invalid. The correct data is obtain from the second read. After read data the
address counter will increase by 1 automatically. If multiple read in succession only the first read data is
dummy.

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

DB0

ST7093

Ver 2.1

2003/09/23

Line shift mode

Set Line Shift mode

Reset Function

Initializing by Internal Reset Circuit

External reset can be achieved by pulling low RESETB pin.

1. Function set:

S = 0; COM left shift

CG = 0; CGRAM disable

2. Display on/off control:

D = 0; Display off

C = 0; Cursor off

B = 0; Blinking off

3. Power control & bias

BS = 0 ; 1/5 bias

OS = 0 ; oscillator off

PS = 0 ; power save off

VC = 0; voltage booster off

VR = 0; voltage regulator off

VF = 0; voltage follower off

4. Line shift mode

(LS2,LS1) = (0,0) ; DDRAM line 1 shown at the first line of LCD display

5. Electronic contrast control register

(E4,E3,E2,E1,E0) = (0,0,0,0,0)

RESETB pulse width

Trw

10us

RESET start time

Tres

50ns

LS2 LS1

Action

Low

Low DDRAM Line1 shows at the first line of LCD (default)

Low

High DDRAM Line2 shows at the first line of LCD

High

Low DDRAM Line3 shows at the first line of LCD

High

High DDRAM Line4 shows at the first line of LCD

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

LS2 LS

DB0

ST7093

Ver 2.1

2003/09/23

Interfacing to the MPU

The ST7093 can send data in either two 4-bit operations or one 8-bit operation, or 4 pin clock synchronous serial

interface is used.

For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are

disabled. The data transfer between the ST7093 and the MPU is completed after the 4-bit data has been

transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)

are transferred before the four low order bits (for 8-bit operation, DB0 to DB3).

For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

For serial interface, by setting PS = "Low" DB7 become SI (serial in data), DB6 become SCL (serial clock).

Each bit of data transfer is at the rising edge of SCL. At the rising edge of 8

SCL the data is converted into 8

bit parallel data and RS bit is read in to select whether write data or write instruction. Read operation is not

supported.

Supply Voltage for LCD Drive

There are different voltages that supply to ST7093's pin (V0 � V4) to obtain LCD drive waveform. The relations of

the bias, duty factor and supply voltages are shown as below:

Duty Factor 1/17

Bias

Supply Voltage

1/4 1/5

V0 V

LCD

V1 3/4

LCD

4/5

LCD

V2 1/2V

LCD

3/5

LCD

V3 1/2V

LCD

2/5

LCD

V4 1/4

LCD

1/5

LCD

Timing Diagram of Serial Mode Data Transfer (serial Mode)

CSB

SCL

D7 D6 ...........D0

D7 D6 ....... D0

100us

ST7093

Ver 2.1

2003/09/23

Voltage booster

The voltage booster use internal generates reference voltage 1.8V to boost 4 times to produce Vout as 7.2V.

out

1.8v

v

Voltage regulator

The voltage regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained
By adjusting resistors Ra and Rb as shown in equation (1) or (2) ,and by setting Electronic Contrast Control data
Bits, see this equation (3) or (4).

The potential of V0 Pin can be adjusted within Vout � Vref, Vref is the internal constant voltage source of the
Chip and this value is 2.0V in the condition vdd 2.4V

The REF selects which voltage is used for voltage regulator between the ecternal VEXT and internal Vref.

Voltage regulation by adjusting resistors Ra,

When REF is "Low"
V0 = ( 1 + Rb / Ra ) x Vref........(1)

When REF is "High"
V0 = ( 1 + Rb / Ra ) x VEXT .....(2)

Reference set value
Ra = 1M Rb = 1.5M

1.8V X 4
=7.2V

Vdd

Cap1+

Cap1-

Cap2+

Cap2-

Vout

REF

Vout

VEXT

Vss

Vref

Inside Chip

GND

Voltage regulator circuit

ST7093

Ver 2.1

2003/09/23

Electronic contrast control (32 steps)

Electronic contrast control data bits is 10H = (C4, C3, C2, C1, C0 ), Voltage regulation is adjusted as 32-contrast
step According to the value of Electronic contrast control data bits. LCD drive voltage V0 has one of 32 voltage
values if 5-bit data is set to the electronic contrast control register (ICONRAM address 10H). When using the
electronic contrast control function, you need to turn the voltage regulators on using power control instruction.

When REF is "Low"

V0 = ( 1 + Rb / Ra ) x Ven ..... (3)
Ven = Vref - n
( n = 0, 1, 2, ..... 30, 31 )
= Vref / 150

When REF is "High"
V0 = ( 1 + Rb / Ra ) x Ven ..... (4)
Ven = Vext - n
( n = 0, 1, 2, ..... 30, 31 )
= Vext / 150

No. C7 C6 C5 C4 C3 C2 C1 C0

Contrast

- - - 0 0 0 0 0

0 (default)

Maximum

High

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

.
.
.

.
.

.
.
.

- - - 1 1 1 1 0

- - - 1 1 1 1 1

Minimum

Low

Electronic contrast control register ("-" don't care)

REF

Vout

VEXT

Vss

Vref

Inside Chip

GND

Ven

Electronic contrast control circuit

ST7093

Ver 2.1

2003/09/23

Absolute Maximum Ratings

Characteristics Symbol

Value

Power Supply Voltage

-0.3V to +7.0V

LCD Driver Voltage

LCD

-0.3V to +10.0V

Input Voltage

-0.3V to V

+0.3V

Operating Temperature

-40

C to + 85

Storage Temperature

STO

-55

C to + 125

DC CHARACTERISTICS ( T

= 25

C , VDD =2.4V � 3.6V )

Symbol Characteristics

Condition

Min.

Typ.

Max. Unit

Operating

Voltage

2.4 - 3.6 V

LCD

Voltage

- V

3.0

7.0

Power

Supply

Current

OSC

= 160KHz, V

=3.0V

checker pattern
no CPU access

- 90

115 uA

IH1

Input

High

Voltage

(Except OSC1)

- 0.7V

- V

IL1

Input

Low

Voltage

(Except OSC1)

- 0.3

0.6

IH2

Input

High

Voltage

(OSC1)

- V

� 1 - V

IL2

Input Low Voltage

(OSC1)

- -

1.0

OH1

Output High Voltage

(DB0 - DB7)

= -0.1mA

0.8V

- V

OL1

Output

Low

Voltage

(DB0 - DB7)

= 0.1mA

0.4

OH2

Output High Voltage

(Except DB0 - DB7)

= -0.04mA

0.8V

- V

OL2

Output

Low

Voltage

(Except DB0 - DB7)

= 0.04mA

0.2 V

COM

Common

Resistance V

LCD

= 4V, I

= 0.05mA

SEG

Segment

Resistance V

LCD

= 4V, I

= 0.05mA

LEAK

Input

Leakage

Current

= 0V to V

-1

�A

ST7093

Ver 2.1

2003/09/23

68 INTERFACE READ/WRITE TIMING(T

= 25

C, VDD =3.6V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

100

Address Hold Time Pins: RS,RW,CSB

DSW

Data Setup Time Pins: DB0 - DB7

150

ITE MO

Data Hold Time

Pins: DB0 - DB7

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

360

Address Hold Time Pins: RS,RW,CSB

DDR

DB output ready Time Pins: DB0 - DB7

300

EAD MODE

DB output Hold Time Pins: DB0 - DB7

68 INTERFACE READ/WRITE TIMING (T

= 25

C, VDD = 2.7V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

500

Address Hold Time Pins: RS,RW,CSB

DSW

Data Setup Time Pins: DB0 - DB7

300

WRI

TE MO

Data Hold Time

Pins: DB0 - DB7

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

580

Address Hold Time Pins: RS,RW,CSB

DDR

DB output ready Time Pins: DB0 - DB7

340

READ MO

DB output Hold Time Pins: DB0 - DB7

ST7093

Ver 2.1

2003/09/23

80 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 3.6V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

Address

Hold

Time

Pins:

RS,RW,CSB

200 - -

DSW

Data Setup Time Pins: DB0 - DB7

180

ITE MO

Data Hold Time

Pins: DB0 - DB7

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

360

Address

Hold

Time

Pins:

RS,RW,CSB

20 - -

DDR

DB output ready Time Pins: DB0 - DB7

300

READ

DB output Hold Time Pins: DB0 - DB7

80 INTERFACE READ/WRITE TIMING (T

= 25

C, VDD = 2.7V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

Address

Hold

Time

Pins:

RS,RW,CSB

380 - -

DSW

Data Setup Time Pins: DB0 - DB7

280

I
T

Data Hold Time

Pins: DB0 - DB7

Enable Cycle Time Pin E

100

Enable Pulse Width Pin E

300

Enable Rise/Fall

Time

Pin E

Address Setup Time Pins: RS,RW,CSB

440

Address

Hold

Time

Pins:

RS,RW,CSB

40 - -

DDR

DB output ready Time Pins: DB0 - DB7

340

EAD MODE

DB output Hold Time Pins: DB0 - DB7

ST7093

Ver 2.1

2003/09/23

Writing data from MPU TO ST7093 by Serial mode interface

SERIAL INTERFACE WRITE TIMING (T

= 25

C, VDD = 3.6V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin SCL

3.0

Enable Pulse Width Pin SCL

1.5

Enable Rise/Fall

Time

Pin SCL

SU1

CSB Setup Time Pin CSB

CSB

Hold

Time

CSB

100 us

SU2

Rs Data Setup Time Pin RS

Rs Data Hold Time Pin RS

SU3

SI Data Setup Time Pin SI

WRIT

E MO

SI Data Hold Time Pin SI

SERIAL INTERFACE WRITE TIMING (T

= 25

C, VDD = 2.7V)

Symbol Characteristics Test

Condition

Min. Typ. Max. Unit

Enable Cycle Time Pin SCL

5.0

Enable Pulse Width Pin SCL

2.5

Enable Rise/Fall

Time

Pin SCL

SU1

CSB Setup Time Pin CSB

CSB

Hold

Time

CSB

100 us

SU2

Rs Data Setup Time Pin RS

Rs Data Hold Time Pin RS

SU3

SI Data Setup Time Pin SI

WRI

E M

SI Data Hold Time Pin SI

tH1

CSB

tSU1

SCL

tSU2

tH2

tSU3

tH3

ST7093

Ver 2.1

2003/09/23

ST7093 Specification Revision History

Version Date

Description

0.1A

2000/06/12 1. 17com*60segment (Original)

0.2A 2000/10/01

26com*80segment

0.3 2001/01/08

1. Changed DC characteristics VLCD=V0-VSS
2. CGROM standard font 0B&C0A
3. Modify 3-Line mode double height instruction
4. Modify AC characteristics

0.3B 2001/03/12

1. Modify Booster 2.4Vx4 1.8Vx4 (page 27)
2. 2line17duty,3line25duty (Page 10)
3. COG Align Key Coordinate (page 4)
4.Reference Ra,Rb value (page 27,29)
5. Modify pin description CK , D0..D3 , TEST pin

0.4

2001/04/17 1. Modify AC characteristics

0.4b

2002/02/07 1. Add COB Pad Dimensions

1.0 2002/05/23

1. Modify double height mode instruction ( P16 & P18 )
2. Add illustration of electronic contrast control circuit ( P30 )
3. Add illustration of voltage regulator circuit ( P29 )
4. Add illustration of MPU interface ( P32 & P33 )

2.0

2002/08/29 1. Modify Operating Voltage 2.4V .. 3.6V

2.0b 2002/09/05

1. Modify CK pin must fixed "Vss"
2. CGROM standard font 0C

2.1

2003/09/23 1. Modify product number to ST7093

Электронный компонент: ST7093