Sitronix

ST8616

PRELIMINARY

168 Segment Driver for STN LCD with Low-Voltage Drive

Notice: This is not a final specification. Some parameters are subject to change

Ver 0.03

1/25

2001/Dec/13

168/160 output mode

LCD drive voltage: 2.6 to 5.5 V

168 LCD drive circuits

Operating voltage: 2.5 to 5.5 V

Shift clock speed

20 MHz max / 3 V

30 MHz max / 5 V

4/8 bits data bus

Display-off function

Automatic generation of the chip enable signal

Standby function

The ST8616 is a 168-channel segment driver that drives a

dot matrix LCD panel at low voltage. The ST8616 can

operate with a 5V LCD drive voltage and a 3V logic drive

voltage, and it can be used together with the common

driver ST8600 and ST8601. The ST8616, packaged in a

fine-pitch slim tape-carrier package (slim-TCP), makes it

possible to reduce the space round the LCD panel.

Sitronix ST8616

Ver 0.03

2/25

2001/Dec/13

(

)

SHL

CL2

CL1

GND1

Top view

Y165

Y166

Y167

Y168

187

186

185

183

184

181

182

179

180

177

178

176

175

174

173

172

171

170

169

165

166

167

168

Figure 1 ST8616 TCP pin assignment

GND2

188

DISP

EIO

194

193

192

191

189

MODE

190

Sitronix ST8616

Ver 0.03

3/25

2001/Dec/13

LCD Drive Circuit

Level Shifter

21 Bit Shift register

latch circuit (1)

(8 Bits)

latch circuit (1)

(8 Bits)

data shifter and

arithmetic circuit

CL2

8 bits

SHL

D0~D7

Y1~Y168

CL1

DISP

EIO1

EIO2

VMR

V1R

V0R

VML

V0L

V1L

Latch circuit (2)

MODE

LCD Drive Circuit

The 168-bit LCD drive circuit selects three voltage levels

, V

and V

to drive the LCD panel. One of these three

levels is output to the corresponding Y pin, depending on

the data in latch circuit (2) and the DISP signal.

Data Shifter and Arithmetic Circuit

The data shifter shifts the destinations of data output when

necessary. The arithmetic circuit performs operations for

the data and AC signal M.

Sitronix ST8616

Ver 0.03

4/25

2001/Dec/13

Latch Circuit (2)

A 168-bit latch circuit (2) latches data which input from

latch circuit (1), and outputs the latched data to the level

shifter, at the falling edge of each clock 1 (CL1) pulse.

Latch Circuit (1)

The latch circuit (1) latches 4/8-bit parallel data which input

from D

to D

pins, and outputs the latched data to latch

circuit (2).

Shift Register

The 21-bit shift register generates and outputs data latch

signals for latch circuit (1) at the falling edge of each clock

2 (CL2) pulse.

Level Shifter

Converts logic signals to LCD drive signals.

Sitronix ST8616

Ver 0.03

5/25

2001/Dec/13

PIN NO.

SYMBOL

I/O

DESCRIPTION

1~168 Y1~Y168

Either level V

or V

is output according to the combination of the M signal and

display data when the DISP pin is set at V

. See figure 4

193,170

194,169

192,171

, V

LCD drive-level voltage. See figure 3

191

172,188

GND1, GND2

Logic power supply

175 CL1

I Display data latch signal. The LCD drive signal corresponding to the display data is

output at the falling edge of this signal.

176

CL2

I Display data latch signal. Display data is latched at the falling edge of this signal.

174

I Changes the LCD drive outputs to AC.

184~177 D

When the display data is 1 (V

level), the LCD drive output level is the selection

level and the liquid-crystal display is on, and when it is 0 (GND level), they are

non-selection level and off, respectively.

187 SHL

A control signal to switch the data output destination. See the section on Switching

the Data Output Destination.

186,173 EIO1 , EIO2 I/O

If SHL is at the GND level, EIO1 inputs the chip enable signal and EIO2
outputs the chip enable signal; and if it is at the V

level, the opposite occurs.

Enable input: The chip enable-input pin of the first ST8616 must be fixed to the GND

level, and the other chip-enable input pins must be connected to the chip

enable-output pins of the previous ST8616.

Enable output: The chip enable-output pin must be connected to the chip

enable-input pin of the next ST8616.

185

DISP

I When DISP is GND level, it sets LCD drive outputs (Y1 to Y168) to the V

level.

189

4/8 bit data selection. Connect to V

when use 8-bit data mode, connect to ground

when use 4 bit data mode (capture data from D

, D

connect to ground)

190

MODE

160/168 outputs mode selection. Connect to V

when use 168 outputs mode,

connect to ground when use 160 outputs mode.

P: power pin

Figure 4 Selection of LCD Drive Output Level

Output level

Sitronix ST8616

Ver 0.03

6/25

2001/Dec/13

Switching the Data Output Destination

The order for the output of captured data is inverted crosswise according to the SHL signal. At this time, the input/output

pin of the enable signal can be switched. See figure 5-1 , figure 5-2.

Y168

Y167

Y165

Y166

Y164

Y163

Y161

Y162

SHL = GND , BS=GND , MODE=V

Enable input : EIO1

Enable output : EIO2

Enable input : EIO2

Enable output : EIO1

Figure 5-1 Data Output Destination ( 168-output mode

)

first data

last data

Y168

Y167

Y165

Y166

Y164

Y163

Y161

Y162

last data

first data

SHL = GND , BS = V

, MODE=V

Enable input : EIO1

Enable output : EIO2

Y168

Y167

Y165

Y166

Y164

Y163

Y161

Y162

last data

first data

Enable input : EIO2

Enable output : EIO1

Y168

Y167

Y165

Y166

Y164

Y163

Y161

Y162

last data

first data

SHL = V

, BS = GND , MODE=V

SHL = V

, BS=V

, MODE=V

Sitronix ST8616

Ver 0.03

7/25

2001/Dec/13

Y160

Y159

Y157

Y158

Y156

Y155

Y153

Y154

SHL=GND , BS=GND , MODE=GND

SHL = V

, BS=GND , MODE=GND

Enable input : EIO1

Enable output : EIO2

Enable input : EIO2

Enable output : EIO1

Figure 5-2 Data Output Destination ( 160-output mode )

first data

last data

Y160

Y159

Y157

Y158

Y156

Y155

Y153

Y154

last data

first data

SHL=GND , BS = V

, MODE=GND

Enable input : EIO1

Enable output : EIO2

Y160

Y159

Y157

Y158

Y156

Y155

Y153

Y154

last data

first data

SHL = V

, BS = V

, MODE=GND

Enable input : EIO2

Enable output : EIO1

Y160

Y159

Y157

Y158

Y156

Y155

Y153

Y154

last data

first data

Sitronix ST8616

Ver 0.03

8/25

2001/Dec/13

Operation Timing
4-bit data mode, BS=GND ,SHL=GND ,MODE=GND
During the data standby state when the data latch
operation enable signal ( EIO1 , when SHL=GND) is low,
the next data latch clock (CL2) cancels the standby state.
The 4-bit data is latch at the falling edge of CL2. When it
has latched 156 bits of data, it sets the EIO2 signal to
low. When it has latched 160 bits of data, it automatically
stops and enters the standby state, initiating the next
ST8616, provided its EIO2 pin is connected to the

EIO1 pin of the next ST8616.

Figure 6-1 shows the 4-bit data-latch timing
When SHL = GND, the EIO1 pin is a chip-enable input

and the EIO2 pin is a chip-enable output, data d1 is
output to Y1 and d160 is output to Y160. When SHL =
V

; the EIO1 pin is a chip-enable output and the

EIO2 pin is a chip-enable input, d1 is output to Y160 and

d160 is output to Y1.

Line

CL2

CL1

EIO2

(1)

EIO2

(2)

Y1 to Y320

ST8616 (2) latch data

ST8616 (1) latch data

Figure 6-1 4 bit data Latch Timing (1 line, 320 dots)

d160

d157

d156

d153

Sitronix ST8616

Ver 0.03

9/25

2001/Dec/13

4-bit data mode, BS=GND ,SHL=GND ,MODE=V

During the data standby state when the data latch
operation enable signal ( EIO1 , when SHL=GND) is low,
the next data latch clock (CL2) cancels the standby state.
The 4-bit data is latch at the falling edge of CL2. When it
has latched 164 bits of data, it sets the EIO2 signal to
low. When it has latched 168 bits of data, it automatically
stops and enters the standby state, initiating the next
ST8616, provided its EIO2 pin is connected to the

EIO1 pin of the next ST8616.

Figure 6-1 shows the 4-bit data-latch timing
When SHL = GND, the EIO1 pin is a chip-enable input

and the EIO2 pin is a chip-enable output, data d1 is
output to Y1 and d168 is output to Y168. When SHL =
V

; the EIO1 pin is a chip-enable output and the

EIO2 pin is a chip-enable input, d1 is output to Y168 and

d168 is output to Y1.

Line

CL2

CL1

EIO2

(1)

EIO2

(2)

Y1 to Y336

ST8616 (2) latch data

ST8616 (1) latch data

Figure 6-2 4 bit data Latch Timing (1 line, 336 dots)

d168

d165

d164

d161

Sitronix ST8616

Ver 0.03

12/25

2001/Dec/13

COM1

COM2

COM3

COM162

SEG1

COM161

COM160

SEG2

SEG3

SEG320

SEG319

SEG318

LCD PANEL

320X162 DOT MATRIX

X1~X162

ST8601

X1~X160

ST8616

EIO

MODE0, MODE1

M/S, AMP

MWS0~4

RESET

GND

SHL

VEO

LL,R

HL,R

ML,R

DISPOFF

DOC

DIO

CL , CCL

CL1
CL2
DISP
M
D0~D3

GND, BS, MODE
D

, SHL

VDD

0L,R

1L,R

ML,R

CL1
CL2
DISP
M
D0~D3

GND, BS, MODE
D

, SHL

VDD

0L,R

1L,R

ML,R

DISP

FLM

CL1

CL2

Controller

VLCD

Power Supply

Circuit

Sitronix ST8616

Ver 0.03

13/25

2001/Dec/13

Item Symbol

Ratings

Unit

Notes

Power supply Logic circuit

-0.3 to +7.0

2 and 5

LCD drive circuit

-0.3 to +7.0

2 and 5

Input voltage (1)

-0.3

+ 0.3

2 and 3

Input voltage (2)

-0.3

+ 0.3

2, 4, and 5

Operating temperature

OPR

-30

+75

�

Storage temperature

STG

-55

+110

�

Notes: 1. If the LSI is used beyond the above maximum

ratings, it may be permanently damaged. It

should always be used within its specified

operating range for normal operation to

prevent malfunctions or degraded reliability.

2. The reference point is GND (0 V)

3. Applies to the SHL, EIO1 , EIO2 ,

DISP , D

to D

, CL1, CL2, M, and BS

pins.

4. Applies to the V

, V

, and V

pins.

5. As shown in figure 14, users should conform

to the following turn-on/off sequence for the

power and signals. Otherwise, the LSI will

malfunction or will be permanently damaged.

In addition, the LSI reliability will be affected.

Figure 14 Turn on and Turn off timing

Input signal

clock data

Signal undefined

period

initilization period

(at least one frame)

2.7V

DISP

Sitronix ST8616

Ver 0.03

14/25

2001/Dec/13

5.1 Turning on the power

1) Turn on the power in the order of GND - V

GND-V

and V

. Then, ground the DISP

pin.

2) The LCD forcibly outputs the V

level by the

display-off function.

3) The display-off function has priority even if an

input signal is disturbed immediately after V

applied.

4) Input the specific signal to initialize the registers

in the driver. The initialization period must be at
least one frame.

5) After the preparation for the normal display is

completed. Apply the V

level to the DISP

pin to cancel the display-off function. At this time,
the level of pins V

, V

, and V

must rise to the

specific potential.

5.2 Turning off the power

The procedure is basically the reverse of that used to

turn on the power.

1) Ground

the DISP pin.

2) Turn off the LCD power in the order of V

and GND-V

3) Set

and input signals to GND.

At this time, the level of pins V

, V

, and V

must be 0V. Since the display-off function stops
when V

falls to 0V, the LCD may output a

level other than V

. Therefore, a display failure

may occur when the power is turned off or on.

Sitronix ST8616

Ver 0.03

15/25

2001/Dec/13

9.1 DC Characteristics 1 (V

= 2.7 to 4.5 V, V

-GND =3.5 to 5.5 V, and Ta = -30 to +75 �C)

Item. Symbol Applicable

Pin Min.

Typ.

Max.

Unit

Conditions

Notes

Input high-level

voltage

0.7V

Input low level

voltage

CL1, CL2, SHL, M,

EIO1 , EIO2 , DISP

to D

, MODE, and BS

0 -

0.3V

Output high- level

voltage

-0.4 -

V I

= -0.4 mA

Output low-level

voltage

EIO1 and EIO2

- -

0.4

= 0.4 mA

Y1 to Y168, V

and V

0.5

Y1 to Y168, V

and V

- 0.7 3.0 k

Vi-Yj on resistance R

Y1 to Y168, V1L and V1R

0.8

2.0

= 200 uA

Input leakage

current (1)

IL1

CL1, CL2, SHL, MODE,

EIO1 , EIO2 DISP ,

, M and BS

-5.0 - 5.0 uA

=-GND

Input leakage

current (2)

IL2

, V

and V

-25

uA V

= V

-GND

Current

consumption (1)

200

Current

consumption (2)

and V

100

500

Current

consumption (3)

100

=3.0V

=4.5V

CL2

=20MHz

CL1

= 33.3 kHz

= 2.78 kHz 2, 3

Sitronix ST8616

Ver 0.03

16/25

2001/Dec/13

9.2

DC Characteristics 2(V

= 4.5 to 5.5 V, V

-GND = 2.6 to 5.5 V and Ta = -30 to +75 �C)

Item. Symbol

Applicable

Pin Min.

Typ.

Max.

Unit

Conditions

Notes

Input high-level

voltage

0.7V

- V

Input low level

voltage

CL1, CL2, SHL, M,

EIO1 , EIO2 , DISP

D0 to D7, MODE, and BS

0 -

0.3V

Output high- level

voltage

-0.4 -

- V

= -0.4 mA

Output low-level

voltage

EIO1 and EIO2

- -

0.4

= 0.4 mA

Y1 to Y168, V

and V

0.5

2.0

Y1 to Y168, V

and V

- 0.7 3.0 k

Vi-Yj on resistance R

Y1 to Y168, V

and V

- 0.8 2.0

= 200 uA

Input leakage

current (1)

IL1

CL1, CL2, SHL, M,

EIO1 , EIO2 , DISP

to D

, MODE, and BS

-5.0 - 5.0

= V

-GND

Input leakage

current (2)

IL2

, V

and V

-25

uA V

= V

-GND

Current

consumption (1)

0.6

Current

consumption (2)

and V

0.3

1.0

Current

consumption (3)

0.2

=5.0V

= 4.5V

CL2

=30MHz

CL1

= 50 kHz

= 4.2 kHz

2, 3

Notes: 1. The resistance is between the LCD drive output

pins(Y1~Y168) and the voltage supply pins for

LCD panel (V0, VM, V1), when load current is

applied to one of the LCD drive output pins;

defined under the following conditions:

- GND = 5.5V

= (V0+V1) / 2

= GND + 1

should be near the GND level, and the V

should be near the middle voltage between V

and

. V

should be within the range of

V = 0.25 V

which is the range within which R

, the LCD

drive circuits output impedance, is stable. See

figure 15.

2. Input and output currents are excluded. When a

CMOS input is left floating, excess current flows

from the power supply through the input circuit. To

avoid this, V

and V

must be used at V

and

GND, respectively.

3. Standby current.

4. The voltage of each signal is shown in figure 16.

Sitronix ST8616

Ver 0.03

18/25

2001/Dec/13

9.3

AC Characteristics 1 (V

=2.7V, V

-GND=3.5 to 5.5V, f

CL2

=15MHz, and Ta=-30 to +75

�

Item Symbol

Applicable

Pins

Min

Max.

Unit

Clock cycle time

CYC

CL2

Clock high-level width (1)

CWH2

CL2

Clock low-level width (1)

CWL2

CL2

Clock high-level width (2)

CWH1

CL1

Clock setup time

SCL

CL1 and CL2

Clock hold time

HCL

CL1 and CL2

Clock rise time

CL1 and CL2

Clock fall time

CL1 and CL2

Data setup time

to D

and CL2

Data hold time

to D

and CL2

M setup time

M and CL1

M hold time

M and CL1

Output delay time (1)

PD1

CL1 and Y1 to Y168

500

Note: 1. The load must be less than 10 pF between the EIO1 and EIO2 connections of the ST8616

Sitronix ST8616

Ver 0.03

19/25

2001/Dec/13

9.4

AC Characteristics 2 (V

=5.0V, V0-GND=2.7 to 5.5V, f

CL2

=30MHz, and Ta=-30 to +75

�

Item Symbol

Applicable

Pins

Min

Max.

Unit

Clock cycle time

CYC

CL2

27 - ns

Clock high-level width (1)

CWH2

CL2

Clock low-level width (1)

CWL2

CL2

Clock high-level width (2)

CWH1

CL1

Clock setup time

SCL

CL1 and CL2

Clock hold time

HCL

CL1 and CL2

Clock rise time

CL1 and CL2

Clock fall time

CL1 and CL2

Data setup time

to D

and CL2

Data hold time

to D

and CL2

M setup time

M and CL1

M hold time

M and CL1

Output delay time 1

CL1 and Y1 to Y168

500

Note: 1. The load must be less than 10 pF between the EIO1 and EIO2 connections of the ST8616

2. For output delay time 1 , connect the load circuit as shown in figure 17.

Test point

10pF

Figure 17 Load Circuit for Output Delay Time 1

Sitronix ST8616

Ver 0.03

21/25

2001/Dec/13

1 2

4142

212

Substrate Connect to Ground

DUMMY

GND

MODE

SHL

EIO

DOFFB

CL2

CL1

EIO

GND

DUMMY

Y168

Y167

Y166

Y165

Y164

DUMMY

Y2 Y3

(0,0)

ST8616

Chip Size = 9670 um X 930 um

Unit: um

PAD NO.

NAME

PAD NO.

NAME

1 DUMMY -4653.6

-219.85

27 DI

1410.4

-219.85

2 DUMMY -4532.3

-219.85

28 CL2 1710.4

-219.85

3 V

-4281.8

-219.85

29 CL1 2010.4

-219.85

4 V

-4195.6

-219.85

30 M 2310.4

-219.85

5 V

-3892

-219.85

31 EIO

2670.35

-219.85

6 V

-3805.8

-219.85

32 GND 2980.7

-219.85

7 V

-3521.8

-219.85

33 GND 3066.9

-219.85

8 V

-3435.6

-219.85

34 GND 3153.1

-219.85

9 GND -3216.6

-219.85

35 V

3451

-219.85

10 GND -3130.4

-219.85

36 V

3537.2

-219.85

11 GND -3044.2

-219.85

37 V

3821.2

-219.85

12 V

-2839.35

-219.85

38 V

3907.4

-219.85

13 V

-2753.15

-219.85

39 V

4211

-219.85

14 V

-2666.95

-219.85

40 V

4297.2

-219.85

15 MODE

-2399.65

-219.85

41 DUMMY 4524.85

-219.85

16 BS

-2099.65

-219.85

42 DUMMY 4646.15

-219.85

17 SHL

-1799.65

-219.85

43 DUMMY 4767.5

337.4

18 EIO

-1499.65

-219.85

44 Y168 4677.3

337.4

19 DOFFB

-1199.65

-219.85

45 Y167 4621.3

337.4

20 DI

-899.65

-219.85

46 Y166 4565.3

337.4

21 DI

-414.35

-219.85

47 Y165 4509.3

337.4

22 DI

-114.35

-219.85

48 Y164 4453.3

337.4

23 DI

185.65

-219.85

49 Y163 4397.3

337.4

24 DI

499.65

-219.85

50 Y162 4341.3

337.4

25 DI

800.05

-219.85

51 Y161 4285.3

337.4

26 DI

1110.4

-219.85

52 Y160 4229.3

337.4

Sitronix ST8616

Ver 0.03

22/25

2001/Dec/13

PAD NO.

NAME

PAD NO.

NAME

53 Y159 4173.3

337.4

91 Y121 2045.3

337.4

54 Y158 4117.3

337.4

92 Y120 1989.3

337.4

55 Y157 4061.3

337.4

93 Y119 1933.3

337.4

56 Y156 4005.3

337.4

94 Y118 1877.3

337.4

57 Y155 3949.3

337.4

95 Y117 1821.3

337.4

58 Y154 3893.3

337.4

96 Y116 1765.3

337.4

59 Y153 3837.3

337.4

97 Y115 1709.3

337.4

60 Y152 3781.3

337.4

98 Y114 1653.3

337.4

61 Y151 3725.3

337.4

99 Y113 1597.3

337.4

62 Y150 3669.3

337.4

100 Y112 1541.3

337.4

63 Y149 3613.3

337.4

101 Y111 1485.3

337.4

64 Y148 3557.3

337.4

102 Y110 1429.3

337.4

65 Y147 3501.3

337.4

103 Y109 1373.3

337.4

66 Y146 3445.3

337.4

104 Y108 1317.3

337.4

67 Y145 3389.3

337.4

105 Y107 1261.3

337.4

68 Y144 3333.3

337.4

106 Y106 1205.3

337.4

69 Y143 3277.3

337.4

107 Y105 1149.3

337.4

70 Y142 3221.3

337.4

108 Y104 1093.3

337.4

71 Y141 3165.3

337.4

109 Y103 1037.3

337.4

72 Y140 3109.3

337.4

110 Y102 981.3

337.4

73 Y139 3053.3

337.4

111 Y101 925.3

337.4

74 Y138 2997.3

337.4

112 Y100 869.3

337.4

75 Y137 2941.3

337.4

113 Y99 813.3

337.4

76 Y136 2885.3

337.4

114 Y98 757.3

337.4

77 Y135 2829.3

337.4

115 Y97 701.3

337.4

78 Y134 2773.3

337.4

116 Y96 645.3

337.4

79 Y133 2717.3

337.4

117 Y95 589.3

337.4

80 Y132 2661.3

337.4

118 Y94 533.3

337.4

81 Y131 2605.3

337.4

119 Y93 477.3

337.4

82 Y130 2549.3

337.4

120 Y92 421.3

337.4

83 Y129 2493.3

337.4

121 Y91 365.3

337.4

84 Y128 2437.3

337.4

122 Y90 309.3

337.4

85 Y127 2381.3

337.4

123 Y89 253.3

337.4

86 Y126 2325.3

337.4

124 Y88 197.3

337.4

87 Y125 2269.3

337.4

125 Y87 141.3

337.4

88 Y124 2213.3

337.4

126 Y86

85.3

337.4

89 Y123 2157.3

337.4

127 Y85

30.3

337.4

90 Y122 2101.3

337.4

128 Y84

-26.7

337.4

Sitronix ST8616

Ver 0.03

23/25

2001/Dec/13

PAD NO.

NAME

PAD NO.

NAME

129 Y83

-82.7

337.4

167 Y45 -2210.7

337.4

130 Y82 -138.7

337.4

168 Y44 -2266.7

337.4

131 Y81 -194.7

337.4

169 Y43 -2322.7

337.4

132 Y80 -250.7

337.4

170 Y42 -2378.7

337.4

133 Y79 -306.7

337.4

171 Y41 -2434.7

337.4

134 Y78 -362.7

337.4

172 Y40 -2490.7

337.4

135 Y77 -418.7

337.4

173 Y39 -2546.7

337.4

136 Y76 -474.7

337.4

174 Y38 -2602.7

337.4

137 Y75 -530.7

337.4

175 Y37 -2658.7

337.4

138 Y74 -586.7

337.4

176 Y36 -2714.7

337.4

139 Y73 -642.7

337.4

177 Y35 -2770.7

337.4

140 Y72 -698.7

337.4

178 Y34 -2826.7

337.4

141 Y71 -754.7

337.4

179 Y33 -2882.7

337.4

142 Y70 -810.7

337.4

180 Y32 -2938.7

337.4

143 Y69 -866.7

337.4

181 Y31 -2994.7

337.4

144 Y68 -922.7

337.4

182 Y30 -3050.7

337.4

145 Y67 -978.7

337.4

183 Y29 -3106.7

337.4

146 Y66 -1034.7

337.4

184 Y28 -3162.7

337.4

147 Y65 -1090.7

337.4

185 Y27 -3218.7

337.4

148 Y64 -1146.7

337.4

186 Y26 -3274.7

337.4

149 Y63 -1202.7

337.4

187 Y25 -3330.7

337.4

150 Y62 -1258.7

337.4

188 Y24 -3386.7

337.4

151 Y61 -1314.7

337.4

189 Y23 -3442.7

337.4

152 Y60 -1370.7

337.4

190 Y22 -3498.7

337.4

153 Y59 -1426.7

337.4

191 Y21 -3554.7

337.4

154 Y58 -1482.7

337.4

192 Y20 -3610.7

337.4

155 Y57 -1538.7

337.4

193 Y19 -3666.7

337.4

156 Y56 -1594.7

337.4

194 Y18 -3722.7

337.4

157 Y55 -1650.7

337.4

195 Y17 -3778.7

337.4

158 Y54 -1706.7

337.4

196 Y16 -3834.7

337.4

159 Y53 -1762.7

337.4

197 Y15 -3890.7

337.4

160 Y52 -1818.7

337.4

198 Y14 -3946.7

337.4

161 Y51 -1874.7

337.4

199 Y13 -4002.7

337.4

162 Y50 -1930.7

337.4

200 Y12 -4058.7

337.4

163 Y49 -1986.7

337.4

201 Y11 -4114.7

337.4

164 Y48 -2042.7

337.4

202 Y10 -4170.7

337.4

165 Y47 -2098.7

337.4

203 Y9 -4226.7

337.4

166 Y46 -2154.7

337.4

204 Y8 -4282.7

337.4

Sitronix ST8616

Ver 0.03

24/25

2001/Dec/13

PAD NO

NAME

PAD NO.

NAME

205 Y7 -4338.7

337.4

209 Y3 -4562.7

337.4

206 Y6 -4394.7

337.4

210 Y2 -4618.7

337.4

207 Y5 -4450.7

337.4

211 Y1 -4674.7

337.4

208 Y4 -4506.7

337.4

212 DUMMY -4764.9 337.4

10.1 Gold Bump size (unit: um)

PAD

NO.

X Y

Area

(um

)

Output 44~211

3610

Input 3~40,

3480

Dummy 1,2,41,42,43,212

5270

Bump pad height = 18um, strength=18g

Электронный компонент: ST8616