ST
Sitronix
ST8624
PRELIMINARY
240 Segment Driver for STN LCD with Low-Voltage Drive
Notice: This is not a final specification. Some parameters are subject to change
Ver 0.12
1/28
2001/Sep/08
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Duty cycle up to 1/300
LCD drive voltage: 3.5 to 5.5 V
240 LCD drive circuits
Operating voltage: 2.7 to 5.5 V
8 bit data bus
Shift clock speed
25 MHz max/3 V
40 MHz max/5 V
Shadowing correction circuit
Display-off function
Automatic generation of the chip enable signal
Standby function
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The ST8624 is a 240-channel segment driver that drives a
dot matrix LCD panel at low voltage. The ST8624 operates
with a 5-V LCD drive voltage and a 3-V logic drive voltage,
and it can be used together with the common driver
ST8600. The ST8624 also incorporates a shadowing
correction circuit and is suitable for high-quality image
processing. The ST8624, packaged in a fine-pitch slim
tape-carrier package (slim-TCP), makes it possible to
reduce the space round the LCD panel.
Sitronix ST8624
Ver 0.12
2/28
2001/Sep/08
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VML
V0L
V1L
Vcc
SHL
EIO1
DISP
D1
D0
D3
D2
D5
D4
D7
D6
CL2
CL1
M
EIO2
CC1
CC2
CC3
CC4
GND
V1R
V0R
VMR
Top view
Y1
Y2
Y3
Y4
Y237
Y238
Y239
Y240
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241
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4
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240
Figure 1 ST8624 TCP pin assignment
Sitronix ST8624
Ver 0.12
3/28
2001/Sep/08
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LCD drive circuit
correction circuit
latch circuit (2)
Shift register
latch circuit (1)
latch circuit (1)
data shifter and
arithmetic circuit
EIO1
EIO2
CL2
SHL
D0~D7
Y1~Y240
V0L
VML
V1L
CC1~CC4
CL1
M
V0R
VMR
V1R
DISP
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LCD Drive Circuit
The 240-bit LCD drive circuit generates three voltage
levels V0, V1, and VM, which drive the LCD panel. One of
these three levels is output to the corresponding Y pin,
depending on the data in latch circuit (2), the correction
signals (CC1 to CC4), and the DISP signal.
Correction Circuit
This circuit corrects the shadowing volume.
(2.1) The circuit compares the cross talk correction signals
(CCI and CC2) from the external circuits and present
output, and determines whether the effective value is
increased due to cross talk. If the effective value is
increased, the output level is reset to the VM level.
(2.2) The circuit compares the present output data to the
next output data. If there are no data changes due to the
waveform distortion correction signals (CC3 and CC4), the
output level is reset to the VM level.
The reset period can be adjusted by using CC1 to CC4.
The correction needed depends on each output pin.
Sitronix ST8624
Ver 0.12
4/28
2001/Sep/08
Latch Circuit (2)
A 240-bit latch circuit (2) latches data input from latch
circuit (1), and outputs the latched data to the correction
circuit and the LCD drive circuit, at the falling edge of each
clock 1 (CL1) pulse.
Latch Circuit (1)
The 240-bit latch circuit (1) latches
8-bit
parallel data input
via the D0 to D7 pins, and outputs the latched data to latch
circuit 2, both according to the timing generated by the
shift register.
Shift Register
The 80-bit shift register generates and outputs data latch
signals for latch circuit (1) at the falling edge of each clock
2 (CL2) pulse.
Data Shifter and Arithmetic Circuit
The data shifter shifts the destinations of data output when
necessary. The arithmetic circuit performs operations for
the data and AC signal M.
Sitronix ST8624
Ver 0.12
5/28
2001/Sep/08
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PIN NO.
SYMBOL
I/O
DESCRIPTION
1~240 Y1~Y240
O
Either level V0 or V1 is output according to the combination of the M signal and
display data when the DISP pin is set at Vdd. See figure 4
266,242
267,241
265,243
V0L, V0R
VML, VMR
V1L, V1R
P
LCD drive-level voltage.
264, 244
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, GND
P Logic power supply
251
CL1
I Display data latch signal. The LCD drive signal corresponding to the display data is
output at the falling edge of this signal.
252
CL2
I Display data latch signal. Display data is latched at the falling edge of this signal.
250
M
I Changes the LCD drive outputs to AC.
260~253
D0~D7
I When the display data is 1 (Vdd level), the LCD drive output level is the selection
level and the liquid-crystal display is on, and when it is 0 (GND level), they are
non-selection level and off, respectively.
263
SHL
I A control signal to switch the data output destination. See the section on Switching
the Data Output Destination.
262,249
EIO1 , EIO2 I/O If SHL is at the GND level, EIO1 inputs the chip enable signal and EIO2
outputs the chip enable signal; and if it is at the Vdd level, the opposite occurs.
Enable input: The chip enable-input pin of the first ST8624 must be fixed to the GND
level, and the other chip-enable input pins must be connected to the chip
enable-output pins of the previous ST8624.
Enable output: The chip enable-output pin must be connected to the chip
enable-input pin of the next ST8624.
261
DISP
I A low DISP level sets LCD drive outputs Y1 to Y240 to the VM level.
248,247
CC1, CC2
I Rising/Falling cross talk correction signal. The V1/V0 output pin is reset to the VM
level when CC1/CC2 is high.
246,245
CC3, CC4
I Waveform distortion non-selected/selected (black/white) data correction signal. The
present output pin (non-selected/selected) and the next output pin (non-
selected/selected) are reset to the VM level when CC3/CC4 is high.
P: power pin
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