SLS System Logic Semiconductor
SL20T0081
81 COMMON x 132 SEGMENT STN LCD DRIVER / CONTROLLER
SL20T0081
SLS System Logic Semiconductor
SL20T0081
INTRODUCTION
The SL20T0081 is a single-chip graphic dot-matrix liquid crystal display driver & controller that can be connected
directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the
internal display data RAM and the chip generates a liquid crystal drive signal independent of the micro-processor. The
SL20T0081 contains 81x132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal
panel pixels and the internal RAM bits, and the device contains 81 common output circuits and 132 segment output
circuits, so that a single chip can drive a 81x132 dot display (capable of displaying 8 columns x 5 rows of a 16 x 16 dot
font). Moreover, the capacity of the display can be extended through the use of master/ slave structures between chips.
The chips are able to minimize power consumption because no external operating clock is necessary for the display
data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power liquid crystal
driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock RC oscillator circuit,
the SL20T0081 Series chips can be used to create the lowest power display system with the fewest
components for high performance portable systems.
Direct display of RAM data through the display data RAM.
RAM capacity
: 81x132 = 8580 bits
FEATURES
RAM bit data :
"1" Non-illuminated
"0" illuminated
(during normal display)
High-speed 8-bit MPU interface
The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs.
Serial interface available (supports write operation only).
Abundant command functions
Display data Read/Write,display ON/OFF, Normal/Reverse display mode, page address set, display start line set,
column address set, status read, display all point ON/OFF, LCD bias set, electronic volume, read/modify/write,
segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation
internal resistor ratio set.
Static drive circuit equipped internally for indicators
1 driver, with 4 kinds of flashing mode
Duty
LCD Driver Bias
Maximum display matrix
1/81
1/10 or 1/8
81 x 132
1/65
1/9 or 1/7
65 x 132
1/55
1/8 or 1/6
55 x 132
1/49
1/8 or 1/6
49 x 132
1/33
1/6 or 1/5
33 x 132
OVERVIEW
DEVICE SPECIFICATION
Table 1. Duty and Bias selection
SLS System Logic Semiconductor
SL20T0081
Built-in Power Supply Circuit
Low-power liquid crystal display power supply circuit equipped internally.
Booster circuit (with Boost ratios of x2 / x3 / x4 / x5, where the step-up voltage reference power supply can be input
externally).
High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/
o
C or external input).
LCD driver voltage regulator resistors and voltage followers equipped internally.
RC oscillator circuit equipped internally (external clock can also be selected).
Operating Voltage Range
Supply Voltage (VDD)
: 2.4V ~ 3.6V
LCD driver Voltage (VLCD) : 4.5V ~ 16.0V
Low Power Consumption
Operating power
: 40uA typical (conditions:V
DD
=3V, x 4 boosting (VCI = V
DD
), V0 =11V, Internal power
supply ON,display OFF and normal mode is selected )
Standby power
: 10uA maximum (during power save [standby] mode)
Operating Temperatures
Wide range of operating temperatures : -40 to 85
o
C
CMOS Process
Package Type
TCP
SLS System Logic Semiconductor
SL20T0081
VDD
VSS
V0
V1
V2
V3
V4
CAP1+
CAP1-
CAP2+
CAP2-
CAP3+
VOUT
VEXT
VR
IREF
IRE
HPMB
SEG Drivers
COM
Drivers
Power
Supply
Circuit
Display Data Memory
81 x 132 bits
Display Data Read Circuit
Column Address Decoder
Row Address Decoder
Timing Generation
&
Read/Write Circuit
COMS
Oscillation
Circuit
Command Decoder
MPU Interface
Status
CE1
CE2
RS
RD (E)
P68/86
PS
WR (R/W)
D7 (SI)
D6 (SCK)
D5
D4
D2
D1
D3
D0
CLS
MS
DISP
CL
SYNC
FRS
SEG0
SEG131
COM40
COM79
COMS
CAP4+
DUTY0
DUTY1
VCI
FR
RESET
COM
Drivers
COM0
COM39
DUTY2
BLOCKDIAGRAM
SLS System Logic Semiconductor
SL20T0081
(0,0)
282
147
104
103
1
325
283
146
Y
X
Figure 1. SL20T0081 PAD Layout
Item
Pad No.
Size
Unit
X
Y
8900
3000
-
Chip Size
Pad pitch
1-2, 102-103, 147-148, 281-282
131
2 to10, 94 to 102, 104 to 146,
148 to 281, 283 to 325
60
10-11, 93-94
90
11 to 41, 45-46, 50 to 93
80
41-42, 44-45, 46-47, 49-50
110
42 to 44, 47 to 49
120
m
Bumped PAD size
(Bottom)
2 to 10, 94 to 102, 148 to 281
37
92
104 to 146, 283 to 325
92
37
11 to 41, 45, 46, 50 to 93
57
92
42 to 44, 47 to 49
67
92
1, 103, 147, 282
72
97
All PAD
Bumped PAD height
18
Table 2. SL20T0081 PAD Dimensions
COG Align Key Coordination
ILB Align Key Coordination
Potting Mark Coordination
30m
30
m
30
m
30
m
30m 30m
30
m
60
m
30m 30m 30m
(-4230.0, -1415.0)
(4230.0, -1430.0)
upper left : (-4365.0, 1415.0)
(4346.0, 1406.0)
lower right : (4365.0, -1415.0)
60m
72m
PAD CONFIGURATION
PAD Layout
Figure 2. Align Key Coordination
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