SL34118
System Logic
Semiconductor
SLS
Voice Switched Speakerphone Circuit
The SL34118 Voice Switched Speakerphone Circuit incorporates
the necessary amplifiers, attenuators, level detectors, and control
algorithm to form the heart of a high quality hands-free speakerphone
system. Included are a microphone amplifier with adjustable gain and
MUTE control, Transmit and Receive attenuators which operate in a
complementary manner, level detectors at both input and output of
both attenuators, and background noise monitors for both the transmit
and receive channels. A Dial Tone Detector prevents the dial tone
from being attenuated by the Receive background noise monitor
circuit. Also included are two line driver amplifiers which can be used
to form a hybrid network in conjunction with an external coupling
transformer. A high pass filter can be used to filter out 60 Hz noise in
the reseive channel, or for other filtering functions. A Chip Disable pin
permits powering down the entire circuit to conserve power on long
loops where loop current is at a minimum.
The SL34118 may be operated from a power supply, or it can be
powered from the telephone line, requiring typically 5.0 mA. The
SL34118 can be interfaced directly to Tip and Ring (through a coupling
transformer) for stand-alone operation, or it can be used in
conjunction with a handset speech network and or other features of a
featurephone.
Improved Attenuator Gain Range: 52 dB Between Transmit and
Receive
Low Voltage Operation for Line-Powered Applications (3.0-6.5 V)
4 Point Signal Sensing for Improved Sensitivity
Background Noise Monitors for Both Transmit and Receive Paths
Microphone Amplifier Gain Set by External Resistors - Mute
Function Included
Chip Disable for Active Standby Operation
On Board Filter Pinned-Out for User Deined Function
Dial Tone Detector to Inhibit Receive Idle Mode During Dial Tone
Presence
ORDERING INFORMATION
SL34118N Plastic
SL34118D SOIC
T
A
= -25
to 70
C for all packages
PIN ASSIGNMENT
SL34118
System Logic
Semiconductor
SLS
SIMPLIFIED BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
INTRODUCTION
The fundamental difference between the operation
of a speakerphone and a handset is that of half-
duplex versus full-duplex. The handset is full duplex
since conversation can occur in both directions
(transmit and receive) simultaneousiy. A
speakerphone has higher gain levels in both paths,
and attempting to converse full duplex results in
oscillatory problems due to the loop that exists within
the system. The loop is formed by the receive and
transmit paths, the hybrid, and the acoustic coupling
(speaker to microphone). The only practical and
economical solution used to data is to design the
speakerphone to function in a half duplex mode - i.e.,
only one person speaks at a time, while the other
listens. To achieve this requires a circuit which can
detect who is talking, switch on the appropriate path
(transmit or receive), and switch off (attenuate) the
other path. In this way, the loop gain is maintained
less than unity. When the talkers exchange function,
the circuit must quickly detect this, and switch the
circuit appropriately.By providing speech level
detectors, the circuit operates in a "hand-free" mode,
eliminating the need for a "push-to-talk" switch.
The handset, by the way, has the same loop as
the speakerphone. But since the gains are
considerably lower, and since the acoustic coupling
from the earpiece to the mouthpiece is almost non-
existent (the receiver is normally held against a
person's ear), oscillations don't occur.
The SL34118 provides the necessary level
detectors, attenuators, and switching control for a
properly operating speakerphone. The detection
sensitivity and timing are externally controllable.
Additionally, the SL34118 provides background noise
monitors which make the circuit insensitive to room
and line noise, hybrid amplifiers for interfacing to Tip
and Ring, the microphone amplifier, and other
associated functions.
ATTENUATORS
The transmit and receive attenuators are
complementary in function, i.e., when one is at
maximum gain (+6.0 dB), the other is at maximum
attenuation (-46 dB), and vice versa. They are never
both fully on or both fully off. The sum of their gains
remains constant (within a nominal error band of
0.1 dB) at a typical value of -40 dB. Their purpose is
to control the transmit and receive paths to provide
the half-duplex operation required in a speakerphone.
The attenuators are non-inverting, and have a -
3.0 dB (from max gain) frequency of
100 KHz. The
input impedance of each attenuator (TXI and RXI) is
nominally 10 k
(see Figure 1), and the input signal
should be limited to 350 mVrms (990 mVp-p) to
prevent distortion. That maximum
SL34118
System Logic
Semiconductor
SLS
recommended input signal is independent of the
volume control setting. The diode clamp on the
inputs limits the input swing, and therefore the
maximum negative output swing. This is the reason
for V
RXOL
and V
TXOL
specification being defined as
they are in the Electrical Characteristics. The output
impedance is <10
until the output current limit
(typically 2.5 mA) is reached.
Figure 1. Attenuator Input Stage
The attenuators are controlled by the single
output of the Control Block, which is measurable at
the C
T
pin (Pin 14). When the C
T
pin is at
+240 millivolts with respect to V
B
, the circuit is in the
receive mode (receive attenuator is at +6.0 dB). When
the C
T
pin is at -240 millivolts with respect to V
B
, the
circuit is in the transmit mode (transmit attenuator is
at +6.0 dB). The circuit is in an idle mode when the C
T
voltage is equal to V
B
, causing the attenuators' gains
to be halfway between their fully on and fully off
positions (-20 dB each). Monitoring the C
T
voltage
(with respect to V
B
) is the most direct method of
monitoring the circuit's mode.
The inputs to the Control Block are seven: 2 from
the comp arators operated by the level detectors, 2
from the background noise monitors, the volume
control, the dial-tone detector, and the AGC circuit.
These seven inputs are described below.
LEVEL DETECTORS
There are four level detectors - two on the receive
side and two on the transmit side. Refer to Figure
2 - the terms in parentheses form one system, and the
other terms form the second system
Figure 2. Level Detectors
Each level detector is a high gain amplifier with
back-to-back diodes in the feedback path, resulting in
non-linear gain, which permits operation over a wide
dynamic range of speech levels. The sensitivity of
each level detector is determined by the external
resistor and capacitor at each input (TLI1, TLI2, RLI1,
and RLI2). Each output charges an external capacitor
through a diode and limiting resistor, thus providing a
dc representation of the input ac signal
level. The outputs have a guick rise time (determined
by the capacitor and an internal 350
resistor), and a
slow decay time set by an internal current source and
the capacitor. The capacitors on the four outputs
should have the same value (
10%) to prevent timing
problems.
Referring to Figure 8, on the receive side, one
level detector (RLI1) is at the receive input receiving
the same signal as at Tip and Ring, and
SL34118
System Logic
Semiconductor
SLS
the other (RLI2) is at the output of the speaker
amplifier. On the transmit side, one level detector
(TLI2) is at the output of the microphone amplifier,
while the other (TLI1) is at the hybrid output. Outputs
RLO1 and TLO1 feed a comparator, the output of
which goes to the Attenuator Control Block. Likewise,
outputs RLO2 and TLO2 feed a second comparator
which also goes to the Attenuator Control Block. The
truth table for the effects of the level detectors on the
Control Block is given in the section describing the
Control Block.
BACKGROUND NOISE MONITORS
The purpose of the background noise monitors is
to distinguish speech (which consists of bursts) from
background noise (a relatively constant signal level).
There are two background noise monitors - one for
the receive path and one for the transmit path.
Refering to Figure 2, the receive background noise
monitor is operated on by the RLI1-RLO1 level
detector, while the transmit background noise monitor
is operated on by the TLI2-TLO2 level detector. They
monitor the background noise by storing a dc voltage
representative of the respective noise levels in
capacitors at CPR and CPT. The voltages at these
pins have slow rise times (determined by the external
RC), but fast decay times. If the signal at RLI1 (or
TLI2) changes slowly, the voltage at CPR (or CPT)
will remain more positive than the voltage at the non-
inverting input of the monitor's output comparator.
When speech is present, the voltage on the
noninverting input of the comparator will rise quicker
than the voltage at the inverting input (due to the
burst characteristic of speech), causing its output to
change. This output is sensed by the Attenuator
Control Block.
The 36 mV offset at the comparator's input keeps
the comparator from changing state unless the
speech level exceeds the background noise by
4.0 dB. The time constant of the external RC
(
4.7 seconds) determines the response time to
background noise variations
VOLUME CONTROL
The volume control input at VLC (Pin 13) is
sensed as a voltage with respect to V
B
. The volume
control affects the attenuators only in the receive
mode. It has no effect in the idle or transmit modes.
When in the receive mode, the gain of the receive
attenuator will be +6.0 dB, and the gain of the transmit
attenuator will be -46 dB only when VLC is equal to
V
B
. As VLC is reduced below V
B
,
the gain of the receive attenuator is reduced, and the
gain of the transmit attenuator is increased such that
their sum remains constant. Changing the voltage at
VLC changes the voltage at C
T
(see the Attenuator
Control Block section), which in turn controls the
attenuators.
The volume control setting does not affect the
maximum attenuator input signal at which notice able
distortion occurs.
The bias current at VLC is typically 60 nA out of
the pin, and does not vary significantly with the VLC
voltage or with V
CC
.
DIAL TONE DETECTOR
The dial tone detector is a comparator with one
side connected to the receive input (RXI) and the
other input connected to V
B
with a 15 mV offset (see
Figure 3). If the circuit is in the receive mode, and the
incoming signal is greater than 15 mV (10 mVrms), the
comparator's output will change, disabling the
receive idle mode. Tthe receive attenuator will then be
at a setting determined solely by the volume control.
The purpose of this circuit is to prevent the dial
tone (which would be considered as continuous
noise) from fading away as the circuit would have the
tendency to swich to the idle mode. By disabling the
receive idle mode, the dial tone remains at the
normally expected full level.
Figure 3. Dial Tone Detector
AGS
The AGS circuit affects the circuit only in the
receive mode, and only when the supply voltage (V
CC
)
is less than 3.5 volts. As V
CC
falls below 3.5 volts, the
gain of the receive attenuator is reduced. The transmit
path attenuation changes such that the sum of the
transmit and receive gains remains constant.
The purpose of this feature is to reduce the power
(and current) used by the speaker when a line-
powered speakerphone is connected to a long line,
where the available power is limited. By reducing the
speaker power, the voltage sag at V
CC
is controlled,
preventing possible erratic operation.
SL34118
System Logic
Semiconductor
SLS
ATTENUATOR CONTROL BLOCK
The Attenuator Control Block has the seven
inputs described above:
- Tthe output of the comparator operated by RLO2
and TLO2 (microphone/speaker side) - designated
C1.
- The output of the comparator operated by RLO1
and TLO1 (Tip/Ring) side) - designated C2.
- The output of the transmit background noise
monitor - designated C3.
- The output of the receive background noise
monitor - designated C4.
- The volume control.
- The dial tone detector.
- The AGC circuit.
The single output of the Control Block controls
the two attenuators. The effect of C1-C4 is as follows:
Inputs
Output
C1
C2
C3
C4
Mode
Tx
Tx
1
X
Transmit
Tx
Rx
Y
Y
Fast Idle
Rx
Tx
Y
Y
Fast Idle
Rx
Rx
X
1
Receive
Tx
Tx
0
X
Slow Idle
Tx
Rx
0
0
Slow Idle
Rx
Tx
0
0
Slow Idle
Rx
Rx
X
0
Slow Idle
X = Don't Care; Y = C3 and C4 are not both 0
A definition of the above terms:
1) "Transmit" means the transmit attenuator is
fully on (+6.0 dB), and the receive attenuator is
at max. attenuation (-46 dB).
2) "Receive" means both attenuators are
controlled by the volume control. At max.
volume, the receive attenuator is fully on
(6.0 dB), and the transmit attenuator is at max.
attenuation (-46 dB).
3) "Fast Idle" means both transmit and receive
speech are present in approximately equal levels.
The attenuators are quickly switched (30 ms) to
idle until one speech level dominates the other.
4) "Slow Idle" means speech has ceassed in both
transmit and receive path. The attenuators are
then slowly switched (1 second) to the idle
mode.
5) Switching to the full transmit or receive modes
from any other mode is at the fast rate (30 ms).
A summary of the truth table is as follows:
1) The circuit will switch to transmit if: a) both
transmit level detectors sense higher signal levels
relative to the respective receive level detectors (TLI1
versus RLI1, TLI2 versus RLI2), and b) the transmit
background noise monitor indicates the presence of
speech.
2) The circuit will switch to receive if: a) both
receive level detectors sense higher signal levels
relative to the respective transmit level detectors, and
b) the receive background noise monitor indicates the
presence of speech.
3) The circuit will switch to the fast idle mode if the
level detectors disagree on the relative strengths of
the signal levels, and at least one of the background
noise monitors indicates speech. For example,
refferring to the Expanded Logic Diagram (Figure 8), if
there is sufficient signal at the microphone amp
output (TLI2) to override the speaker signal (RLI2),
and there is sufficient signal at the receive input
(RLI1) to override the signal at the hybrid output
(TLI1), and either or both background monitors
indicate speech, then the circuit will be in the fast idle
mode. Two conditions which can cause the fast idle
mode to occur are a) when both talkers are attempting
to gain control of the system by talking at the same
time, and b) when one talker is in a very noisy
environment, forcing the other talker to continually
override that noise level. In general, the fast idle mode
will occur infrequently.
4) The circuit will switch to the slow idle mode
when a) both talkers are quiet (no speech present), or
b) when one talker's speech level is continuously
overriden by noise at the other speaker's location.
The time required to switch the circuit between
transmit, receive, fast idle and slow idle is determined
in part by the components at the C
T
pin (Pin 14). A
schematic of the C
T
circuitry is shown in Figure 4 and
operates as follows:
- R
T
is typically 120 k
, and C
T
typically 5.0
F.
- To switch to the receive mode, I
1
is turned on (I
2
is
off), charging the external capacitor to +240 mV
above V
B
. (An internal clamp prevents further
charging of the capacitor.)
- To switch to the transmit mode, I
2
is turned on (I
1
is off) bringing down the voltage on the capacitor
to -240 mV with respect to V
B
.
- To switch to idle quickly (fast idle), the current
sources are turned off, and the internal 2.0 k
resistor is switched in, discharging the capacitor
to V
B
with a time constant = 2.0 K
x C
T
.
- To switch to idle slowly (slow idle), the current
sources are turned off, the switch at the 2.0 k
resistor is open, and the capacitor discharges to
V
B
through the external resistor R
T
with a time
constant = R
T
x C
T
.
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