SL4020B
System Logic
Semiconductor
SLS
14 Stage Ripple-Carry Binary Counter/Divider
High-Voltage Silicon-Gate CMOS
The SL4020B is ripple-carry binary counter. All counter stages are
master-slave flip-flops. The state of a counter advances one count on
the negative transition of each input pulse; a high level on the RESET
line resets the counter to its all zeros state. Schmitt trigger action on the
input-pulse line permits unlimited rise and fall times.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
A at 18 V over full package-
temperature range; 100 nA at 18 V and 25
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4020BN Plastic
SL4020BD SOIC
T
A
= -55
to 125
C for all packages
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
Clock
Reset
Output state
L
No change
L
Advance to
next state
X
H
All Outputs
are low
X=don't care
SL4020B
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
10
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
P
D
Power Dissipation per Output Transistor
100
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
3.0
18
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL4020B
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
-55
C
25
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=GND or V
CC
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=GND or V
CC
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
I
IN
Maximum Input
Leakage Current
V
IN
= GND or V
CC
18
0.1
0.1
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
= GND or V
CC
5.0
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
A
I
OL
Minimum Output Low
(Sink) Current
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
I
OH
Minimum Output High
(Source) Current
V
IN
= GND or V
CC
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
SL4020B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200k
, Input t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
f
max
Maximum Clock Frequency(Figure 1)
5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q1
(Figure 1)
5.0
10
15
360
160
130
360
160
130
720
320
260
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Q
n
to Q
n
+1 (Figure
3)
5.0
10
15
330
80
60
330
80
60
660
160
120
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figure 2)
5.0
10
15
280
120
100
280
120
100
560
240
200
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
C
IN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200k
, Input t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
t
w
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
140
60
40
140
60
40
280
120
80
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
5.0
10
15
200
80
60
200
80
60
400
160
120
ns
t
rem
Minimum Removal Time, Reset(Figure 2)
5.0
10
15
350
150
100
350
150
100
700
300
200
ns
t
r,
t
f
Maximum Input Rise and Fall Times, Clock
(Figure 1)
5.0
10
15
Unlimited
s
SL4020B
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
SL4020B
System Logic
Semiconductor
SLS
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
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