SL74HC192
System Logic
Semiconductor
SLS
Presettable BCD/Decade UP/DOWN Counter
High-Performance Silicon-Gate CMOS
The SL74HC192 is identical in pinout to the LS/ALS192. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset inputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TC
D
) and Terminal Count Up (TC
U
) Outputs are provided to
enable cascading of both up and down counting functions. The TC
D
output produces a negative going pulse when the counter underflows
and TC
U
outputs a pulse when the counter overflows. The counter can
be cascaded by connecting the TC
U
and TC
D
outputs of one device to
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC192N Plastic
SL74HC192D SOIC
T
A
= -55
to 125
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
SL74HC192
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL74HC192
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
6.0
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0
8.0
80
160
A
FUNCTION TABLE
Inputs
Mode
MR
PL
CP
U
CP
D
H
X
X
X
Reset(Asyn.)
L
L
X
X
Preset(Asyn.)
L
H
H
No Count
L
H
H
Count Up
L
H
H
Count Down
L
H
H
No Count
X = don't care
The IN74HC192 can be preset to any state, but
will not count beyond 9. If preset to state 10, 11, 12, 13,
14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4:
14, 15, 2 if counting Up, and follow the sequence 15,
14, 13, 12, 11, 10, 9 if counting Down.
Logic equations
For Terminal Count:
TC
U
= Q
0
Q
3
CP
U
TC
D
= Q
0
Q
1
Q
2
Q
3
CP
D
SL74HC192
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
f
max
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
2.0
4.5
6.0
12
36
43
3.2
16
19
2.6
13
15
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q (Figures
1 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
t
PLH
, t
PHL
Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
TLH
, t
THL
Maximum Output Transition Time,Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
20
18
110
23
20
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
60
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to -55
C
85
C
125
C
Unit
t
su
Minimum Setup Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
100
20
18
125
35
22
150
30
26
ns
t
h
Minimum Hold Time, Pn to PL (Figure
4)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
t
w
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
w
Minimum Pulse Width, PL
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
t
w
Minimum Pulse Width, MR
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
t
r
, t
f
Minimum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
100
500
400
100
500
400
100
500
400
ns
SL74HC192
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Test Circuit
SL74HC192
System Logic
Semiconductor
SLS
TIMING DIAGRAM
SL74HC192
System Logic
Semiconductor
SLS
EXPANDED LOGIC DIAGRAM
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