SL74HC323
System Logic
Semiconductor
SLS
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
The SL74HC323 is identical in pinout to the LS/ALS323. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC323 features a multiplexed parallel input/output data
port to active full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally
suited for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S
1
and S
2
, high. This places the outputs in the high-
impedance state, which permits data applied to the data port to be
clocked into the register. Reading out of the register can be
accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC323N Plastic
SL74HC323D SOIC
T
A
= -55
to 125
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
SL74HC323
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
35
mA
I
CC
DC Supply Current, V
CC
and GND Pins
75
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
SL74HC323
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA (P/Q)
I
OUT
7.8 mA (P/Q)
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
IN
=V
IH
or V
IL
I
OUT
4.0 mA (Q')
I
OUT
5.2 mA (Q')
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
or V
IH
I
OUT
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA (P/Q)
I
OUT
7.8 mA (P/Q)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
V
IN
=V
IH
or V
IL
I
OUT
4.0 mA (Q')
I
OUT
5.2 mA (Q')
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
6.0
0.1
1.0
1.0
A
I
OZ
Maximum Three-State
Leakage Current
(Q
A
thru Q
H
)
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
6.0
0.5
5.0
10
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0
8.0
80
160
A
SL74HC323
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q
A
' or Q
H
'
(Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q
A
or Q
H
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , OE1, OE2, S1, or S2
to Q
A
thru Q
H
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
, t
PZH
Maximum Propagation Delay , OE1, OE2, S1, or S2
to Q
A
thru Q
H
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Q
A
thru Q
H
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
TLH
, t
THL
Maximum Output Transition Time, Q
A
' or Q
H
'
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
thru Q
H
-
15
15
15
pF
Power Dissipation Capacitance (Per Package),
Outputs Enable
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
240
pF
SL74HC323
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to-55
C
85
C
125
C
Unit
t
su
Minimum Setup Time, Mode Select S1
or S2 to Clock (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
su
Minimum Setup Time, Data Inputs S
A
,
S
H
, P
A
thru P
H
to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
t
h
Minimum Hold Time, Clock to Data
Inputs, S
A
, S
H
, P
A
thru P
H
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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