SL74HC4046
System Logic
Semiconductor
SLS
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC4046 phase-locked loop contains three phase
comparators, a voltage-controlled oscillator (VCO) and unity gain op-
amp DEM
OUT
. The comparators have two common signal inputs,
COMP
IN
, and SIG
IN
. Input SIG
IN
and COMP
IN
can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self-bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator 1
(an exclusive OR gate) provides a digital error signal PC1
OUT
and
maintains 90 degrees phase shift at the center frequency between SIG
IN
and COMP
IN
signals (both at 50% duty cycle). Phase comparator 2
(with leading-edge sensing logic) provides digital error signals PC2
OUT
and PCP
OUT
and maintains a 0 degree phase shift between SIG
IN
and
COMP
IN
signals (duty cycle is immaterial). The linear VCO produces an
output signal VCO
OUT
whose frequency is determined by the voltage of
input VCO
IN
signal and the capacitor and resistors connected to pins
C1A, C1B, R1 and R2. The unity gain op-amp output DEM
OUT
with an external resistor is used where the VCO
IN
signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps
to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,
frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency
conversion and motor speed control.
Low Power Consumption Characteristic of CMOS Device
Operating Speeds Similary to LS/ALSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0
A Maximum (except SIG
IN
and
COMP
IN
)
Low Quiescent Current: 80
A Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Pin No.
Symbol
Name and Function
1
PCP
OUT
Phase Comparator Pulse Output
2
PC1
OUT
Phase Comparator 1 Output
3
COMP
IN
Comparator Input
4
VCO
OUT
VCO Output
5
INH
Inhibit Input
6
C1A
Capacitor C1 Connection A
7
C1B
Capacitor C1 Connection B
8
GND
Ground (0 V) V
SS
9
VCO
IN
VCO Input
10
DEM
OUT
Demodulator Output
11
R1
Resistor R1 Connection
12
R2
Resistor R2 Connection
13
PC2
OUT
Phase Comparator 2 Output
14
SIG
IN
Signal Input
15
PC3
OUT
Phase Comparator 3 Output
16
V
CC
Positive Supply Voltage
ORDERING INFORMATION
SL74HC4046N Plastic
SL74HC4046D SOIC
T
A
= -55
to 125
C for all packages
PIN ASSIGNMENT
SL74HC4046
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND) VCO only
3.0
6.0
V
V
CC
DC Supply Voltage (Referenced to GND) NON-VCO
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL74HC4046
System Logic
Semiconductor
SLS
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
V
OUT
= 0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High-Level
Output Voltage
PCP
OUT
, PCn
OUT
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage Q
a
-Q
h
PCP
OUT
, PCn
OUT
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
SIG
IN
, COMP
IN
V
IN
=V
CC
or GND
2.0
3.0
4.5
6.0
3.0
7.0
18.0
30.0
4.0
9.0
23.0
38.0
5.0
11.0
27.0
45.0
A
I
OZ
Maximum Three-State
Leakage Current
PC2
OUT
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
6.0
0.5
5.0
10
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
(VCO disabled)
Pins 3,5 and 14 at V
CC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0
4.0
40
160
A
SL74HC4046
System Logic
Semiconductor
SLS
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, SIG
IN
/COMP
IN
to
PC1
OUT
(Figure 1)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
, t
PHL
Maximum Propagation Delay, SIG
IN
/COMP
IN
to
PCP
OUT
(Figure 1)
2.0
4.5
6.0
340
68
58
425
85
72
510
102
87
ns
t
PLH
, t
PHL
Maximum Propagation Delay , SIG
IN
/COMP
IN
to
PC3
OUT
(Figure 1)
2.0
4.5
6.0
270
54
46
340
68
58
405
81
69
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , SIG
IN
/COMP
IN
Output Disable Time to PC2
OUT
(Figures 2 and 3)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
t
PZL
, t
PZH
Maximum Propagation Delay , SIG
IN
/COMP
IN
Output Enable Time to PC2
OUT
(Figures 2 and 3)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
t
TLH
, t
THL
Maximum Output Transition Time (Figure 1)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
[VCO Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C to-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage INH
V
OUT
= 0.1 V or
V
CC
-0.1 V
I
OUT
20
A
3.0
4.5
6.0
2.1
3.15
4.2
2.1
3.15
4.2
2.1
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage INH
V
OUT
=0.1 V or V
CC
-
0.1 V
I
OUT
20
A
3.0
4.5
6.0
0.90
1.35
1.8
0.90
1.35
1.8
0.90
1.35
1.8
V
V
OH
Minimum High-Level
Output Voltage
VCO
OUT
V
IN
=V
IH
or V
IL
I
OUT
20
A
3.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
VCO
OUT
V
IN
=V
IH
or V
IL
I
OUT
20
A
3.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
SL74HC4046
System Logic
Semiconductor
SLS
(continued)
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