TECHNICAL DATA
1
System Logic
Semiconductor
SLS
Hex Inverter
The SL74LV04 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT04A.
The SL74LV04 provides six inverting buffers.
Wide Operating Voltage: 1.0 ~ 5.5 V
Optimized for Low Voltage applications: 1.0 ~ 3.6 V
Accepts TTL input levels between V
CC
=2.7 V and V
CC
=3.6 V
Low Input Current
SL74LV04
ORDERING INFORMATION
SL74LV04N Plastic
SL74LV04D SOIC
SL74LV04
Chip
T
A
= -40
125
C for all packages
LOGIC DIAGRAM
PIN 14 =V
CC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Input
Output
A
Y
L
H
H
L
SL74LV04
2
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage (Referenced to GND)
-0.5 ~ +7.0
V
I
IK
*
1
DC input diode current
20
mA
I
OK
*
2
DC output diode current
50
mA
Io*
3
DC output source or sink current
-bus driver outputs
25
mA
I
GND
DC GND current for types with
- bus driver outputs
50
mA
I
CC
DC V
CC
current for types with
- bus driver outputs
50
mA
P
D
Power dissipation per package, plastic DIP+
SOIC package+
750
500
mW
Tstg
Storage temperature
-65 ~ +150
C
T
L
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SOIC Package: : - 8 mW/
C from 70
to 125
C
*
1
: V
I
<
-0.5V or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5V or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
1.0
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
0
0
0
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
SL74LV04
3
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test Conditions
V
CC
,
V
min max
min
max
min
max
Unit
V
IH
High-Level Input
Voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
IL
Low-Level Input
Voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
V
V
I
= V
IL
I
O
= -50
A
1.2
2.0
*
1.1
1.92
2.92
-
-
-
1.0
1.9
2.9
-
-
-
1.0
1.9
2.9
-
-
-
V
V
OH
High-Level Output
Voltage
V
I
= V
IL
I
O
= -6.0
A
*
2.48
-
2.34
-
2.20
-
V
V
OL
Low-Level Output
Voltage
V
I
= V
IH
I
O
= 50
A
1.2
2.0
-
-
-
0.09
0.09
0.09
-
-
-
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
V
V
I
= V
IH
or V
IL
I
O
= 6.0 m
3.0
-
0.33
-
0.4
-
0.5
V
I
IL
Low-Level Input
Leakage Current
-
-0.1
-
-1.0
-
-1.0
A
I
I
High-Level Input
Leakage Current
V
I
= V
CC
*
-
0.1
-
1.0
-
1.0
A
I
Quiescent Supply
Current
(per Package)
V
I
= 0 or V
CC
I
O
= 0
A
*
-
2.0
-
20
-
40
A
* : V
CC
= (3.30.3) V
SL74LV04
4
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
= t
HL
= 6.0 ns, V
IL
=0V, V
IH
=V
CC,
R
L
=1 k)
Guaranteed Limit
25
C
-40
C 85
C
-40
C 125
C
Symbol
Parameter
V
CC
V
min
max
min
max
min
max
Unit
t
THL,
(t
TLH)
Output Transition
Time, Any Output
(Figure 1)
1.2
2.0
*
-
-
70
16
10
-
-
-
85
20
13
-
-
-
100
24
15
ns
t
PHL,
(t
PLH)
Propagation Delay,
Input A to Output Y
(Figure 1)
1.2
2.0
*
-
-
-
90
23
14
-
-
-
120
28
18
-
-
-
150
34
21
C
I
Input Capacitance
3.0
-
-
-
3.5
-
3.5
pF
=25
, V
I
=0VV
CC
C
PD
Power Dissipation Capacitance (Per Inverter)
42
pF
Used to determine the no-load dynamic power consumption:
P
D
= C
PD
V
CC
2
f
I
+ (C
L
V
CC
2
fo), f
I
- input frequency, fo - output frequency (MHz)
(C
L
V
CC
2
fo) sum of the outputs
Figure 1. Switching Waveforms
Figure 2. Test Circuit
0.1
0.1
0.1
0.1
0.9
0.9
0.9
0.9
V
1
t
PHL
t
HL
t
THL
t
PLH
t
LH
t
TLH
V
1
V = 0.5 V
1
C C
Input
Output Y
GND
GND
V
CC
V
CC
V
1
V
1
PULSE
GENERATOR
DEVICE
UNDER
TEST
V
CC
V
I
V
O
C
L
R
L
R
T
Termination resistance R
T
should
be equal to Z
OUT
of pulse
generators
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