TECHNICAL DATA
1
System Logic
Semiconductor
SLS
Hex Schmitt-Trigger Inverter
The 74LV14 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger action.
Wide Operating Voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
=2.7 V and V
CC
=3.6 V
Low input current
SL74LV14
ORDERING INFORMATION
SL74LV14N Plastic
SL74LV14D SOIC
SL74LV14
Chip
T
A
= -40
125
C for all packages
LOGIC DIAGRAM
PIN 14 =V
CC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Input
Output
A
Y=
A
L
H
H
L
SL74LV14
2
System Logic
Semiconductor
SLS
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage (Referenced to GND)
-0.5 ~ +7.0
V
I
IK
*
1
DC input diode current
20
mA
I
OK
*
2
DC output diode current
50
mA
Io*
3
DC output source or sink current
-bus driver outputs
25
mA
I
GND
DC GND current for types with
- bus driver outputs
50
mA
I
CC
DC V
CC
current for types with
- bus driver outputs
50
mA
P
D
Power dissipation per paskade, plastic DIP+
SOIC package+
750
500
mW
Tstg
Storage temperature
-65 ~ +150
C
T
L
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SOIC Package: : - 8 mW/
C from 70
to 125
C
*
1
: V
I
<
-0.5V or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5V or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
1.0
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time
1.0 V
V
CC
<2.0 V
2.0 V
V
CC
<2.7 V
2.7 V
V
CC
<3.6 V
3.6 V
V
CC
5.5 V
0
0
0
0
500
200
100
50
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SL74LV14
3
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test
Conditions
V
CC
V
min
max
min
max
min
max
Unit
V
IT
+
Positive-Going
Input Threshold
Voltage
V
O
V
OH
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.45
0.85
1.05
1.25
1.55
1.75
2.15
0.95
1.35
1.95
2.15
2.35
3.10
3.80
0.4
0.8
1.0
1.2
1.5
1.7
2.1
1.0
1.4
2.0
2.2
2.4
3.15
3.85
0.4
0.8
1.0
1.2
1.5
1.7
2.1
1.0
1.4
2.0
2.2
2.4
3.15
3.85
V
V
IT
-
Negative-Going
Input Threshold
Voltage
V
O
V
OL
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.2
0.35
0.45
0.65
0.85
0.95
1.15
0.65
0.85
1.35
1.45
1.75
1.95
1.15
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.26
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.26
V
V
H
Hysteresis
Voltage
V
O
V
OH
V
O
V
OL
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.2
0.25
0.35
0.45
0.45
0.45
0.65
0.65
0.75
1.05
1.15
1.15
1.35
1.45
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.6
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.7
0.9
1.4
1.5
1.8
2.0
2.6
V
V
OH
High-Level
Output Voltage
V
I
= V
IH
or
V
IL
I
O
= -100
A
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
V
V
I
= V
IH
or
V
IL
I
O
= -6.0
mA
3.0
2.48
-
2.40
-
2.20
-
V
OH
High-Level
Output Voltage
V
I
= V
IH
or
V
IL
I
O
= -12.0
mA
4.5
3.70
-
3.60
-
3.50
-
V
V
OL
Low-Level
Output Voltage
V
I
= V
IH
or
V
IL
I
O
= 100
A
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
V
SL74LV14
4
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS
(continuation)
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test
Conditions
V
CC
V
min
max
min
max
min
max
Unit
V
I
= V
IH
or
I
O
= 6.0 mA
3.0
-
0.33
-
0.40
-
0.50
V
OL
Low-Level
Output Voltage
V
I
= V
IH
or
V
IL
I
O
= 12.0
mA
4.5
-
0.40
-
0.55
-
0.65
V
I
IL
Low-Level Input
Leakage Current
V
I
=0 V
5.5
-
-0.1
-
-1.0
-
-1.0
A
I
IH
High-Level
Input Leakage
Current
V
I
= V
5.5
-
0.1
-
1.0
-
1.0
I
CC
Quiescent
Supply Current
(per Package)
V
I
=0 or
V
I
O
= 0
A
5.5
-
4.0
-
20
-
40
A
I
CC1
Additional
Quiescent
Supply Current
on input
V
I
= V
-
0.6V
I
O
= 0
A
2.7
3.6
-
0.2
-
0.5
-
0.85
mA
.
SL74LV14
5
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
=t
HL
= 2.5 ns, R
L
=1 k)
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test
Conditions
V
CC
V
min
max
min
max
min
max
Unit
t
PLH
, t
PHL
Propagation
Delay, Input A
to Output Y
(Figure 1 )
V
I
=0 V or
V
1
t
LH
= t
HL
=2.5 ns
L
= 50 pF
R
L
= 1 k
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
150
28
22
17
14
-
-
-
-
-
170
37
28
22
18
-
-
-
-
-
200
48
35
28
23
ns
C
I
Input
Capacitance
5.5
-
7.0
-
7.0
-
7.0
pF
C
PD
V
I
=0 V or
V
5.5
-
30
-
30
-
30
pF
V
X
=0.5 V
CC
Figure 1. Switching Waveforms
Figure 2. Test Circuit
0.1
0.1
0.9
0.9
V
X
V
X
t
P H L
t
H L
t
PL H
t
L H
V
Y
V
Y
Input
Output Y
GND
V
O L
V
1
V
O H
P U L S E
G E N E R A T O R
D E V I C E
U N D E R
T E S T
V
C C
V
I
V
O
C
L
R
L
R
T
Termination resistance R
T
should
be equal to Z
OUT
of pulse
generators
SL74LV14
6
System Logic
Semiconductor
SLS
CHIP PAD DIAGRAM SL74LV14
Pad size 0.108 x 0.108 mm (Pad size is given as per
metallization
layer)
Thickness of chip 0.46
0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
A1
0.130
0.463
02
Y1
0.130
0.230
03
A2
0.381
0.126
04
Y2
0.616
0.126
05
A3
0.881
0.126
06
Y3
1.116
0.126
07
GND
1.115
0.631
08
Y4
1.115
0.846
09
A4
1.115
1.181
10
Y5
0.804
1.194
11
A5
0.569
1.194
12
Y6
0.378
1.194
13
A6
0.143
1.194
14
V
CC
0.130
0.813
01
02
03
04
05
06
07
08
09
10
11
12
13
14
1
.
4
2
0
.
0
3
1.33 0.03
Chip marking
IN74LV14
(x=0.130; y=0.130
)
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