Infrared Communications Controller Chip
CameraFR
FEATURES
!"
Mixed Voltage Support
-
Supports 3.3V Operation
-
Supports Mixed Internal 3.3V
Operation with 3.3V/5V External
Configuration
!"
Intelligent Auto Power Management
-
Supports Multiple Power Down
Modes
!"
Serial Port
-
High Speed NS16C550A Compatible
UART with 16-Byte Send/Receive
FIFOs
-
Programmable Baud Rate Generator
!"
Infrared Port
-
Multi-Protocol Infrared Interface
-
128-Byte Data FIFO
-
IrDA 1.1 Compliant (up to 4Mbps)
- Consumer
IR
-
SHARP ASK IR
-
Programmed I/O and DMA Options
!"
Up to 5 General Purpose I/O Pins
!"
Programmable Multi-Protocol Host Interface
-
ISA-Style 5 Bit Address and 8 Bit
Data
Bus
-
IOCHRDY and No Wait State Support
for
Fast
IR
-
Non-ISA 8 Bit Multiplexed
Address/Data
Bus
-
Programmable Read/Write Interface
-
One 8 Bit DMA Channel
-
One Programmable IRQ
- Chip
Select
-
Multihost Interface Support Includes
Hitachi and Mitsubishi
Microcontrollers
!"
24MHz Crystal Oscillator
-
Supports Internal or External Clock
Source
!"
48 Pin TQFP Package
GENERAL DESCRIPTION
The CAM35C44 with IrDA v1.1 (4Mbps) and
Consumer IR support incorporates SMSC's
advanced Infrared Communications Controller
(IrCC 2.0), a 16C550A-compatible UART,
Multiple Host Interface options, flexible Address
Decoding and up to five General Purpose I/Os.
The CAM35C44 also features sophisticated
power control circuitry to support multiple power
down modes, an on-chip 24MHz crystal
oscillator, and 12mA host bus drivers.
The CAM35C44 is particularly suited for 3.3v
battery-powered systems.
CAM35C44
ADVANCE INFORMATION
2
TABLE OF CONTENTS
FEATURES.............................................................................................................................................. 1
GENERAL DESCRIPTION ...................................................................................................................... 1
ARCHITECTURE ..................................................................................................................................... 4
PIN CONFIGURATION ............................................................................................................................ 5
DESCRIPTION OF PIN FUNCTIONS ...................................................................................................... 6
B
UFFER
-T
YPE
S
UMMARY
........................................................................................................................... 11
CLOCK GENERATOR........................................................................................................................... 12
MULTIHOST CPU INTERFACE ............................................................................................................ 13
H
OST
I
NTERFACE
S
ELECT
.......................................................................................................................... 14
H
OST
I
NTERFACE
P
IN
M
ULTIPLEXING
........................................................................................................... 14
System Data Bus ................................................................................................................................... 14
ISA Address Bus SA0 - SA1 .................................................................................................................. 15
ISA Address Bus SA2 - SA4 .................................................................................................................. 15
ISA nIOR ................................................................................................................................................ 15
ISA nIOW ............................................................................................................................................... 15
REGISTER ADDRESS MAP.................................................................................................................. 16
N
ON
-M
ULTIPLEXED
(ISA) A
DDRESSING
....................................................................................................... 16
M
ULTIPLEXED
A
DDRESSING
........................................................................................................................ 17
CONFIGURATION ................................................................................................................................. 18
C
ONFIGURATION
A
CCESS
P
ORTS
................................................................................................................ 18
C
ONFIGURATION
S
TATE
............................................................................................................................. 19
C
ONFIGURATION
R
EGISTERS
...................................................................................................................... 21
INFRARED INTERFACE ....................................................................................................................... 30
I
R
DA SIR/FIR ......................................................................................................................................... 30
ASKIR .................................................................................................................................................... 30
C
ONSUMER
IR .......................................................................................................................................... 30
H
ARDWARE
I
NTERFACE
............................................................................................................................. 30
GENERAL PURPOSE I/O ..................................................................................................................... 32
I
NTRODUCTION
.......................................................................................................................................... 32
D
ESCRIPTION
............................................................................................................................................ 32
R
EGISTERS
.............................................................................................................................................. 34
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 36
A.C. TIMING .......................................................................................................................................... 38
C
LOCK AND
R
ESET
T
IMING
......................................................................................................................... 38
R
EAD
C
YCLE
T
IMING
(N
ON
-M
ULTIPLEXED
)................................................................................................... 39
R
EAD
C
YCLE
T
IMING
(M
ULTIPLEXED
)........................................................................................................... 40
W
RITE
C
YCLE
T
IMING
(N
ON
-M
ULTIPLEXED
) ................................................................................................. 41
W
RITE
C
YCLE
T
IMING
(M
ULTIPLEXED
) ......................................................................................................... 42
4
ARCHITECTURE
There are six basic architectural components in
the CAM35C44: the multihost CPU interface, the
IrCC 2.0, a clock generator, configuration
registers, power management, and general
purpose I/O (
FIGURE
1).
The multihost CPU interface is capable of
supporting several bus configurations; including,
a non-multiplexed ISA-style address and data
bus, and a multiplexed address/data bus with
selectable read/write command options. The
multihost CPU interface includes support for
Hitachi and Mitsubishi microcontrollers.
The IrCC 2.0 is a multi-protocol serial
communications controller that incorporates an
ACE 16C550A UART and a Synchronous
Communications Engine (SCE). Refer to the
SMSC Infrared Communications Controller 2.0
specification for more information.
The clock generator provides connections for a
24MHz crystal or an external clock source. The
24MHz clock directly drives the ACE block. An
internal PLL is used for data rates above
115.2Kbps.
Power management in the CAM35C44 includes
various power down modes and an infrared
wake-up option. The general purpose I/O
interface provides generic I/O programming
capabilities.
FIGURE 1 - CAM35C44 BLOCK DIAGRAM
MULTIHOST
CPU
INTERFACE
SD[7:0]/AD[7:0]
SA[1:0]/GPIO[4:3]
SA[4:2]/BS[2:0]
nCS
AEN
ASTRB
IOCHRDY
nNOWS
RESET_DRV
IRQ
DRQ
nDACK
TC
nIOR/RW
nIOW/DSTRB
CLOCK
GEN
GENERAL
PURPOSE
I/O
GPIO[2:0]
POWER
MGMT
CONFIGURATION
REGISTERS
IRCC 2.0
IRRX
IRTX
IRMODE/IRRX3
POWER
RXD/IRRX
TXD/IRTX
CONTROL
DATA
ADDRESS
X1/CLK1
x2
PWRGD
VCC[2:1],VSS[3:1],
VIO
HS1
HS0
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