SMSC COM20020I Rev D
Page 1
Rev. 08-13-03
DATASHEET
COM20020I Rev D
Universal Local Area Network
Controller with 2K x 8 On-Board
RAM
Datasheet
Product Features
New Features for Rev. D
- Data Rates up to 5 Mbps
- Programmable Reconfiguration Times
24 Pin DIP, 28 Pin PLCC, 48 Pin TQFP
Packages
Ideal for Industrial/Factory/Building
Automation and Transportation Applications
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Media Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microprocessors
Automatically Detects Type of
Microcontroller Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Eight, 256 Byte Pages Allow Four Pages TX
and RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
Operating Temperature Range of -40
o
C to
+85
o
C
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star,
Tree, Bus...)
CMOS, Single +5V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
- Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5Mbps.
- RS485 Differential Driver Interface For Low
Cost, Low Power, High Reliability
ORDERING INFORMATION
Order Number(s):
COM20020I-LJP for 28 pin PLCC package
COM20020I-P for 24 pin DIP package
COM20020I-HD for 48 pin TQFP package
Universal Local Area Network Controller with 2K x 8 On-Board RAM
Datasheet
Rev. 08-13-03
Page 2
SMSC COM20020I Rev D
DATASHEET
STANDARD MICROSYSTEMS CORPORATION (SMSC) 2003
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the
trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;
consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is
believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product
descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The
provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or
others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms
of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as
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products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or
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Universal Local Area Network Controller with 2K x 8 On-Board RAM
Datasheet
SMSC COM20020I Rev D
Page 3
Rev. 08-13-03
DATASHEET
Revision History
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY CORRECTION
07/03/01
Figure 2.2 - - Pin Configuration -
COM20020I 48-Pin TQFP, pg. 9
48 pin TQFP added
07/03/01
Figure 9.3 - 48 Pin TQFP Package Outline,
pg. 69
48 pin TQFP added
Universal Local Area Network Controller with 2K x 8 On-Board RAM
Datasheet
Rev. 08-13-03
Page 4
SMSC COM20020I Rev D
DATASHEET
Table of Contents
Revision History .......................................................................................................................................... 3
Chapter 1
General Description................................................................................................................ 7
Chapter 2
Pin Configurations .................................................................................................................. 8
Chapter 3
Description of Pin Functions ................................................................................................ 10
Chapter 4
Protocol Description ............................................................................................................. 13
4.1
Network Protocol........................................................................................................................................13
4.2
Data Rates .................................................................................................................................................13
4.2.1
Selecting Clock Frequencies Above 2.5 Mbps....................................................................................13
4.3
Network Reconfiguration ............................................................................................................................14
4.4
Broadcast Messages..................................................................................................................................15
4.5
Extended Timeout Function .......................................................................................................................15
4.5.1
Response Time ...................................................................................................................................15
4.5.2
Idle Time .............................................................................................................................................15
4.5.3
Reconfiguration Time ..........................................................................................................................15
4.6
Line Protocol ..............................................................................................................................................15
4.6.1
Invitations To Transmit........................................................................................................................16
4.6.2
Free Buffer Enquiries ..........................................................................................................................16
4.6.3
Data Packets.......................................................................................................................................16
4.6.4
Acknowledgements .............................................................................................................................17
4.6.5
Negative Acknowledgements..............................................................................................................17
Chapter 5
System Description .............................................................................................................. 18
5.1
Microcontroller Interface.............................................................................................................................18
5.1.1
High Speed CPU Bus Timing Support ................................................................................................21
5.2
Transmission Media Interface ....................................................................................................................22
5.2.1
Traditional Hybrid Interface .................................................................................................................22
5.2.2
Backplane Configuration .....................................................................................................................22
5.2.3
Differential Driver Configuration ..........................................................................................................24
5.2.4
Programmable TXEN Polarity .............................................................................................................24
Chapter 6
Functional Description.......................................................................................................... 27
6.1
Microsequencer..........................................................................................................................................27
6.2
Internal Registers .......................................................................................................................................28
6.2.1
Interrupt Mask Register (IMR) .............................................................................................................28
6.2.2
Data Register ......................................................................................................................................29
6.2.3
Tentative ID Register ..........................................................................................................................29
6.2.4
Node ID Register.................................................................................................................................29
6.2.5
Next ID Register..................................................................................................................................29
6.2.6
Status Register....................................................................................................................................30
6.2.7
Diagnostic Status Register..................................................................................................................30
6.2.8
Command Register .............................................................................................................................30
6.2.9
Address Pointer Registers ..................................................................................................................30
6.2.10
Configuration Register.....................................................................................................................30
6.2.11
Sub-Address Register .....................................................................................................................30
6.2.12
Setup 1 Register..............................................................................................................................31
6.2.13
Setup 2 Register..............................................................................................................................31
6.3
Internal RAM ..............................................................................................................................................41
6.3.1
Sequential Access Memory.................................................................................................................41
6.3.2
Access Speed .....................................................................................................................................41
6.4
Software Interface ......................................................................................................................................41
6.4.1
Selecting RAM Page Size ...................................................................................................................42
6.4.2
Transmit Sequence .............................................................................................................................43
6.4.3
Receive Sequence ..............................................................................................................................45
6.5
Command Chaining....................................................................................................................................46
6.5.1
Transmit Command Chaining .............................................................................................................46
6.5.2
Receive Command Chaining ..............................................................................................................47
6.6
Reset Details..............................................................................................................................................48
6.6.1
Internal Reset Logic ............................................................................................................................48
6.7
Initialization Sequence ...............................................................................................................................48
Universal Local Area Network Controller with 2K x 8 On-Board RAM
Datasheet
SMSC COM20020I Rev D
Page 5
Rev. 08-13-03
DATASHEET
6.7.1
Bus Determination...............................................................................................................................48
6.8
Improved Diagnostics.................................................................................................................................49
6.8.1
Normal Results:...................................................................................................................................49
6.8.2
Abnormal Results:...............................................................................................................................49
6.9
Oscillator ....................................................................................................................................................50
Chapter 7
Operational Description........................................................................................................51
7.1
Maximum Guaranteed Ratings* .................................................................................................................51
7.2
DC Electrical Characteristics......................................................................................................................51
Chapter 8
Timing Diagrams .................................................................................................................. 54
Chapter 9
Package Outlines ................................................................................................................. 67
Appendix A.................................................................................................................................................. 70
Appendix B -
Example of Interface Circuit Diagram to ISA Bus ............................................................. 73
Appendix C -
Software Identification of the COM20020 Rev B, Rev C and Rev D ................................ 74
List of Figures
Figure 2.1 - Pin Configuration - COM20020I 24-Pin DIP or 28-Pin PLCC......................................................................8
Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP ............................................................................................9
Figure 3.1 - COM20020ID Operation ...........................................................................................................................12
Figure 5.1 Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................19
Figure 5.2 Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ............................................................20
Figure 5.3 High Speed CPU Bus Timing Intel CPU Mode......................................................................................21
Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers ...............................................................23
Figure 5.5 Dipulse Waveform for Data of 1-1-0.........................................................................................................23
Figure 5.6 - Internal Block Diagram..............................................................................................................................25
Figure 6.1 - Sequential Access Operation.....................................................................................................................40
Figure 6.2 - RAM Buffer Packet Configuration .............................................................................................................43
Figure 6.3 Command Chaining Status Register Queue..............................................................................................45
Figure 8.1 Multiplexed Bus, 68XX-Like Control Signals; Read Cycle........................................................................54
Figure 8.2 Multiplexed Bus, 80XX-Like Control Signals; Read Cycle........................................................................55
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................56
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................57
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................59
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................61
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................62
Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................63
Figure 8.11 - Normal Mode Transmit or Receive Timing..............................................................................................64
Figure 8.12 - Backplane Mode Transmit or Receive Timing ........................................................................................65
Figure 8.13 - TTL Input Timing on XTAL1 Pin..............................................................................................................66
Figure 8.14 - Reset and Interrupt Timing .....................................................................................................................66
Figure 9.1 - 28 Pin PLCC Package Dimensions...........................................................................................................67
Figure 9.2 - 24 Pin Dip Package Dimensions...............................................................................................................68
Figure 9.3 - 48 Pin TQFP Package Outline..................................................................................................................69
Figure 0.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................72
List of Tables
Table 5.1 - Typical Media.............................................................................................................................................25
Table 6.1 - Read Register Summary............................................................................................................................27
Table 6.2 - Write Register Summary ............................................................................................................................28
Table 6.3 - Status Register ...........................................................................................................................................32
Table 6.4 -
Diagnostic Status Register
............................................................................................................................33
Table 6.5 - Command Register.....................................................................................................................................34
Table 6.6 - Address Pointer High Register ....................................................................................................................35
Table 6.7 - Address Pointer Low Register.....................................................................................................................35
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