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Электронный компонент: COM90C66

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1
COM90C66
Data Sheet with Erratas for
Rev. B and Rev. D devices
ARCNET
Controller/Transceiver with
AT
Interface and On-Chip RAM
FEATURES
ARCNET LAN Controller/Transceiver/
Support Logic/Dual-Port RAM
Integrates SMSC COM90C65 with 16-Bit
Data Bus, Dual-Port RAM, and Enhanced
Diagnostics Circuitry
Includes IBM
PC/AT
Bus Interface
Circuitry
Supports 8- and 16-Bit Data Buses
Full 2K x 8 On-Chip Dual-Port Buffer RAM
Zero Wait State Arbitration for Most AT
Buses
SMSC COM90C26 Software Compatible
Command Chaining Enhances Performance
Supports Memory Mapped and Sequential
I/O Mapped Access to the Internal RAM
Buffer
Compatible with the SMSC HYC9058/68/ 88
(COAX and Twisted Pair Drivers)
Token Passing Protocol with Self
Reconfiguration Detection
Variable Data Length Packets
16 Bits CRC Check/Generation
Includes Address Decoding Circuitry for On-
Chip RAM, PROM and I/O
Supports up to 255 Nodes
Contains Software Accessible Node ID
Register
Compatible with Various Topologies (Star,
Tree, Bus, ...)
On-Board Crystal Oscillator and Reset
Circuitry
Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
The SMSC COM90C66 is a special purpose
communications controller for interconnecting
processors and intelligent peripherals using the
ARCNET Local Area Network. The COM90C66
is unique in that it integrates the core ARCNET
logic found in Standard Microsystems' original
COM90C26 and COM90C32 with an on-chip 2K
x 8 RAM, as well as the 16-bit data bus interface
for the IBM PC/AT. Because of the inclusion of
the RAM buffer in the COM90C66, a complete
ARCNET node can be implemented with only
one or two additional ICs (8- or 16-bit
applications, respectively) and a media driver
circuit. The ARCNET core remains functionally
untouched, eliminating validation and
compatibility concerns. The enhancements exist
in the integration and the performance of the
device. Maximum integration has been achieved
by including the 2K x 8 RAM buffer on the chip,
providing the immediate benefits of a lower
device pin count and less board components.
The performance is enhanced in four ways: a
16-bit data bus for operation with the IBM PC/AT;
a zero wait state arbitration mechanism, due
partly to the integration of the RAM buffer on-
chip; the ability of the device to do consecutive
transmissions and receptions via the Command
Chaining operation; and improved diagnostics,
allowing the user to control the system more
efficiently. For most AT compatibles, the device
handles zero wait state transfers.
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
International Business Machines Corporation
2
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................................ 1
GENERAL DESCRIPTION ................................................................................................................................................ 1
PIN CONFIGURATION...................................................................................................................................................... 3
DESCRIPTION OF PIN FUNCTIONS ............................................................................................................................... 4
PROTOCOL DESCRIPTION ............................................................................................................................................. 9
NETWORK PROTOCOL........................................................................................................................................... 9
NETWORK RECONFIGURATION ........................................................................................................................... 9
BROADCAST MESSAGES ..................................................................................................................................... 10
EXTENDED TIMEOUT FUNCTION ........................................................................................................................ 10
LINE PROTOCOL .................................................................................................................................................... 10
SYSTEM DESCRIPTION..................................................................................................................................................12
MICROPROCESSOR INTERFACE .........................................................................................................................12
TRANSMISSION MEDIA INTERFACE ....................................................................................................................13
FUNCTIONAL DESCRIPTION .........................................................................................................................................13
MICROSEQUENCER ...............................................................................................................................................13
ADDRESS DECODING ............................................................................................................................................19
INTERNAL REGISTERS ..........................................................................................................................................22
INTERNAL RAM .......................................................................................................................................................29
SOFTWARE INTERFACE........................................................................................................................................29
SOFTWARE COMPATIBILITY CONSIDERATIONS ..............................................................................................31
COMMAND CHAINING ............................................................................................................................................32
RESET DETAILS ......................................................................................................................................................34
READ AND WRITE CYCLES ...................................................................................................................................35
NODE ID LOGIC .......................................................................................................................................................43
TRANSMIT/RECEIVE LOGIC ..................................................................................................................................43
IMPROVED DIAGNOSTICS.....................................................................................................................................43
OSCILLATOR ...........................................................................................................................................................45
OPERATIONAL DESCRIPTION ......................................................................................................................................46
MAXIMUM GUARANTEED RATINGS .....................................................................................................................46
DC CHARACTERISTICS..........................................................................................................................................46
TIMING DIAGRAMS .........................................................................................................................................................49
Please see Addendum 1 entitled Data Sheet Errata for Revision B COM90C66, which discusses changes to this
data sheet which apply to the Revision B device, on Page 62.
Please see Addendum 2 entitled Data Sheet Errata for Revision D COM90C66, which discusses changes to this
data sheet which apply to the Revision D device, on Page 64.
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
3
For other machines, the IOCHRDY signal may
be briefly negated to give the device the extra
time necessary to support the faster machines.
Aside from the implementation of a 16-bit data
bus interface, the remaining bus interface logic
is identical to that found in the SMSC
COM90C65, which contains all the support logic
circuitry.
The ARCNET Local Area Network is a token
passing network which operates at a 2.5 Mbps
data rate. A token passing protocol provides
predictable response times because each
network event occurs within a known time
interval. Throughput can be reliably predeter-
mined based upon the number of nodes and
their expected traffic.
The COM90C66 establishes the network
configuration and automatically reconfigures the
token passing order as new nodes are added or
deleted from the network.
The COM90C66 performs address recognition,
CRC checking and generation, packet
acknowledgement, and other network
management functions. The C0M90C66
interfaces directly to the IBM PC/AT or
compatibles. The internal 2K x 8 RAM buffer is
used to hold up to four data packets with a
maximum length of 508 bytes each.
PIN CONFIGURATION
AEN
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
INTR
nBSLED
nTXLED
nPROM
nPULSE1
nPULSE2
RXIN
CLK
CACLK
NC
NC
nTOPH
nIOR
nIOW
nMEMR
nMEMW
GND
nIOCS16
nMEMCS16
X
T
A
L
1
X
T
A
L
2
N
I
D
0
N
I
D
1
N
I
D
2
N
I
D
3
N
I
D
4
N
I
D
5
N
I
D
6
N
I
D
7
V
C
C
I
O
S
2
I
O
S
1
I
O
S
0
M
S
4
M
S
3
M
S
2
M
S
1
M
S
0
R
E
S
E
T

I
N
n
E
N
R
O
M
A
1
9
A
1
8
A
1
7
A
1
6
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
V
C
C
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
11 10
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38
40 41 42 43 44 45 46 47 48 49 50 51 52 53
39
IOCHRDY
nOWS
nSBHE
BALE
PACKAGE: 84-Pin PLCC
Ordering Information: COM90C66 LJP
nTOPL
COM90C66
4
DESCRIPTION OF PIN FUNCTIONS
PLCC
PIN NO.
NAME
SYMBOL
DESCRIPTION
PROCESSOR INTERFACE
75-84, 2-
11
Address 0-19
A0-A19
Input. These signals are connected to the address lines
of the host processor and are used to access memory
and I/O locations of the COM90C66, as well as to access
the external ROM through the COM90C66.
13-20,
22-29
Data 0-15
D0-D15
Input/Output. These signals are used by the host to
transmit data to and from the internal registers and buffer
memory of the COM90C66 and are connected to weak
internal pull-up resistors.
63, 62
nTransceiver
Direction
Control
nTOPL,
nTOPH
Output. These active low signals control the data bus
transceiver. When these signals are high, data gets sent
from the PC to the COM90C66. When these signals are
low, data gets sent from the COM90C66 to the PC, or
from the PROM to the PC if the PROM signal is also low.
71
I/O Channel
Ready
IOCHRDY
Output. This signal, when low, is optionally used by the
COM90C66 to extend host cycles. This is an open-drain
signal. An external pull-up resistor is typically provided
by the system.
12
Address
Enable
AEN
Input. This signal, when low, acts as a qualifier for I/O
Address Selection. When the signal is high, I/O
decoding is disabled. This signal has no effect on
Memory Address Selection.
74
Address Latch
Enable
BALE
Input. The falling edge of this signal is used by the
COM90C66 to latch the A0-A19 lines and the nSBHE
signal via an internal transparent latch. This signal is
connected to a weak internal pull-up resistor.
64
nI/O Read
nIOR
Input. This active low signal is issued by the host
microprocessor to indicate an I/O Read operation. A low
level on this pin when the COM90C66 is accessed
enables data from the internal registers of the
COM90C66.
65
nI/O Write
nIOW
Input. This active low signal is issued by the host
microprocessor to indicate an I/O Write operation. A low
pulse on this pin when the COM90C66 is accessed
enables data from the Data Bus into the internal registers
of the COM90C66.
5
DESCRIPTION OF PIN FUNCTIONS
PLCC
PIN NO.
NAME
SYMBOL
DESCRIPTION
66
nMemory Read nMEMR
Input. This active low signal is issued by the host
microprocessor to indicate a Memory Read operation. A
low level on this pin when the COM90C66 is accessed
enables data from the internal RAM of the COM90C66 or
the PROM onto the data bus to be read by the host.
67
nMemory
Write
nMEMW
Input. This active low signal is issued by the host
microprocessor to indicate a Memory Write operation. A
low pulse on this pin when the COM90C66 is accessed
enables data from the data bus into the internal RAM of
the COM90C66.
52
Reset In
RESETIN
Input. This active high signal is the power on reset signal
from the host. It is used to activate the internal reset
circuitry within the COM90C66.
53
nROM Enable
nENROM
Input. This active low signal enables the decoding of the
external PROM. This signal also affects the timing of
IOCHRDY and the number of address lines used to
decode nMEMCS16. This signal is connected to a weak
internal pull-up resistor.
54
nROM Select
nPROM
Output. This active low signal is issued by the
COM90C66 to enable the external 8-bit wide PROM or
the external register of the COM90C66.
30
Interrupt
Request
INTR
Output. This active high signal is generated by the
COM90C66 when an enabled interrupt condition occurs.
INTR returns to its inactive state when the interrupt
status condition or the corresponding interrupt mask bit
is reset.
72
nZero Wait
State
n0WS
Output. This active low signal is used to force zero wait
state access cycles on the IBM PC Bus. This is an open-
drain signal. An external pull-up resistor is typically
provided by the system.
70
nMemory
16-Bit Chip
Select
nMEMCS16
Output. This active low signal is used to indicate that the
present data transfer is a 16-bit memory cycle. The
COM90C66 can be configured to use A19-A17 or A19-
A11 to generate nMEMCS16. This is an open-drain
signal. An external pull-up resistor is typically provided
by the system.