FDC37C93xFR
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/O
TM
TM
Controller
with Fast IR
FEATURES
5 Volt Operation
ISA Plug-and-Play Standard (Version 1.0a)
Compatible Register Set
Soft Power Management, SMI Support
ACCESS.bus Support
8042 Keyboard Controller
-
2K Program ROM
-
256 Bytes Data RAM
-
Asynchronous Access to Two Data
Registers and One Status Register
-
Supports Interrupt and Polling Access
-
8 Bit Timer/Counter
-
Port 92 Support
-
Fast Gate A20 and Hardware Keyboard
Reset
Real Time Clock
-
MC146818 and DS1287 Compatible
-
256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
-
128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
-
12 and 24 Hour Time Format
-
Binary and BCD Format
-
1
A Standby Current (typ)
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
Four DMA Options
-
Licensed CMOS 765B Floppy Disk
Controller
-
Advanced Digital Data Separator
-
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
-
Game Port Select Logic
-
Supports Two Floppy Drives Directly
-
24mA AT Bus Drivers
-
Low Power CMOS Design
Licensed CMOS 765B Floppy Disk
Controller Core
-
Supports Vertical Recording Format
-
16 Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun
Conditions
-
48mA Drivers and Schmitt Trigger Inputs
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
Enhanced Digital Data Separator
-
Low Cost Implementation
-
No Filter Components Required
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
-
Programmable Precompensation Modes
Serial Ports
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
2
TABLE OF CONTENTS
FEATURES ...................................................................................................................................... 1
GENERAL DESCRIPTION................................................................................................................ 3
PIN CONFIGURATION...................................................................................................................... 4
DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 5
FUNCTIONAL DESCRIPTION ........................................................................................................ 14
SUPER I/O REGISTERS.............................................................................................................14
HOST PROCESSOR INTERFACE .............................................................................................14
FLOPPY DISK CONTROLLER ................................................................................................... 15
FLOPPY DISK CONTROLLER INTERNAL REGISTERS .............................................................15
COMMAND SET/DESCRIPTIONS .................................................................................................. 39
INSTRUCTION SET ........................................................................................................................ 43
SERIAL PORT (UART) .................................................................................................................... 69
INFRARED INTERFACE...................................................................................................................84
FAST IR .......................................................................................................................................... 85
PARALLEL PORT........................................................................................................................... 87
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ................................................89
EXTENDED CAPABILITIES PARALLEL PORT............................................................................95
AUTO POWER MANAGEMENT .....................................................................................................111
INTEGRATED DRIVE ELECTRONICS INTERFACE ..................................................................... 116
HOST FILE REGISTERS ..........................................................................................................116
TASK FILE REGISTERS ...........................................................................................................116
IDE OUTPUT ENABLES ...........................................................................................................117
BIOS BUFFER ..........................................................................................................................117
GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION ...............................................................120
8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL DESCRIPTION ...........134
SOFT POWER MANAGEMENT..................................................................................................... 159
SYSTEM MANAGEMENT INTERRUPT (SMI) ................................................................................ 162
ACCESS.BUS ............................................................................................................................... 163
CONFIGURATION......................................................................................................................... 169
OPERATIONAL DESCRIPTION..................................................................................................... 216
MAXIMUM GUARANTEED RATINGS....................................................................................... 216
DC ELECTRICAL CHARACTERISTICS.................................................................................... 216
TIMING DIAGRAMS ...................................................................................................................... 221
ECP PARALLEL PORT TIMING..................................................................................................... 247
80 Arkay Drive
Hauppauge, NY. 11788
(516) 435-6000
FAX (516) 273-3123
3
-
Programmable Baud Rate Generator
-
Modem Control Circuitry Including 230K
and 460K Baud
-
IrDA, HP-SIR, ASK-IR Support, Fast IR
(4Mbps IrDA), Consumer IR
IDE Interface
-
Relocatable to 480 Different Addresses
-
13 IRQ Options (IRQ Steering through
Chip)
-
Two Channel/Four Drive Support
-
On-Chip Decode and Select Logic
Compatible with IBM PC/XT and
PC/AT Embedded Hard Disk Drives
Serial EEPROM Interface
Multi-Mode
TM
Parallel Port with ChiProtect
TM
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
Four DMA Options
-
Enhanced Mode
-
Standard Mode:
-
IBM PC/XT, PC/AT, and PS/2
TM
Compatible Bidirectional Parallel Port
-
Enhanced Parallel Port
-
(EPP) Compatible - EPP 1.7 and EPP
1.9 (IEEE 1284 Compliant)
-
High Speed Mode
-
Microsoft and Hewlett Packard
Extended Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
-
Incorporates ChiProtect
TM
Circuitry for
Protection Against Damage Due to
Printer Power-On
-
12 mA Output Drivers
ISA Host Interface
16 Bit Address Qualification
160 Pin QFP Package
GENERAL DESCRIPTION
The FDC37C93xFR with Fast IR support
incorporates a keyboard interface, real-time
clock, SMSC's true CMOS 765B floppy disk
controller, advanced digital data separator, 16
byte data FIFO, two 16C550 compatible UARTs,
one Multi-Mode parallel port which includes
ChiProtect circuitry plus EPP and ECP support,
IDE interface, on-chip 24 mA AT bus drivers,
game port chip select and two floppy direct drive
support, as well as ACCESS.bus, soft power
management and SMI support. The true CMOS
765B core provides 100% compatibility with IBM
PC/XT and PC/AT architectures in addition to
providing data overflow and underflow
protection. The SMSC advanced digital data
separator incorporates SMSC's patented data
separator technology, allowing for ease of
testing and use. Both on-chip UARTs are
compatible with the NS16C550. The parallel
port, the IDE interface, and the game port select
logic are compatible with IBM PC/AT
architecture, as well as EPP and ECP. The
FDC37C93xFR incorporates sophisticated
power control circuitry (PCC). The PCC
supports multiple low power down modes. The
FDC37C93xFR provides support for the ISA
Plug-and-Play Standard (Version 1.0a) and
provides for the recommended functionality to
support Windows '95. Through internal
configuration registers, each of the
FDC37C93xFR's logical device's I/O address,
DMA channel and IRQ channel may be
programmed. There are 480 I/O address
location options, 13 IRQ options, and three DMA
channel options for each logical device. The
FDC37C93xFR does not require any external
filter components and is, therefore, easy to use
and offers lower system cost and reduced board
area. The FDC37C93xFR is software and
register compatible with SMSC's proprietary
82077AA core.
IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark
of International Business Machines Corporation
SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode
are trademarks of Standard Microsystems Corporation
4
PIN CONFIGURATION
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
GND
DRVDEN0
DRVDEN1
nMTR0
nDS1
nDS0
nMTR1
GND
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
nDSKCHG
MEDIA_ID1
mEDIA_ID0
VCC
CLOCKI
nIDE1_OE
nHDCS0
nHDCS1
IDE1_IRQ
nHDCS2/SA13
nHDCS3/SA14
IDE2_IRQ/SA15
nIOROP
nIOWOP
VTR
nPOWER ON
BUTTON_IN
HCLK
16CLK
CLK01
CLK02
CLK03
GND
nROMDIR
nROMCS
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
GP25
GP24
GP23
GP22
GP21
GP20
GP17
GP16
GP15
VCC
GP14
GP13
GP12
GP11
GP10
GND
MCLK
MDAT
KCLK
KDAT
IOCHRDY
TC
DRQ3
nDACK3
DRQ2
nDACK2
DRQ1
nDACK1
DRQ0
nDACK0
n
D
T
R
2
n
C
T
S
2
n
R
T
S
2
n
D
S
R
2
T
X
D
2
R
X
D
2
n
D
C
D
2
n
R
I
2
n
D
C
D
1
n
R
I
1
n
D
T
R
1
n
C
T
S
1
n
R
T
S
1
n
D
S
R
1
T
X
D
1
R
X
D
1
n
S
T
B
n
A
L
F
n
E
R
R
O
R
n
I
N
I
T
n
S
L
C
T
I
N
V
C
C
P
D
0
P
D
1
P
D
2
P
D
3
P
D
4
P
D
5
P
D
6
P
D
7
G
N
D
n
A
C
K
B
U
S
Y
P
E
S
L
C
T
V
C
C
X
T
A
L
2
G
N
D
X
T
A
L
1
V
B
A
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
1
6
0
1
5
9
1
5
8
1
5
7
1
5
6
1
5
5
1
5
4
1
5
3
1
5
2
1
5
1
1
5
0
1
4
9
1
4
8
1
4
7
1
4
6
1
4
5
1
4
4
1
4
3
1
4
2
1
4
1
1
4
0
1
3
9
1
3
8
1
3
7
1
3
6
1
3
5
1
3
4
1
3
3
1
3
2
1
3
1
1
3
0
1
2
9
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
FDC37C93xFR
160 Pin QFP
S
A
0
S
A
1
S
A
2
S
A
3
S
A
4
S
A
5
S
A
6
S
A
7
S
A
8
S
A
9
S
A
1
0
S
A
1
1
n
C
S
/
S
A
1
2
I
R
Q
1
5
I
R
Q
1
4
I
R
Q
1
2
I
R
Q
1
1
I
R
Q
1
0
I
R
Q
9
V
C
C
I
R
Q
8
/
n
I
R
Q
8
I
R
Q
7
I
R
Q
6
I
R
Q
5
I
R
Q
4
I
R
Q
3
I
R
Q
1
n
I
O
R
n
I
O
W
A
E
N
G
N
D
S
D
0
S
D
1
S
D
2
S
D
3
S
D
4
S
D
5
S
D
6
S
D
7
R
E
S
E
T
_
D
R
V
5
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
SYMBOL
BUFFER TYPE
PROCESSOR/HOST INTERFACE
72:79
System Data Bus
SD[0:7]
I/O24
41:52
System Address Bus
SA[0:11]
I
53
Chip Select/SA12 (Active Low)(Note 1, 4)
nCS
I
70
Address Enable (DMA master has bus control)
AEN
I
90
I/O Channel Ready
IOCHRDY
OD24
80
Reset Drive
RESET_DRV
IS
67:61,
59:54
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
IRQ[1,3:12,
14,15]
024/OD24
(Note 0)
82,84,
86,88
DMA Requests
DRQ[0:3]
O24
81,83,
85,87
DMA Acknowledge
nDACK[0:3]
I
89
Terminal Count
TC
I
68
I/O Read
nIOR
I
69
I/O Write
nIOW
I
35
High Speed Clock Out 24/48 MHz
HCLK
O20
36
16 MHz Out
16CLK
O8SR
22
14.318 MHz Clock Input
CLOCKI
ICLK
37
14.318 MHz Clock Output 1
CLKO1
O16SR
38
14.318 MHz Clock Output 2
CLKO2
O8SR
39
14.318 MHz Clock Output 3
CLKO3
O8SR
POWER PINS
21, 60,
101, 125,
139
+5V Supply Voltage
VCC
32
Trickle Voltage Input
VTR
1, 8, 40,
71, 95,
123, 130
Ground
GND
FDD INTERFACE
17
Read Disk Data
nRDATA
IS
12
Write Gate
nWGATE
OD48
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