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Электронный компонент: FDC37N958FR

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SMSC DS FDC37N958FR
Rev. 09/01/99
FDC37N958FR
Notebook I/O Controller with Enhanced Keyboard
and System Control
FEATURES
!
5 Volt Operation
!
ACPI 1.0 Compliant
!
PC 99 Compliant
!
Three Power Planes
!
<20
"
A Consumption in Sleep Mode
!
Configuration Register Set Compatible with
ISA Plug-and-Play Standard (Version 1.0a)
!
Serial IRQ meets IRQ Specification for PCI
Systems
-
Quiet (Active) Mode
-
Continuous (Idle) Mode
!
8051 Controller uses Parallel Port to
Reprogram the Flash ROM
!
IR Interface Fully Compliant to IrDA 1.1
(Fast IR)
-
TEMIC/IBM Module Support
-
HP Module Support
-
Sharp Module Support
!
ISA Host Interface
-
16 Bit Address Qualification
-
8 Bit Data bus
-
Zero Wait-State I/O Register Access
-
All Write Only Registers are Shadowed
-
IOCHRDY for ECP and Flash Cycles
-
8 Direct IRQs Including nSMI
-
Four 8 Bit DMA Channels
!
System Flash Interface (256Kx8)
-
8051/Host CPU Multiplexed Interface
- Eight 32K pages - 8051 Keyboard BIOS
-
Four 64K pages - Host System BIOS
!
8051 Keyboard and System Controller
-
Provides System Power Management
-
System Watch Dog Timer (WDT)
-
8042 Style Host Interface
-
Asynchronous Access to Two Data
Registers and One Status Register
-
Supports Interrupt and Polling Access
-
2K Internal ROM, nEA Pin Select
- 32K Bank Switchable External Flash Rom
Interface
-
256 Bytes Data RAM
-
Access to On-Chip Control Registers via
MOVX External Data Access Commands
-
Access to RTC and CMOS Registers
- Up to 16x8 Keyboard Scan Matrix
-
Two 16 Bit Timer/Counter
-
Integrated TX/RX Serial Interface
-
Six 8051 Interrupt Sources
-
Sixteen 8 Bit, Host/8051 Mailbox
Registers
-
19 Maskable Hardware Wake-Up Events
Supported
-
Fast GATEA20
-
Fast CPU_RESET
-
Multiple Clock Sources and Frequencies
-
IDLE and SLEEP Modes
!
Real Time Clock
-
MC146818 and DS1287 Compatible
-
256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
-
128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
-
12 and 24 Hour Time Format
-
Binary and BCD Format
-
<1
"
A Standby Current (typ)
!
ACCESS.bus
Interface
-
8584 Style Interface
!
PS/2
Ports
SMSC DS FDC37N958FR
Rev. 09/01/99
- Four Independent Hardware Driven Ports
!
General Purpose I/O
-
22 I/O Pins
-
12 Out Pins
-
8 In Pins
!
Two Pulse Width Modulators
-
Independent Clock Rates
-
7 Bit Duty Cycle Granularity
!
Intelligent Auto Power Management
!
2.88MB Super I/O Floppy Disk Controller
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
4 DMA Options
-
Open Drain / Push-Pull Configurable
Output Drivers
-
Licensed CMOS 765B Floppy Disk
Controller
-
Advanced Digital Data Separator
-
Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
-
Supports Two Floppy Drives Directly
-
24 mA AT Bus Drivers
-
Low Power CMOS Design
!
Floppy Disk Interface on Parallel Port
!
Licensed CMOS 765B Floppy Disk Controller
Core
-
Supports Vertical Recording Format
-
16 Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun
Conditions
-
48 mA Drivers and Schmitt Trigger Inputs
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
!
Enhanced Digital Data Separator
-
Low Cost Implementation
-
No Filter Components Required
-
2 Mbps, 1 Mbps, 500 Kbps, 300
Kbps, 250 Kbps Data Rates
-
Programmable Precompensation Modes
!
Multi-Mode
#
Parallel Port with ChiProtect
#
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
4 DMA Options
-
Enhanced Mode
-
Standard Mode:
-
IBM PC/XT
, PC/AT
, and PS/2
#
Compatible Bidirectional Parallel Port
-
Enhanced Parallel Port (EPP)
Compatible
- EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)
-
High Speed Mode
-
Microsoft and Hewlett Packard
Extended Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
-
Incorporates ChiProtect
#
Circuitry for
Protection Against Damage Due to
Printer Power-On
-
12 mA Output Drivers
!
Serial
Ports
-
Relocatable to 480 Different Addresses
-
13 IRQ Options
-
Two High Speed NS16C550A
Compatible UARTs with Send/Receive 16
Byte FIFOs
-
Programmable Baud Rate Generator
-
Modem Control Circuitry Including 230K
and 460K Baud
-
IrDA, HP-SIR, ASK-IR Support
IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation.
SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems
Corporation
ORDERING INFORMATION
Order Number: FDC37N958FRTQFP
208 Pin QFP/TQFP Package Options
SMSC DS FDC37N958FR
Rev. 09/01/99
TABLE OF CONTENTS
GENERAL DESCRIPTION ...................................................................................................................... 1
PIN CONFIGURATION ............................................................................................................................ 2
DESCRIPTION OF PIN FUNCTIONS ...................................................................................................... 3
ALTERNATE FUNCTION PIN LIST ...................................................................................................... 10
BUFFER TYPE DESCRIPTIONS .......................................................................................................... 12
FUNCTIONAL DESCRIPTION............................................................................................................... 13
AUTO POWER MANAGEMENT............................................................................................................ 17
FLOPPY DISK CONTROLLER ............................................................................................................. 23
FDC INSTRUCTION SET ...................................................................................................................... 50
FDC DATA TRANSFER COMMANDS .................................................................................................. 62
FDC CONTROL COMMANDS............................................................................................................... 71
COMPATIBILITY ................................................................................................................................... 77
SERIAL PORT (UART).......................................................................................................................... 80
REGISTER DESCRIPTION ................................................................................................................... 80
PROGRAMMABLE BAUD RATE GENERATOR .................................................................................. 89
FIFO INTERRUPT MODE OPERATION................................................................................................ 91
FIFO POLLED MODE OPERATION...................................................................................................... 91
NOTES ON SERIAL PORT FIFO MODE OPERATION ........................................................................ 96
INFRARED COMMUNICATIONS CONTROLLER (IRCC) .................................................................... 98
IRRX/IRTX PIN ENABLE....................................................................................................................... 99
IR REGISTERS - LOGICAL DEVICE 5 ............................................................................................... 100
IR DMA CHANNELS............................................................................................................................ 101
SMSC DS FDC37N958FR
Rev. 09/01/99
IR IRQS................................................................................................................................................ 101
PARALLEL PORT ............................................................................................................................... 102
PARALLEL PORT INTERFACE MULTIPLEXOR ............................................................................... 124
HOST (LEGACY) PARALLEL PORT INTERFACE (FDC37N958FR STANDARD)............................ 125
PARALLEL PORT FDC INTERFACE ................................................................................................. 125
PARALLEL PORT - 8051 CONTROL (FDC37N958FR STANDARD) ................................................ 126
8051 EMBEDDED CONTROLLER...................................................................................................... 127
FEATURES.......................................................................................................................................... 127
8051 FUNCTIONAL OVERVIEW......................................................................................................... 127
8051 MEMORY MAP ........................................................................................................................... 131
8051 CONTROL REGISTERS............................................................................................................. 136
WATCH DOG TIMER........................................................................................................................... 151
SHARED FLASH INTERFACE............................................................................................................ 153
8051 SYSTEM POWER MANAGEMENT ............................................................................................ 158
KEYBOARD CONTROLLER ............................................................................................................... 168
MAILBOX REGISTER INTERFACE .................................................................................................... 181
PS/2 INTERFACE DESCRIPTION....................................................................................................... 184
ACCESS.BUS INTERFACE DESCRIPTION ....................................................................................... 185
LED CONTROLS................................................................................................................................. 189
PULSE WIDTH MODULATORS.......................................................................................................... 190
REAL TIME CLOCK CMOS ACCESS................................................................................................. 190
8051 CONTROLLED PARALLEL PORT ............................................................................................ 193
8051 CONTROLLED IR PORT............................................................................................................ 196
SMSC DS FDC37N958FR
Rev. 09/01/99
GENERAL PURPOSE I/O (GPIO) ....................................................................................................... 197
MULTIPLEXED PINS .......................................................................................................................... 203
REAL TIME CLOCK ............................................................................................................................ 209
VCC1 POR........................................................................................................................................... 211
INTERNAL REGISTERS ..................................................................................................................... 212
TIME CALENDAR AND ALARM ......................................................................................................... 213
UPDATE CYCLE ................................................................................................................................. 214
CONTROL AND STATUS REGISTERS.............................................................................................. 215
INTERRUPTS ...................................................................................................................................... 220
FREQUENCY DIVIDER ....................................................................................................................... 220
PERIODIC INTERRUPT SELECTION ................................................................................................. 220
POWER MANAGEMENT..................................................................................................................... 221
ACCESS.BUS...................................................................................................................................... 222
BACKGROUND ................................................................................................................................... 222
REGISTER DESCRIPTION ................................................................................................................. 223
PS/2 DEVICE INTERFACE.................................................................................................................. 229
PS/2 LOGIC OVERVIEW..................................................................................................................... 229
SERIAL INTERRUPTS ........................................................................................................................ 233
FDC37N958FR CONFIGURATION ..................................................................................................... 238
CONFIGURATION ELEMENTS........................................................................................................... 238
TYPICAL SEQUENCE OF CONFIGURATION OPERATION.............................................................. 239
CONFIGURATION REGISTERS ......................................................................................................... 241
OPEN MODE REGISTERS.................................................................................................................. 266