SMSC DS LPC47M112
Rev. 02/02/2005
DATASHEET
LPC47M112
Enhanced Super I/O Controller with LPC Interface
FEATURES
3.3 Volt Operation (5 Volt Tolerant)
LPC
Interface
ACPI 1.0 Compliant
Fan
Control
-
Fan Speed Control Outputs
-
Fan Tachometer Inputs
Programmable Wake-up Event Interface
PC98, PC99 Compliant
Dual Game Port Interface
MPU-401 MIDI Support
General Purpose Input/Output Pins
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
System Management Interrupt
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core
-
Supports Two Floppy Drives Directly
- Configurable Open Drain/Push-Pull Output
Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, Up to Eight IRQ and Three DMA
Options
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates
-
Programmable Precompensation Modes
Keyboard
Controller
- 8042
Software
Compatible
-
8 Bit Microcomputer
-
2k Bytes of Program ROM
256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
-
Asynchronous Access to Two Data Registers
and One Status Register
-
Supports Interrupt and Polling Access
-
8 Bit Counter Timer
-
Port 92 Support
-
Fast Gate A20 and KRESET Outputs
Serial
Ports
-
Two Full Function Serial Ports
- High Speed NS16C550 Compatible UARTs
with Send/Receive 16-Byte FIFOs
-
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
-
480 Address and 15 IRQ Options
Infrared
Port
-
Multiprotocol Infrared Interface
-
IrDA 1.0 Compliant
-
SHARP ASK IR
-
480 Addresses, Up to 15 IRQ
Multi-Mode Parallel Port with ChiProtect
-
Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bidirectional Parallel Port
- Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
-
IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
-
ChiProtect Circuitry for Protection
-
480 Address, Up to 15 IRQ and Three DMA
Options
LPC
Interface
-
Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
- PME
Interface
100 Pin QFP package in a 3.2 mm format; green,
lead-free package also available
ORDERING INFORMATION
Order Number(s):
LPC47M112-MC for 100 pin QFP package
LPC47M112-MW for 100 pin QFP package (green, lead-free)
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS LPC47M112
Page 3
Rev. 02/02/2005
DATASHEET
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2005. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
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OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS LPC47M112
Page 4
Rev. 02/02/2005
DATASHEET
Table of Contents
1
General Description .............................................................................................. 8
2
PIN CONFIGURATION ........................................................................................... 9
3
DESCRIPTION OF PIN FUNCTIONS ................................................................... 10
3.1
Buffer Type Descriptions................................................................................................................................14
3.2
Pins That Require External Pullup Resistors................................................................................................14
4
BLOCK DIAGRAM ............................................................................................... 15
5
REFERENCE DOCUMENTS ................................................................................ 16
6
3 VOLT OPERATION / 5 VOLT TOLERANCE..................................................... 17
7
POWER FUNCTIONALITY................................................................................... 18
7.1
VCC Power .......................................................................................................................................................18
7.2
VTR Support ....................................................................................................................................................18
7.3
Internal PWRGOOD .........................................................................................................................................18
7.4
32.768 kHz Trickle Clock Input .......................................................................................................................18
7.5
Indication of 32kHz Clock ...............................................................................................................................18
7.6
Trickle Power Functionality............................................................................................................................19
7.7
VREF Pin ..........................................................................................................................................................20
7.8
Maximum Current Values ...............................................................................................................................20
7.9
Power Management Events (PME/SCI) ..........................................................................................................20
8
FUNCTIONAL DESCRIPTION ............................................................................. 21
8.1
Super I/O Registers .........................................................................................................................................21
8.2
Host Processor Interface (LPC) .....................................................................................................................21
8.3
LPC INTERFACE..............................................................................................................................................21
8.3.1
LPC Interface Signal Definition.........................................................................................................................................21
8.3.2
LPC Cycles .......................................................................................................................................................................22
8.3.3
Field Definitions ................................................................................................................................................................22
8.4
Power Management.........................................................................................................................................23
8.4.1
CLOCKRUN Protocol .......................................................................................................................................................23
8.4.2
Typical Usage ...................................................................................................................................................................23
8.4.3
SYNC Timeout..................................................................................................................................................................23
8.4.4
SYNC Patterns and Maximum Number of SYNCS...........................................................................................................23
8.4.5
SYNC Error Indication ......................................................................................................................................................23
8.5
LPC Transfer Sequence Examples ................................................................................................................25
8.5.1
Wait State Requirements..................................................................................................................................................25
9
FLOPPY DISK CONTROLLER ............................................................................ 26
9.1
FDC Internal Registers....................................................................................................................................26
10 COMMAND SET/DESCRIPTIONS ....................................................................... 42
11 INSTRUCTION SET.............................................................................................. 45
12 SERIAL PORT (UART)......................................................................................... 64
13 Serial Data............................................................................................................ 68
14 INFRARED INTERFACE ...................................................................................... 77
15 MPU-401 MIDI UART............................................................................................ 78
15.1
Overview.......................................................................................................................................................78
15.2
Host Interface...............................................................................................................................................78
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS LPC47M112
Page 4
Rev. 02/02/2005
DATASHEET
ADDRESS.........................................................................................................................................................................................79
16 Status Port ........................................................................................................... 80
17 Bits[5:0]................................................................................................................ 81
17.1
MPU-401 Command Controller ...................................................................................................................82
17.2
MIDI UART ....................................................................................................................................................83
17.3
MPU-401 Configuration Registers..............................................................................................................83
18 PARALLEL PORT ................................................................................................ 84
18.1
IBM XT/AT Compatible, Bi-Directional And Epp Modes ...........................................................................85
18.2
Extended Capabilities Parallel Port............................................................................................................90
19 POWER MANAGEMENT.................................................................................... 102
20 Timing Diagrams for SER_IRQ Cycle .............................................................. 105
21 8042 KEYBOARD CONTROLLER DESCRIPTION ........................................... 108
21.1
Latches On Keyboard and Mouse IRQs...................................................................................................114
21.2
Keyboard and Mouse PME Generation ....................................................................................................116
22 GENERAL PURPOSE I/O .................................................................................. 117
22.1
GPIO Pins ...................................................................................................................................................117
22.1.1
GPIO Operation ..............................................................................................................................................................121
PME ................................................................................................................................................................................................123
22.2
Either Edge Triggered Interrupts..............................................................................................................123
22.3
Led Functionality .......................................................................................................................................123
23 SYSTEM MANAGEMENT INTERRUPT (SMI) ................................................... 125
24 PME SUPPORT .................................................................................................. 126
24.1
`Wake On Specific Key' Option.................................................................................................................127
25 FAN SPEED CONTROL AND MONITORING .................................................... 129
25.1
Fan Speed Control.....................................................................................................................................129
25.1.1
FANx Registers...............................................................................................................................................................129
25.1.2
Fan Control Register.......................................................................................................................................................130
25.2
Fan Tachometer Inputs .............................................................................................................................130
PRELOAD.......................................................................................................................................................................................132
26 SECURITY FEATURE ........................................................................................ 133
26.1
GPIO Device Disable Register Control.....................................................................................................133
26.2
Device Disable Register ............................................................................................................................133
27 GAME PORT LOGIC .......................................................................................... 134
27.1
Power Control Register .............................................................................................................................135
27.2
VREF Pin.....................................................................................................................................................135
28 RUNTIME REGISTERS ...................................................................................... 136
29 CONFIGURATION.............................................................................................. 160
30 OPERATIONAL DESCRIPTION......................................................................... 178
30.1
Maximum Guaranteed Ratings*................................................................................................................178
DC ELECTRICAL CHARACTERISTICS ...................................................................................................................178
31 TIMING DIAGRAMS ........................................................................................... 181
32 PACKAGE OUTLINE.......................................................................................... 205
33 APPENDIX - TEST MODE.................................................................................. 206
33.1
Board Test Mode........................................................................................................................................206
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS LPC47M112
Page 5
Rev. 02/02/2005
DATASHEET
List of Figures
FIGURE 1 - LPC47M112 BLOCK DIAGRAM...............................................................................................................15
FIGURE 2 - MPU-401 MIDI INTERFACE ....................................................................................................................78
FIGURE 3 - MPU-401 INTERRUPT.............................................................................................................................81
FIGURE 4 - MIDI DATA BYTE EXAMPLE ...................................................................................................................83
FIGURE 5 KEYBOARD LATCH..............................................................................................................................115
FIGURE 6 MOUSE LATCH.....................................................................................................................................115
FIGURE 7 -GPIO FUNCTION ILLUSTRATION .........................................................................................................121
FIGURE 8 - POWER-UP TIMING ..............................................................................................................................182
FIGURE 9A - INPUT CLOCK TIMING .......................................................................................................................182
FIGURE 10 - OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS......................................................184
FIGURE 11 INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.......................................................184
FIGURE 12 I/O WRITE ...........................................................................................................................................185
FIGURE 13 I/O READ.............................................................................................................................................185
FIGURE 14 DMA REQUEST ASSERTION THROUGH NLDRQ ............................................................................186
FIGURE 15 DMA WRITE (FIRST BYTE) ................................................................................................................186
FIGURE 16 DMA READ (FIRST BYTE)..................................................................................................................186
FIGURE 17 FLOPPY DISK DRIVE TIMING (AT MODE ONLY) .............................................................................187
FIGURE 18 EPP 1.9 DATA OR ADDRESS WRITE CYCLE ...................................................................................188
FIGURE 19 EPP 1.9 DATA OR ADDRESS READ CYCLE ....................................................................................189
FIGURE 20 EPP 1.7 DATA OR ADDRESS WRITE CYCLE ...................................................................................190
FIGURE 21 EPP 1.7 DATA OR ADDRESS READ CYCLE ....................................................................................191
FIGURE 22 - PARALLEL PORT FIFO TIMING...........................................................................................................193
FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING ........................................................................................194
FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING..........................................................................................195
FIGURE 25 - IRDA RECEIVE TIMING.......................................................................................................................196
FIGURE 26 - IRDA TRANSMIT TIMING ....................................................................................................................197
FIGURE 27 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING..............................................................................198
FIGURE 28 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ...........................................................................199
FIGURE 29 SETUP AND HOLD TIME....................................................................................................................200
FIGURE 30 SERIAL PORT DATA ..........................................................................................................................200
FIGURE 31 JOYSTICK POSITION SIGNAL...........................................................................................................201
FIGURE 32 JOYSTICK BUTTON SIGNAL .............................................................................................................201
FIGURE 33 KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .......................................................................202
FIGURE 34 MIDI DATA BYTE .................................................................................................................................203
FIGURE 35 FAN OUTPUT TIMING ........................................................................................................................203
FIGURE 36 FAN TACHOMETER INPUT TIMING ..................................................................................................204
FIGURE 37 LED OUTPUT TIMING ........................................................................................................................204
FIGURE 38 - 100 PIN 14X20MM QFP PACKAGE OUTLINE, 3.2 MM FOOTPRINT.................................................205
FIGURE 39 - XNOR-CHAIN TEST STRUCTURE......................................................................................................206
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