SMSC DS LPC47M14X
Rev. 03/19/2001
128 Pin Enhanced Super I/O Controller
with an LPC Interface and USB Hub
FEATURES
3.3 Volt Operation (5 Volt Tolerant)
LPC Interface
ACPI 1.0 Compliant
Fan Control
-
Fan Speed Control Outputs
-
Fan Tachometer Inputs
Programmable Wake-up Event Interface
PC98, PC99 Compliant
Dual Game Port Interface
MPU-401 MIDI Support
General Purpose Input/Output Pins
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
System Management Interrupt
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk
Controller
- Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core
-
Supports Two Floppy Drives
- Configurable Open Drain/Push-Pull Output
Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
-
100% IBM Compatibility
- Detects All Overrun and Underrun
Conditions
-
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, Up to Eight IRQ and Four DMA
Options
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates
-
Programmable Precompensation Modes
Keyboard Controller
- 8042
Software
Compatible
-
8 Bit Microcomputer
-
2k Bytes of Program ROM
-
256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
- Asynchronous Access to Two Data
Registers and One Status Register
-
Supports Interrupt and Polling Access
-
8 Bit Counter Timer
-
Port 92 Support
-
Fast Gate A20 and KRESET Outputs
Serial Ports
-
Two Full Function Serial Ports
-
High Speed NS16C550A Compatible UARTs
with Send/Receive 16-Byte FIFOs
-
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
-
480 Address and 15 IRQ Options
Infrared Port
-
Multiprotocol Infrared Interface
-
IrDA 1.0 Compliant
-
SHARP ASK IR
-
480 Addresses, Up to 15 IRQ
Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT,
PC/AT, and
PS/2 Compatible Bi-directional Parallel Port
-
Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)
-
IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
-
ChiProtect Circuitry for Protection
-
960 Address, Up to 15 IRQ and Four DMA
Options
LPC47M14x
PRELIMINARY
SMSC DS LPC47M14X
Page 2
Rev. 03/19/2001
USB Hub
-
1 Upstream and up to 4 Downstream Ports
-
Compliant with USB Spec. version 1.1
-
Programmable USB Manufacturer ID,
Product ID and Device Rev. Number
-
Number of active ports programmable or
selectable via jumpers
-
Powered by Vtr for Downstream Port
Wakeup
LPC Interface
- Multiplexed Command, Address and Data
Bus
- Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
- PME
Interface
Interrupt Generating Registers
-
Registers Generate IRQ1 15 on Serial IRQ
Interface
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
ORDERING INFORMATION
Order Number: LPC47M14x NC
128 Pin QFP Package
SMSC DS LPC47M14X
Page 3
Rev. 03/19/2001
GENERAL DESCRIPTION
The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller with an LPC interface and a standalone
USB hub. It is designed to be compatible with a family of Super I/O Controllers (LPC47M13x, LPC47M14x, and
LPC47M15x). To the interested reader, the LPC47M15x offers hardware monitoring capabilities. The first one
hundred pins of all these packages are completely pin compatible and offer the designer added flexibility in their
board designs. In addition, any board designed to support the LPC47M14x will automatically offer the dual capability
of supporting the LPC47M13x, as well.
The LPC47M14x implements the LPC interface, a pin reduced ISA bus interface which provides the same or better
performance as the ISA/X-bus with a substantial savings in pins used. This interface makes use of the PCI clock,
which runs at 33MHz instead of the traditional 8MHz for the ISA bus, that eases some complications found in
synchronous designs. In addition, all legacy drivers used for Super I/O components are still supported making this
new interface transparent to the supporting software. The LPC bus also supports power management, such as
wake-up and sleep modes, in the same way as the PCI bus.
The LPC47M14X incorporates a standalone USB Hub, implementing one upstream port and up to four (4)
downstream ports, with an internal data path connection for programming the USB Vendor ID, Product ID and Device
Revision Number. The number of active downstream ports is also programmable or selectable with external jumpers.
This programming is done by BIOS accessing the hub control registers.
The LPC47M14x has incorporated the following Super I/O components: a parallel port that is compatible with IBM
PC/AT architecture, as well as the IEEE 1284 EPP and ECP; two serial ports that are 16C550A UART compatible; a
keyboard/mouse controller that uses an 8042 microcontroller; two floppy controllers, which use SMSC's true CMOS
765B core; two infrared ports that are IrDA 1.0 compliant; a MIDI interface, which is a MPU-401-compatible; and 37
General Purpose I/O control functions, which offer flexibility to the system designer. The true CMOS 765B core
provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with
the 82077AA. This chip also controls two LED's, a dual game port interface, and the speed of two fans with fan
tachometer inputs through the use of a pulse width modulation scheme.
The LPC47M14x is ACPI 1.0 compatible and therefore supports multiple low power-down modes. It incorporates
sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events.
The LPC47M14X supports the ISA Plug-and-Play Standard (Version 1.0a). The I/O Address, DMA Channel and
hardware IRQ of each logical device in the LPC47M14X may be reprogrammed through the internal configuration
registers. There are 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and four
DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on
the Serial IRQ Interface.
The LPC47M14X does not require any external filter components and is therefore easy to use and offers lower
system costs and reduced board area.
* The "x" in the part number is a designator that changes depending upon the particular BIOS used inside the specific
chip.
SMSC DS LPC47M14X
Page 4
Rev. 03/19/2001
TABLE OF CONTENTS
1 PIN
LAYOUT ..........................................................................................................................................................8
2 PIN
CONFIGURATION...........................................................................................................................................9
3 DESCRIPTION
OF PIN FUNCTIONS...................................................................................................................10
3.1 B
UFFER
T
YPE
D
ESCRIPTIONS
...........................................................................................................................14
3.2 P
INS
T
HAT
R
EQUIRE
E
XTERNAL
P
ULLUP
R
ESISTORS
..........................................................................................15
4 BLOCK
DIAGRAM ...............................................................................................................................................16
5 POWER
FUNCTIONALITY...................................................................................................................................17
5.1 VCC
P
OWER
..................................................................................................................................................17
5.1.1
3 Volt Operation / 5 Volt Tolerance.........................................................................................................17
5.2 USB
P
OWER
..................................................................................................................................................17
5.3 VTR
S
UPPORT
...............................................................................................................................................17
5.4 VREF
P
IN
.....................................................................................................................................................17
5.5 I
NTERNAL
PWRGOOD ...................................................................................................................................18
5.6 32.768
K
H
Z
T
RICKLE
C
LOCK
I
NPUT
..................................................................................................................18
5.7 T
RICKLE
P
OWER
F
UNCTIONALITY
......................................................................................................................18
5.8 M
AXIMUM
C
URRENT
V
ALUES
............................................................................................................................19
5.9 P
OWER
M
ANAGEMENT
E
VENTS
(PME/SCI) ......................................................................................................19
6 FUNCTIONAL
DESCRIPTION .............................................................................................................................20
6.1 S
UPER
I/O R
EGISTERS
....................................................................................................................................20
6.2 H
OST
P
ROCESSOR
I
NTERFACE
(LPC) ...............................................................................................................20
6.3 LPC
I
NTERFACE
.............................................................................................................................................21
6.3.1 LPC
Interface
Signal Definition...............................................................................................................21
6.3.2 LPC
Cycles.............................................................................................................................................21
6.3.3 Field
Definitions ......................................................................................................................................21
6.3.4 LFRAME# Usage....................................................................................................................................21
6.3.5
I/O Read and Write Cycles .....................................................................................................................22
6.3.6
DMA Read and Write Cycles ..................................................................................................................22
6.3.7 DMA
Protocol .........................................................................................................................................22
6.3.8 Power
Management................................................................................................................................22
6.3.9 SYNC
Protocol .......................................................................................................................................22
6.3.10 LPC
Transfer ..........................................................................................................................................23
6.4 USB
H
UB
F
UNCTIONAL
D
ESCRIPTION
...............................................................................................................24
6.4.1 USB
Downstream Port Selection............................................................................................................25
6.5 FLOPPY
DISK
CONTROLLER ....................................................................................................................26
6.5.1 FDC
Internal Registers ...........................................................................................................................27
6.5.2 STATUS
REGISTER ENCODING ..........................................................................................................37
6.5.3 Instruction Set.........................................................................................................................................43
6.5.4 DATA
TRANSFER COMMANDS............................................................................................................50
6.6 SERIAL
PORT (UART) ................................................................................................................................60
6.7 INFRARED
INTERFACE..............................................................................................................................72
6.8 MPU-401
MIDI UART...................................................................................................................................73
6.8.1 Overview.................................................................................................................................................73
6.8.2 Host
Interface .........................................................................................................................................73
6.8.3 MIDI
Data Port........................................................................................................................................74
6.8.4 Status Port..............................................................................................................................................74
6.8.5 MPU-401
Command Controller ..............................................................................................................76
6.8.6 MIDI UART .............................................................................................................................................77
6.8.7 MPU-401
Configuration Registers ..........................................................................................................77
6.9 PARALLEL PORT ........................................................................................................................................78
6.9.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................79
6.9.2 Extended
Capabilities Parallel Port.........................................................................................................84
6.10 POWER
MANAGEMENT .............................................................................................................................94
6.11 SERIAL IRQ .................................................................................................................................................98
6.12 I
NTERRUPT
G
ENERATING
R
EGISTERS
..............................................................................................................101
6.13
8042 KEYBOARD CONTROLLER DESCRIPTION ...................................................................................102
6.13.1 Keyboard Interface ...............................................................................................................................103
6.13.2 External
Keyboard and Mouse Interface...............................................................................................104
6.13.3 Keyboard
Power Management .............................................................................................................104
6.13.4 Interrupts ..............................................................................................................................................104
6.13.5 Memory
Configurations.........................................................................................................................104
6.13.6 Register Definitions...............................................................................................................................105
SMSC DS LPC47M14X
Page 5
Rev. 03/19/2001
6.13.7 External
Clock Signal............................................................................................................................105
6.13.8 Default
Reset Conditions ......................................................................................................................105
6.13.9 Latches On Keyboard and Mouse IRQs ...............................................................................................108
6.13.10 Keyboard and Mouse PME Generation ................................................................................................109
6.14 GENERAL
PURPOSE I/O..........................................................................................................................110
6.14.1 GPIO Pins.............................................................................................................................................110
6.14.2 Description............................................................................................................................................111
6.14.3 GPIO
Control ........................................................................................................................................112
6.14.4 GPIO
Operation....................................................................................................................................112
6.14.5 GPIO PME and SMI Functionality.........................................................................................................113
6.14.6 Either
Edge
Triggered Interrupts...........................................................................................................114
6.14.7 LED
Functionality..................................................................................................................................115
6.15 SYSTEM
MANAGEMENT INTERRUPT (SMI)...........................................................................................115
6.15.1 SMI
Registers .......................................................................................................................................115
6.16 PME
SUPPORT .........................................................................................................................................116
6.16.1 `Wake
on
Specific Key' Option..............................................................................................................117
6.17
FAN SPEED CONTROL AND MONITORING............................................................................................118
6.17.1 Fan
Speed Control................................................................................................................................118
6.17.2 Fan
Tachometer Inputs.........................................................................................................................119
6.18 SECURITY FEATURE ...............................................................................................................................122
6.18.1 GPIO Device Disable Register Control .................................................................................................122
6.18.2 Device
Disable Register .......................................................................................................................122
6.19 GAME
PORT LOGIC..................................................................................................................................122
6.19.1 Power
Control Register.........................................................................................................................124
6.19.2 VREF Pin..............................................................................................................................................124
7 RUNTIME
REGISTERS......................................................................................................................................125
8 CONFIGURATION..............................................................................................................................................152
9 OPERATIONAL
DESCRIPTION ........................................................................................................................172
9.1 M
AXIMUM
G
UARANTEED
R
ATINGS
...................................................................................................................172
9.2 DC
E
LECTRICAL
C
HARACTERISTICS
................................................................................................................172
10 TIMING
DIAGRAMS...........................................................................................................................................177
11 PACKAGE
OUTLINE .........................................................................................................................................200
12 APPENDIX
-
TEST MODE..................................................................................................................................201
12.1 B
OARD
T
EST
M
ODE
.......................................................................................................................................201
12.1.1 XNOR-Chain Test Mode.......................................................................................................................201
13 REFERENCE DOCUMENTS..............................................................................................................................204
14 LPC47M14X
REVISIONS...................................................................................................................................205
TABLES
Table 1 Super I/O Block Addresses ........................................................................................................................20
Table 2 Hub Descriptor to be Modified....................................................................................................................25
Table 3 Status, Data and Control Registers............................................................................................................27
Table 4 Tape Select Bits .........................................................................................................................................30
Table 5 Internal 2 Drive Decode - Normal...............................................................................................................30
Table 6 Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................31
Table 7 Drive Type ID .............................................................................................................................................31
Table 8 Precompensation Delays ...........................................................................................................................32
Table 9 Data Rates .................................................................................................................................................33
Table 10 DRVDEN Mapping ...................................................................................................................................33
Table 11 Default Precompensation Delays .............................................................................................................33
Table 12 FIFO Service Delay ..................................................................................................................................35
Table 13 Status Register 0......................................................................................................................................37
Table 14 Status Register 1......................................................................................................................................38
Table 15 Status Register 2......................................................................................................................................38
Table 16 Status Register 3......................................................................................................................................39
Table 17 Description of Command Symbols ...........................................................................................................41
Table 18 Instruction Set ..........................................................................................................................................43
Table 19 Sector Sizes .............................................................................................................................................50
Table 20 Effects of MT and N Bits...........................................................................................................................51
Table 21 Skip Bit vs Read Data Command.............................................................................................................51
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