SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
LPC47M172
Advanced I/O Controller
with Motherboard GLUE
Logic
Datasheet
Product Features
3.3V Operation (5V tolerant)
LPC Interface
- Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
ACPI 1.0b/2.0 Compliant
Programmable Wake-up Event Interface
PC99a/PC2001 Compliant
General Purpose Input/Output Pins (13)
Fan Tachometer Inputs (2)
Green and Yellow Power LEDs
ISA Plug-and-Play Compatible Register Set
Motherboard GLUE Logic
- 5V Reference Generation
- 5V Standby Reference Generation
- IDE Reset/Buffered PCI Reset Outputs
- Power OK Signal Generation
- Power Sequencing
- Power Supply Turn On Circuitry
- Resume Reset Signal Generation
- Hard Drive Front Panel LED
- Voltage Translation for DDC to VGA Monitor
- SMBus Isolation Circuitry
- CNR Dynamic Down Control
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
- Supports One Floppy Drive
- Configurable Open Drain/Push-Pull Output Drivers
- Supports Vertical Recording Format
16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
480 Address, Up to Eight IRQ and Three DMA
Options
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
- Programmable Precompensation Modes
Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers and
One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
Serial Ports
- Two Full Function Serial Ports
- High Speed 16C550A Compatible UART with
Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
Infrared Port
- Multiprotocol Infrared Interface
- 32-Byte Data FIFO
- IrDA 1.0 Compliant
- SHARP ASK IR
- HP-SIR
- 480 Address, Up to 15 IRQ and Three DMA Options
Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT
,
PC/AT, and PS/2
Compatible Bi-directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Three DMA Options
Interrupt Generating Registers
- Registers Generate IRQ1 IRQ15 on Serial IRQ
Interface.
XOR-Chain Board Test
128 Pin MQFP Package, 3.2 mm Footprint
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 2
SMSC LPC47M172
DATASHEET
ORDERING INFORMATION
Order Number(s):
LPC47M172-NR for 128 MQFP (3.2mm footprint) package
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
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OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 3
SMSC LPC47M172
DATASHEET
LPC47M172 Datasheet Revision History
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY CORRECTION
Rev. 02-27-04
Table 12.2 - S3-S5 Standby Current, page
201
Added note above table.
Rev. 02-27-04
Ordering Information
Added.
Rev. 02-27-04
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Revised heading to include "standard
SMSC" and "non-standard SMSC" register
sets.
Rev. 02-26-04
Chapter 1 - General Description, page 12
Revised General Description adding AMI
TM
BIOS to keyboard interface.
Rev. 02-23-04
Chapter 12 - Electrical Characteristics,
page 196
Lead Temperature Range, lead and lead-
free; reference to spec name J-STD-020B.
Rev. 02-20-04
Section 3.1 - Buffer Name Descriptions,
page 23
Added I0_SW.
Rev. 02-20-04
Table 3.1 - LPC47M172 Pin Description,
page 15
Buffer names revised for pins 87 90,
113 116.
Note 8 under table revised.
Rev. 02-20-04
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Added table.
Rev. 02-20-04
Table 7.31 - Voltage Translation DDC Pins,
page 137
Replaced buffer IOD8 with IO_SW.
Rev. 02-20-04
Figure 7.10 - VGA DDC Voltage
Translation Circuit, page 139
Revised figure.
Rev. 02-20-04
Table 7.34 - SMBus Isolation Pins, page
139
Replaced buffer IOD8 with IO_SW.
First paragraph under table revised.
Rev. 02-20-04
Figure 7.11 - SMBUS Isolation Circuit,
page 140
Revised figure.
Rev. 02-20-04
Table 12.1 - Operational DC
Characteristics, page 196
Added IO_SW buffer and description;
updated parameters for Icc and Itr.
Rev. 02-20-04
Table 7.7 - Programming for Configuration
Register B (Bits 5:3), page 106; Table 7.8 -
Programming for Configuration Register B
(Bits 2:0), page 106
Titles added to tables.
Rev. 02-20-04
Table 11.2 - LPC47M172 Configuration
Register Summary, page 178
Value of TEST 7 reg for LD_NUM=1
changed to 0x01.
Rev. 02-20-04
Table 11.3 - Chip Level Registers, page
180
Definition of TEST 7 value:
Default = 0x00 (when pin 117 is NC), 0x01
(when pin 117 is connected to VTR) on
VCC POR, VTR POR, and HARD RESET
Rev. 02-20-04
Chapter 2 - Pin Layout, page 13
Note for pin 117
Rev. 02-20-04
Table 3.1 - LPC47M172 Pin Description,
page 15
No Connect Pin 117,
Pin 117 described in Note 11.
Rev. 02-20-04
Chapter 8 Power Control Runtime
Registers, page 151
Table added.
Rev. 02-20-04
Chapter 9 GPIO Runtime Registers, page
158
Table added.
Rev. 02-20-04
Chapter 10 Runtime Register Block
Runtime Registers, page 162
Added paragraph describing runtime
registers tables.
Rev. 02-20-04
Table 11.3 - Chip Level Registers, page
180
Register 0x29
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 4
SMSC LPC47M172
DATASHEET
Table Of Contents
LPC47M172 Datasheet Revision History ................................................................................................. 3
Chapter 1
General Description.............................................................................................................. 12
Chapter 2
Pin Layout ............................................................................................................................ 13
Chapter 3
Description of Pin Functions ................................................................................................ 15
3.1
Buffer Name Descriptions ..........................................................................................................................23
3.2
Pins With Internal Resistors .......................................................................................................................24
3.3
Pins That Require External Resistors.........................................................................................................24
3.4
Default State of Pins...................................................................................................................................25
Chapter 4
Block Diagram ...................................................................................................................... 29
Chapter 5
Power and Clock Functionality............................................................................................. 30
5.1
3 Volt Operation / 5 Volt Tolerance ............................................................................................................30
5.2
VCC Power ................................................................................................................................................30
5.3
VTR Power.................................................................................................................................................30
5.3.1
Trickle Power Functionality .................................................................................................................31
5.4
V5P0_STBY Power ....................................................................................................................................31
5.5
32.768 kHz Trickle Clock Input...................................................................................................................31
5.5.1
Indication of 32KHZ Clock...................................................................................................................31
5.6
14.318 MHz Clock Input .............................................................................................................................32
5.7
Internal PWRGOOD...................................................................................................................................32
5.8
Maximum Current Values...........................................................................................................................32
5.9
Power Management Events (PME/SCI) .....................................................................................................32
Chapter 6
Functional Description.......................................................................................................... 33
6.1
Super I/O Registers....................................................................................................................................33
6.2
Host Processor Interface (LPC) .................................................................................................................34
6.3
LPC Interface .............................................................................................................................................34
6.3.1
LPC Interface Signal Definition ...........................................................................................................34
6.3.2
LPC Cycles .........................................................................................................................................34
6.3.3
Field Definitions...................................................................................................................................34
6.3.4
NLFRAME Usage................................................................................................................................35
6.3.5
I/O Read and Write Cycles..................................................................................................................35
6.3.6
DMA Read and Write Cycles ..............................................................................................................35
6.3.7
DMA Protocol ......................................................................................................................................35
6.3.8
Power Management ............................................................................................................................36
6.3.9
SYNC Protocol ....................................................................................................................................36
6.3.10
I/O and DMA START Fields.............................................................................................................37
6.3.11
LPC Transfers .................................................................................................................................37
6.4
Floppy Disk Controller ................................................................................................................................38
6.4.1
FDC Configuration Registers ..............................................................................................................38
6.4.2
FDC Internal Registers........................................................................................................................38
6.4.3
Status Register A (SRA) .....................................................................................................................39
6.4.4
Status Register B (SRB) .....................................................................................................................40
6.4.5
Digital Output Register (DOR).............................................................................................................42
6.4.6
Tape Drive Register (TDR) .................................................................................................................43
6.4.7
Data Rate Select Register (DSR)........................................................................................................44
6.4.8
Main Status Register...........................................................................................................................46
6.4.9
Data Register (FIFO)...........................................................................................................................47
6.4.10
Digital Input Register (DIR)..............................................................................................................48
6.4.11
Configuration Control Register (CCR) .............................................................................................49
6.4.12
Status Register Encoding ................................................................................................................50
6.5
Modes of Operation....................................................................................................................................52
6.5.1
PC/AT Mode .......................................................................................................................................52
6.5.2
PS/2 Mode ..........................................................................................................................................52
6.5.3
Model 30 Mode ...................................................................................................................................52
6.6
DMA Transfers ...........................................................................................................................................52
6.7
Controller Phases.......................................................................................................................................53
6.7.1
Command Phase ................................................................................................................................53
6.7.2
Execution Phase .................................................................................................................................53
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 5
SMSC LPC47M172
DATASHEET
6.8
Data Transfer Termination .........................................................................................................................54
6.9
Result Phase..............................................................................................................................................54
6.10
Command Set/Descriptions ....................................................................................................................54
6.10.1
Instruction Set..................................................................................................................................57
6.11
Data Transfer Commands ......................................................................................................................63
6.11.1
Read Data .......................................................................................................................................63
6.12
Read Deleted Data .................................................................................................................................64
6.13
Read A Track..........................................................................................................................................65
6.14
Write Data...............................................................................................................................................66
6.15
Write Deleted Data .................................................................................................................................66
6.16
Verify ......................................................................................................................................................66
6.17
Format A Track .......................................................................................................................................67
6.18
Control Commands.................................................................................................................................69
6.18.1
Read ID ...........................................................................................................................................69
6.18.2
Recalibrate ......................................................................................................................................69
6.18.3
Seek ................................................................................................................................................69
6.19
Sense Interrupt Status ............................................................................................................................70
6.20
Sense Drive Status .................................................................................................................................71
6.21
Specify....................................................................................................................................................71
6.22
Configure ................................................................................................................................................71
6.22.1
Configure Default Values.................................................................................................................71
6.23
Version ...................................................................................................................................................72
6.24
Relative Seek .........................................................................................................................................72
6.25
Perpendicular Mode................................................................................................................................73
6.26
Lock ........................................................................................................................................................74
6.27
Enhanced DUMPREG ............................................................................................................................75
6.27.1
Compatibility ....................................................................................................................................75
6.28
Serial Port (UART)..................................................................................................................................75
6.28.1
Register Description ........................................................................................................................75
6.28.2
Receive Buffer Register (RB) ..........................................................................................................76
6.28.3
Transmit Buffer Register (TB)..........................................................................................................76
6.28.4
Interrupt Enable Register (IER) .......................................................................................................76
6.28.5
FIFO Control Register (FCR)...........................................................................................................77
6.28.6
Interrupt Identification Register (IIR)................................................................................................77
6.28.7
Line Control Register (LCR) ............................................................................................................79
6.28.8
Modem Control Register (MCR) ......................................................................................................80
6.28.9
Line Status Register (LSR) ..............................................................................................................81
6.28.10
Modem Status Register (MSR)........................................................................................................82
6.28.11
Scratchpad Register (SCR) .............................................................................................................83
6.29
Programmable Baud Rate Generator (And Divisor Latches DLH, DLL) .................................................83
6.29.1
Effect Of The Reset on Register File ...............................................................................................84
6.29.2
FIFO Interrupt Mode Operation .......................................................................................................84
6.29.3
FIFO Polled Mode Operation...........................................................................................................85
Chapter 7
Notes On Serial Port Operation ........................................................................................... 89
7.1
FIFO Mode Operation: ...............................................................................................................................89
7.1.1
General ...............................................................................................................................................89
7.1.2
TX and RX FIFO Operation.................................................................................................................89
7.2
Infrared Interface........................................................................................................................................90
7.3
Parallel Port................................................................................................................................................90
7.4
IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................92
7.4.1
Data Port.............................................................................................................................................92
7.4.2
Status Port ..........................................................................................................................................92
7.4.3
Control Port.........................................................................................................................................93
7.4.4
EPP Address Port ...............................................................................................................................94
7.4.5
EPP Data Port 0..................................................................................................................................94
7.4.6
EPP Data Port 1..................................................................................................................................94
7.4.7
EPP Data Port 2..................................................................................................................................94
7.4.8
EPP Data Port 3..................................................................................................................................95
7.5
EPP 1.9 Operation .....................................................................................................................................95
7.5.1
Software Constraints...........................................................................................................................95
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