SMSC DS LPC47N237
Revision 0.3 (10-26-04)
DATASHEET
LPC47N237
3.3v I/O Controller for
Port Replicators and
Docking Stations
Datasheet
Product Features
3.3 Volt Operation (5V Tolerant)
32 SMBus-Hosted General Purpose Input/Output
Pins
- SMBus Slave Controller Enables Read/Write Access
to GPIO Ports
- SMBus Runs on and GPIO Pins are Driven by
Suspend Supply (VTR)
- SMBus Interrupt Pin
- SMBus Isolation Circuitry
PC99a/PC2001
Compliant
ACPI 1.0/2.0 Compliant
Power Management Interface
LPC
Interface
- Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
- nIO_PME pin for UART Ring Indicate
- PCI Clock Run Support
4 LPC-Hosted General Purpose Input/Output
Pins
Serial
Port
- Full Function Serial Port
- High Speed 16C550A Compatible UART with
16-Byte Send/Receive FIFOs
- Programmable Baud Rate Generator supports 230k
and 460k Baud
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
- Ring Indicator Wakeup Event
Multi-ModeTM Parallel Port with ChiProtectTM
- Standard Mode IBM PC/XT, PC/AT, and PS/2TM
Compatible Bidirectional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
- ChiProtect Circuitry for Protection
- 480 Address, Up to 15 IRQ and Three DMA Options
XNOR-Chain
100 pin TQFP package; green, lead-free package
also available
3.3v I/O Controller for Port Replicators and Docking Stations
Revision 0.3 (10-26-04)
Page 2
SMSC DS LPC47N237
DATASHEET
ORDERING INFORMATION
Order Number(s):
LPC47N237-MD for 100 pin TQFP package
LPC47N237-MT for 100 pin TQFP package (green, lead-free)
80 Arkay Drive
Hauppauge, NY 11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
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NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS LPC47N237
Page 3
Revision 0.3 (10-26-04)
DATASHEET
TABLE OF CONTENTS
Chapter 1
General Description ........................................................................................................... 10
Chapter 2
Pin Configuration............................................................................................................... 11
Chapter 3
Pin Layout........................................................................................................................... 12
Chapter 4
Description of Pin Functions ............................................................................................. 13
4.1
Buffer Name Description ................................................................................................................... 18
4.2
Pins That Require External Resistors ............................................................................................... 19
Chapter 5
Block Diagram.................................................................................................................... 20
Chapter 6
Power/Clock Functionality................................................................................................ 21
6.1
3.3 Volt Operation / 5 Volt Tolerance ................................................................................................ 21
6.2
VCC Power........................................................................................................................................ 21
6.3
VTR Power ........................................................................................................................................ 21
6.3.1
Trickle Power Functionality .....................................................................................................................22
6.4
24 MHz Crystal.................................................................................................................................. 22
6.5
24 MHz Output .................................................................................................................................. 22
6.6
Internal PWRGOOD .......................................................................................................................... 22
6.7
Maximum Current Values.................................................................................................................. 23
6.8
Power Management Events (PME/SCI)............................................................................................ 23
Chapter 7
Functional Description....................................................................................................... 24
7.1
Super I/O Registers........................................................................................................................... 24
7.2
Host Processor Communication........................................................................................................ 24
7.3
LPC Interface .................................................................................................................................... 24
7.3.1
LPC Interface Signal Definition ...............................................................................................................25
LPC Cycles........................................................................................................................................................25
Field Definitions.................................................................................................................................................25
nLFRAME Usage ..............................................................................................................................................25
I/O Read and Write Cycles ................................................................................................................................26
DMA Read and Write Cycles.............................................................................................................................26
DMA Protocol ....................................................................................................................................................26
7.3.2
Power Management................................................................................................................................26
CLOCKRUN Protocol ........................................................................................................................................26
LPCPD Protocol ................................................................................................................................................26
SYNC Protocol ..................................................................................................................................................27
Typical Usage....................................................................................................................................................27
SYNC Timeout ..................................................................................................................................................27
SYNC Patterns and Maximum Number of SYNCS............................................................................................27
SYNC Error Indication .......................................................................................................................................28
I/O and DMA START Fields ..............................................................................................................................28
Reset Policy ......................................................................................................................................................28
7.3.3
LPC Transfers ........................................................................................................................................28
Wait State Requirements...................................................................................................................................28
Chapter 8
Serial Port (UART) ............................................................................................................ 29
8.1
Register Description.......................................................................................................................... 29
8.1.1
Receive Buffer Register (RB)..................................................................................................................29
8.1.2
Transmit Buffer Register (TB).................................................................................................................30
8.1.3
Interrupt Enable Register (IER)...............................................................................................................30
8.1.4
FIFO Control Register (FCR)..................................................................................................................30
8.1.5
Interrupt Identification Register (IIR) .......................................................................................................31
8.1.6
Line Control Register (LCR)....................................................................................................................33
8.1.7
Modem Control Register (MCR) .............................................................................................................34
8.1.8
Line Status Register (LSR) .....................................................................................................................35
3.3v I/O Controller for Port Replicators and Docking Stations
Revision 0.3 (10-26-04)
Page 4
SMSC DS LPC47N237
DATASHEET
8.1.9
Modem Status Register (MSR) ...............................................................................................................37
8.1.10
Scratchpad Register (SCR).................................................................................................................38
8.2
Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ......................................... 38
8.3
Effect Of The Reset on Register File ................................................................................................ 38
8.4
FIFO Interrupt Mode Operation......................................................................................................... 38
8.5
FIFO Polled Mode Opertion .............................................................................................................. 39
8.6
Notes On Serial Port Operation ........................................................................................................ 42
8.6.1
FIFO Mode Operation.............................................................................................................................42
8.6.2
TX AND RX FIFO Operation...................................................................................................................42
Chapter 9
Parallel Port........................................................................................................................ 44
9.1
IBM XT/AT Compatible, Bi-Directional And EPP Modes .................................................................. 45
9.1.1
Data Port ................................................................................................................................................45
9.1.2
Status Port..............................................................................................................................................45
9.1.3
Control Port ............................................................................................................................................46
9.1.4
EPP Address Port...................................................................................................................................47
9.1.5
EPP Data Port 0 .....................................................................................................................................47
9.1.6
EPP Data Port 1 .....................................................................................................................................48
9.1.7
EPP Data Port 2 .....................................................................................................................................48
9.1.8
EPP Data Port 3 .....................................................................................................................................48
9.2
EPP 1.9 Operation ............................................................................................................................ 48
9.2.1
Software Constraints ..............................................................................................................................48
9.2.2
EPP 1.9 Write .........................................................................................................................................48
9.2.3
EPP 1.9 Read.........................................................................................................................................49
9.3
EPP 1.7 Operation ............................................................................................................................ 50
9.3.1
Software Constraints ..............................................................................................................................50
9.3.2
EPP 1.7 Write .........................................................................................................................................50
9.3.3
EPP 1.7 Read.........................................................................................................................................50
9.4
Extended Capabilities Parallel Port................................................................................................... 51
9.5
Vocabulary ........................................................................................................................................ 51
9.6
ECP Implementation Standard.......................................................................................................... 53
9.6.1
Description..............................................................................................................................................53
9.6.2
Register Definitions.................................................................................................................................54
Data And ecpAFifo Port.....................................................................................................................................55
Device Status Register (DSR) ...........................................................................................................................55
Device Control Register (DCR)..........................................................................................................................56
cFifo (Parallel Port Data FIFO) ..........................................................................................................................57
ecpDFifo (ECP Data FIFO)................................................................................................................................57
tFifo (Test FIFO Mode)......................................................................................................................................57
cnfgA (Configuration Register A) .......................................................................................................................58
cnfgB (Configuration Register B) .......................................................................................................................58
ecr (Extended Control Register) ........................................................................................................................58
9.6.3
Operation................................................................................................................................................61
Mode Switching/Software Control .....................................................................................................................61
ECP Operation ..................................................................................................................................................61
Termination from ECP Mode .............................................................................................................................61
Command/Data .................................................................................................................................................62
Data Compression.............................................................................................................................................62
Pin Definition .....................................................................................................................................................62
LPC Connections...............................................................................................................................................62
Interrupts ...........................................................................................................................................................63
FIFO Operation .................................................................................................................................................63
DMA Transfers ..................................................................................................................................................63
DMA Mode - Transfers from the FIFO to the Host.............................................................................................64
Programmed I/O Mode or Non-DMA Mode .......................................................................................................64
Programmed I/O - Transfers from the FIFO to the Host ....................................................................................64
Programmed I/O - Transfers from the Host to the FIFO ....................................................................................65
Chapter 10
Power Management ........................................................................................................ 66
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS LPC47N237
Page 5
Revision 0.3 (10-26-04)
DATASHEET
10.1
UART Power Management ............................................................................................................ 66
10.1.1
Exit Auto Powerdown ..........................................................................................................................66
10.2
Parallel Port Power Management .................................................................................................. 66
10.2.1
Exit Auto Powerdown ..........................................................................................................................67
Chapter 11
Serial IRQ........................................................................................................................ 68
11.1
Timing Diagrams For SER_IRQ Cycle .......................................................................................... 68
11.1.1
SER_IRQ Cycle Control ......................................................................................................................69
11.1.2
SER_IRQ Data Frame ........................................................................................................................69
11.1.3
Stop Cycle Control ..............................................................................................................................70
11.1.4
Latency................................................................................................................................................70
11.1.5
EOI/ISR Read Latency........................................................................................................................70
11.1.6
AC/DC Specification Issue ..................................................................................................................70
11.1.7
Reset and Initialization ........................................................................................................................71
Chapter 12
PCI CLKRUN Support .................................................................................................. 72
12.1
Overview ........................................................................................................................................ 72
12.2
nCLKRUN for Serial IRQ ............................................................................................................... 72
12.3
nCLKRUN for nLDRQ .................................................................................................................... 72
12.4
Using nCLKRUN ............................................................................................................................ 72
Chapter 13
LPC General Purpose I/O .............................................................................................. 75
13.1
Description ..................................................................................................................................... 75
13.2
GPIO Control.................................................................................................................................. 75
13.3
GPIO Operation ............................................................................................................................. 76
Chapter 14
PME Support................................................................................................................... 78
Chapter 15
SMBus GPIO Block ........................................................................................................ 79
15.1
SMBus Slave Controller................................................................................................................. 79
15.1.1
SMBus Pins.........................................................................................................................................79
15.1.2
Bus Protocols ......................................................................................................................................80
Write Byte..........................................................................................................................................................80
Read Byte..........................................................................................................................................................80
15.1.3
Slave Address .....................................................................................................................................80
15.1.4
Invalid Protocol Response Behavior....................................................................................................81
15.1.5
General Call Address Response .........................................................................................................81
15.1.6
Slave Device Time-Out .......................................................................................................................81
15.1.7
Stretching the SCLK Signal.................................................................................................................81
15.1.8
SMBus Timing.....................................................................................................................................81
15.1.9
Bus Reset Sequence ..........................................................................................................................81
15.1.10
SMBus Alert Response .......................................................................................................................82
15.2
SMBus Isolation Logic ................................................................................................................... 82
15.3
SMBus Controlled GPIOs .............................................................................................................. 83
15.3.1
GPIO Pins ...........................................................................................................................................84
15.4
SMBus GPIO Registers ................................................................................................................. 84
15.4.1
Direction Registers..............................................................................................................................84
15.4.2
Output Type Registers ........................................................................................................................84
15.4.3
Data Registers ....................................................................................................................................84
15.4.4
GPIO Mask Registers .........................................................................................................................84
15.4.5
GPIO Change Status Register ............................................................................................................85
15.5
Operation of SMBus Interrupt ........................................................................................................ 85
Chapter 16
Runtime Registers........................................................................................................... 89
16.1
Runtime Registers Block Summary ............................................................................................... 89
16.2
Runtime Registers Block Description ............................................................................................89
Chapter 17
Configuration .................................................................................................................. 91
17.1
Configuration Access Ports............................................................................................................ 91
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