LPC47S42x
Enhanced Super I/O with LPC Interface for
Server Applications
FEATURES
3.3 Volt Operation (5V Tolerant)
Floppy Disk Controller (Supports Two FDCs)
Multi-Mode Parallel Port
Two
UARTs
8042 Keyboard Controller
SMBus
Controller
X-Bus
Interface
Programmable Wakeup Event Interface
(nIO_PME Pin)
SMI Support (nIO_SMI Pin)
GPIOs
(39)
Fan Speed Control Output
Fan Tachometer Input
ISA IRQ to Serial IRQ Conversion
XNOR
Chain
PC99 and ACPI 1.0 Compliant
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk
Controller
-
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
-
Configurable Open Drain/Push-Pull
Output Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
- 100%
IBM
Compatibility
-
Detects All Overrun and Underrun
Conditions
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, up to 15 IRQ and Three
DMA Options
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable
Precompensation
Modes
Keyboard
Controller
- 8042
Software
Compatible
- 8-Bit
Microcomputer
-
2k Bytes of Program ROM
-
256 Bytes of Data RAM
-
Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
-
Asynchronous Access to Two Data
Registers and One Status Register
-
Supports Interrupt and Polling Access
-
8-Bit Counter Timer
-
Port 92 Support
-
Fast Gate A20 and KRESET Outputs
Serial
Ports
-
Two Full Function Serial Ports
-
High Speed NS16C550 Compatible
UARTs with Send/Receive 16-Byte
FIFOs
-
Supports 230k and 460k Baud
-
Programmable Baud Rate Generator
-
Modem Control Circuitry
-
480 Address and 15 IRQ Options
-
IrDA 1.0, HP-SIR, ASK IR Support
Multi-Mode Parallel Port with ChiProtectTM
2
-
Standard Mode IBM PC/XT
, PC/AT
,
and PS/2TM Compatible Bidirectional
Parallel Port
-
Enhanced Parallel Port (EPP)
Compatible - EPP 1.7 and EPP 1.9
(IEEE 1284 Compliant)
-
IEEE 1284 Compliant Enhanced
Capabilities Port (ECP)
-
ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-
On
-
480 Address, up to 15 IRQ and 3 DMA
Options
-
Multiplexed Command, Address and
Data Bus
- 8-Bit
I/O
Transfers
-
8-Bit DMA Transfers
-
16-Bit Address Qualification
-
Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
-
Power Management Event (PME)
Interface Pin
100 Pin QFP package; green, lead-free
package also available
ORDERING INFORMATION
Order Number(s):
LPC47S422QFP for 100 pin QFP package
LPC47S422-MS for 100 pin QFP package (green, lead-free)
3
GENERAL DESCRIPTION
The LPC47S42x* is a 3.3V PC99 compliant
Super I/O controller. The LPC47S42x
implements the LPC interface, a pin reduced ISA
interface which provides the same or better
performance as the ISA/X-bus with a substantial
savings in pins used. The part provides 39 GPIO
pins, an SMBus controller, a fan speed control
output, a fan tachometer input, four ISA IRQs
that can be routed to any of the serial IRQs, and
an X-Bus interface.
The LPC47S42x incorporates a keyboard
interface, SMSC's true CMOS 765B floppy disk
controller, advanced digital data separator, two
16C550 compatible UARTs, one Multi-Mode
parallel port which includes ChiProtect circuitry
plus EPP and ECP, and Intelligent Power
Management. The true CMOS 765B core
provides 100% compatibility with IBM PC/XT and
PC/AT architectures in addition to providing data
overflow and underflow protection. The SMSC
advanced digital data separator incorporates
SMSC's patented data separator technology,
allowing for ease of testing and use. The on-chip
UARTs are compatible with the NS16C550. The
parallel port is compatible with IBM PC/AT
architecture, as well as IEEE 1284 EPP and
ECP. The LPC47S42x incorporates
sophisticated power control circuitry (PCC). The
PCC supports multiple low power down modes.
The LPC47S42x supports the ISA Plug-and-Play
Standard (Version 1.0a) and provides the
recommended functionality to support Windows
'95/'98 and PC99. The I/O Address, DMA
Channel and Hardware IRQ of each logical
device in the LPC47S42x may be reprogrammed
through the internal configuration registers.
There are 480 I/O address location options, a
Serialized IRQ interface, and three DMA
channels.
.
*The "x" in the part number is a designator that changes depending upon the particular BIOS used
inside the specific chip. "2" denotes AMI Keyboard BIOS and "7" denotes Phoenix 42i Keyboard BIOS.
4
TABLE OF CONTENTS
FEATURES ............................................................................................................................................. 1
GENERAL DESCRIPTION...................................................................................................................... 3
PIN CONFIGURATION............................................................................................................................ 6
DESCRIPTION OF PIN FUNCTIONS...................................................................................................... 7
Buffer Type Descriptions .....................................................................................................................12
Pins That Require External Pullup Resistors.......................................................................................13
3.3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................14
POWER FUNCTIONALITY ....................................................................................................................14
VCC Power .........................................................................................................................................14
VTR Support .......................................................................................................................................14
Internal PWRGOOD............................................................................................................................14
32.768 kHz Trickle Clock Input............................................................................................................14
Indication of 32kHz Clock....................................................................................................................14
Trickle Power Functionality .................................................................................................................15
Maximum Current Values....................................................................................................................17
Power Management Events (PME/SCI) ..............................................................................................17
FUNCTIONAL DESCRIPTION ...............................................................................................................18
Super I/O Registers.............................................................................................................................18
Host Processor Interface (LPC) ..........................................................................................................18
FLOPPY DISK CONTROLLER ..............................................................................................................23
FDC Internal Registers........................................................................................................................23
Command Set/Descriptions.................................................................................................................41
Instruction Set .....................................................................................................................................45
SERIAL PORT (UART) ..........................................................................................................................73
INFRARED INTERFACE........................................................................................................................88
PARALLEL PORT..................................................................................................................................90
POWER MANAGEMENT .....................................................................................................................113
SERIAL IRQ .........................................................................................................................................117
Routable IRQ to Serial IRQ Conversion Capability ...........................................................................121
8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................122
Keyboard Interface............................................................................................................................122
External Keyboard and Mouse Interface ...........................................................................................124
Keyboard Power Management..........................................................................................................124
Interrupts ...........................................................................................................................................125
Memory Configurations .....................................................................................................................125
Register Definitions ...........................................................................................................................125
External Clock Signal ........................................................................................................................125
Default Reset Conditions...................................................................................................................126
Latches On Keyboard and Mouse IRQs............................................................................................129
Keyboard and Mouse PME Generation.............................................................................................131
GENERAL PURPOSE I/O ....................................................................................................................132
GPIO Pins .........................................................................................................................................132
Description ........................................................................................................................................133
GPIO Control.....................................................................................................................................136
GPIO Operation ................................................................................................................................137
GPIO PME and SMI Functionality .....................................................................................................138
Either Edge Triggered Interrupts .......................................................................................................140
LED Functionality ..............................................................................................................................140
5
WATCH DOG TIMER ...........................................................................................................................140
SYSTEM MANAGEMENT INTERRUPT (SMI).....................................................................................141
SMI Registers....................................................................................................................................142
ACPI Support Register for SMI Generation.......................................................................................142
PME Support .......................................................................................................................................143
Wake On Specific Key Option ...........................................................................................................144
FAN SPEED CONTROL AND MONITORING......................................................................................145
Fan Speed Control ............................................................................................................................145
Fan Tachometer Input .......................................................................................................................147
SECURITY FEATURE..........................................................................................................................151
GPIO Device Disable Register Control..............................................................................................151
Device Disable Register ....................................................................................................................151
SMBus CONTROLLER........................................................................................................................151
Overview ...........................................................................................................................................151
Configuration Registers.....................................................................................................................152
Runtime Registers.............................................................................................................................152
Pin Multiplexing .................................................................................................................................159
SMBus Timeouts...............................................................................................................................159
X-BUS INTERFACE .............................................................................................................................160
X-Bus Chip Select Base I/O Address Registers ................................................................................163
X-Bus Configuration Register............................................................................................................163
RUNTIME REGISTERS........................................................................................................................164
Runtime Registers Block Summary...................................................................................................164
Runtime Registers Block Description ................................................................................................168
CONFIGURATION ...............................................................................................................................199
OPERATIONAL DESCRIPTION ..........................................................................................................228
Maximum Guaranteed Ratings..........................................................................................................228
DC Electrical Characteristics.............................................................................................................228
TIMING DIAGRAMS.............................................................................................................................232
ECP Parallel Port Timing...................................................................................................................243
X-Bus Timing.....................................................................................................................................252
PACKAGE OUTLINE ...........................................................................................................................260
APPENDIX - TEST MODES .................................................................................................................261
Board Test Mode...............................................................................................................................261
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