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MOST Network Interface Controller OS8104
Multimedia Network Protocol Chip
Features
Low Cost Multimedia Network Solution
24,5 Mb/sec MOST Network Interface Chip
Programmable bandwidth for up to
11 Mbps Packet Data, or up to
60 channels of Stream Data
Over 2900 control messages per second
On-Chip Network Management
Automatic stream data allocation
Network activity and data valid detection
Node position and delay sensing, alive
check and power management
Flexible Consumer Electronics Interface
Parallel, I
2
C and SPI control interface
I
2
S and various other serial stream I/O
Description
The OS8104 is a highly integrated C-MOS Net-
work Interface Controller with full featured inter-
face to the 24.5 Mbit/sec MOST optical network
system.
All relevant network management including
source data allocation, physical layer interface,
synchronization and network detection is on
chip. Its ultra low jitter PLL guarantees high qual-
ity audio and video transmission and clock re-
covery over a wide frequency range. Coding is
optimized for Plastic Optical Fiber.
The OS8104 works at ultralow bit error rate and
supports real-time synchronous networking at
ultra low cost and high data rate compromising
up to 15 stereo CD channels at the same time.
In addition to the control channel some of the
available bandwidth can be allocated to Asyn-
chronous Packet Data Transfer.
RX
SX0 - D0
SX1 - D7
SX2 - D1
SX3 - D2
SR0 - D3
SR1 - D6
SR2 - D4
SR3 - D5
FSY
SCK - SRC_FL
TX
SDA - SDOUT
AD0 - SDIN
AD1 - /CS
SCL
/INT
/RS
ASYNC
PAR_SRC
PAR_CP
XTO
C
P
_F
LO
W
PAD
0
PAD
1
/A
I
N
T
/R
D
/WR
/WAK
E
_
U
P
ST
A
T
U
S
R_
T
I
M
E
R
VR
E
F
FL
T
ER
R
O
R
RMCK
XTI
10
36
42
SOURCE
NET IN
22
23
WAKE UP UNIT
9
Blocks/Pins V1.0-29_980320
Programmable serial and parallel real-time data
interfaces with different clock and data modes
support various consumer electronic devices
such as Codecs, Converters and DSPs.
S/P DIF - IEC 958 digital interface, FIFO
buffered parallel stream data interface
MOST Network Interface Controller OS8104
Multimedia Network Protocol Chip
Functional Description
The chip contains a MOST core and several peripherals
including a clock manager, source data ports, and an
I
2
C/SPI control port.
The network interface includes an ultra low jitter Phase
Lock Loop (PLL) and a channel demodulator on the input
side. The network output provides a channel coded sig-
nal. Those signals can be connected directly to an optical
receiving/ transmitting device (FOT Unit) or a balanced
line driver. Each device is able to generate the network
clock or to synchronize to it. However, there can be only
one device generating the clock and the frame structure
within the entire network.
All kind of A/D converter, D/A converter, digital signal pro-
cessing and Media Player (CD-AUDIO/ VIDEO/ ROM etc.)
devices can be synchronized using one of the different
clock and serial interface modes.
The source data ports SR0-3 and SX0-3 provide a data
interface to the serial bitstream. Data sources and sinks
can be connected to the source ports to provide data to
another node on the network, or receive data from an-
other node on the network. Up to 4 inputs are usable as
real time data input channels and up to 4 outputs as real
time data output channels.
The MOST Network Interface Controller can operate in a
real Peer to Peer Network or in a host centric architec-
ture.
All trademarks used in this document are proprietary of their respective owners
PFL_OS8104-03.pmd
12/02
MOST and OptoLyzer are registered trademarks of Oasis SiliconSystems
1998-2002 Oasis SiliconSystems, all rights reserved
MOST Network Implementation
An example implementation including Audio/Video, Telephone and Computing Applications is shown above. Up to
64 devices with as many as 15 MPEG 1 Audio/Video channels can be implemented on one fiber without a central
host.
PDF 
ZIP