SMSC SIO1036
PRODUCT PREVIEW
Revision 0.4 (04-27-05)
Data Brief
PRODUCT FEATURES
ORDER NUMBER(S):
SIO1036-AEY FOR 36 PIN, QFN PACKAGE
SIO1036-ZG FOR 36 PIN, QFN PACKAGE (GREEN, LEAD-FREE)
SIO1036
Super I/O with LPC
Interface with FIR and
Consumer IR Support
3.3 Volt Operation (5V tolerant)
GPIOs (1)
XNOR Chain
PC99a, PC2001
36-pin QFN package, green, lead-free package also
available
Intelligent Auto Power Management
Infrared Communications Controllers
-- One IR Port
-- Multi-Protocol Serial Communications Controllers
-- IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR
Support
-- Multiple Base I/O Address options, 15 IRQ Options and
3 DMA Options
-- Two Pin Serial Port (UART) Support
Multi-Mode Parallel Port with ChiProtectTM
-- Standard Mode IBM PC/XT
, PC/AT
, and PS/2TM
Compatible Bidirectional Parallel Port
-- Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
-- IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
-- ChiProtect Circuitry for Protection Against Damage Due
to Printer Power-On
-- 192 Base I/O Address, 15 IRQ and 3 DMA Options
LPC Bus Host Interface
-- Multiplexed Command, Address and Data Bus
-- 8-Bit I/O Transfers
-- 8-Bit DMA Transfers
-- 16-Bit Address Qualification
-- Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
-- PCI CLKRUN# Support
80 Arkay Drive
Hauppauge, NY 11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2005. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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Super I/O with LPC Interface with FIR and Consumer IR Support
Revision 0.4 (04-27-05)
2
SMSC SIO1036
PRODUCT PREVIEW
Super I/O with LPC Interface with FIR and Consumer IR Support
SMSC SIO1036
3
Revision 0.4 (04-27-05)
PRODUCT PREVIEW
General Description
The SMSC SIO1036 is a 3.3V PC 99, PC2001 compliant Super I/O Controller. The SIO1036
implements the LPC interface, a pin reduced ISA interface which provides the same or better
performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 1 GPIO
pin.
The SIO1036 incorporates a Multi-Mode parallel port with ChiProtect
circuitry plus EPP and ECP
support. The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and
ECP. The parallel port ChiProtect
circuitry prevents damage caused by an attached powered printer
when the SIO1036 is not powered.
The SIO1036 offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.
There is a dedicated Serial Infrared interface UART, which complies with IrDA v1.2 (Fast IR), HPSIR,
and ASKIR formats (used by Sharp and other PDAs), as well as Consumer IR. This can also be used
as a 2 pin UART.
The SIO1036 features Software Configurable Logic (SCL) for ease of use. SCL allows programmable
system configuration of key functions such as the parallel port and UART.
The SIO1036 supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides the
recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the SIO1036 may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.
Figure 1 SIO1036 Block Diagram
SER_IRQ
PCI_CLK
Vcc Vss
Denotes Multifunction Pins
IRTX, IRMODE*
IRRX, ALT_IRRX*
SERIAL
IRQ
LPC BUS
INTERFACE
CLOCK
GEN
CLOCKI
WDT
*
CONFIGURATION
REGISTERS
GENERAL
PURPOSE
I/O
GPIO*
MULTI-MODE
PARALLEL
PORT
PD[0:7],
BUSY, SLCT,
PE, nERROR, nACK
nSLCTIN, nALF
nINIT, nSTROBE
CONTROL, ADDRESS, DATA
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
LPCPD#
PCI_RESET#
INFRARED
INTERFACE
(IrCC 2.0)
and
2 Pin UART
CLKRUN#
SMI
SMSC SIO1036
4
Revision 0.4 (0
4-27-
05)
PRODUCT PREVIEW
Package Outline
-
SEE SPEC FRONT PAGE FOR REVISION HISTORY
-
-
DECIMAL
X.X
X.XX
X.XXX
MATERIAL
FINISH
STD COMPLIANCE
THIRD ANGLE PROJECTION
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
APPROVED
ANGULAR
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DIM AND TOL PER ASME Y14.5M - 1994
DRAWN
CHECKED
NAME
SCALE
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
DWG NUMBER
TITLE
DATE
SHEET
REV
REVISION HISTORY
DESCRIPTION
REVISION
RELEASED BY
DATE
S.K.ILIEV
S.K.ILIEV
S.K.ILIEV
1
-
-
0.025
0.05
0.1
12/6/04
1:1
12/6/04
12/6/04
F
JEDEC: MO-220
1 OF 1
36 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH
PACKAGE OUTLINE
MO-36-QFN-6x6
SIDE VIEW
3-D VIEWS
TOP VIEW
3
2
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL IS 0.05mm AT MAXIMUM MATERIAL CONDITION. DIMENSIONS
"b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE
TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
4. COPLANARITY ZONE APPLIES TO EXPOSED PAD AND TERMINALS.
E2
E
E1
0.6(MAX)
0.6(MAX)
D
D1
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
36X b
36X L
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
D2
e
EXPOSED PAD
3
A1
A2
A
CHAMFERED CORNERS
ARE OPTIONAL 4X
36X 0.2 MIN
4
ccc C
4
C
A3
4X 0-12
D2 / E2 VARIATIONS
CATALOG PART
PDF 
ZIP