SMSC SIO10N268
Page 1
Rev. 0.5 (03-24-05)
DATASHEET
SIO10N268
Advanced Notebook I/O
for ISA or LPC Designs
with X-Bus Interface for
I/O, Memory, and FWH
Emulation and Four Serial
Ports
Datasheet
Product Features
3.3 Volt Operation (5 Volt Tolerant)
PC99, PC01, ACPI 1.0 Compliant
LPC or ISA Interface
-
SIO10N268 offers two modes of operation: LPC
Mode or ISA Mode. These modes are jumper
selectable.
X-Bus Interface (LPC Mode Only)
-
Three chip selects (2 I/O and 1 Memory)
-
8-bit data transfers
-
Support for up to 2MB Flash
-
Interfaces with 3V memory devices
-
Support for up to two external I/O components
-
Offers three modes of operation for I/O devices
-
Provides FWH Emulation
Serial IRQ Compatible with Serialized IRQ
Support for PCI Systems
Programmable Wake-up Event (PME) Interface
(33) General Purpose Input/Output Pins
System Management Interrupt
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk Controller
-
Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
-
Supports Two Floppy Drives Directly
-
Configurable Open Drain/Push-Pull Output Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun Conditions
-
Sophisticated Power Control Circuitry (PCC)
Including Multiple Power Down Modes for Reduced
Power Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, Up to 15 IRQ and Four DMA Options
Floppy Disk Available on Parallel Port Pins (ACPI
Compliant)
-
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
-
Programmable Precompensation Modes
Serial
Ports
-
Four Full Function Serial Ports
-
High Speed NS16C550 Compatible UARTs with
Send/Receive 16-Byte FIFOs
-
Supports 230k and 460k Baud
-
Programmable Baud Rate Generator
-
Modem Control Circuitry
-
480 Address and 15 IRQ Options
Infrared Communications Controller
-
IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR
Support
-
2 IR Ports
-
96 Base I/O Address, 15 IRQ, and 4 DMA Options
Multi-Mode Parallel Port with ChiProtect
-
Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bi-directional Parallel Port
-
Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
-
IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
-
ChiProtect Circuitry for Protection
-
480 Address, Up to 15 IRQ, and Four DMA Options
Two LED Drivers with blinking options
Watch Dog Timer with optional output pin
128 Pin TQFP package, VTQN package (green,
lead-free)
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 2
SMSC SIO10N268
DATASHEET
ORDERING INFORMATION
Order Number(s):
SIO10N268-NE for 128 pin TQFP package
SIO10N268-NU for 128 pin VTQN package (green, lead-free)
80 Arkay Drive
Hauppauge, NY 11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2005. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
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OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268 Page
3
Rev. 0.5 (03-24-05)
DATASHEET
TABLE OF CONTENTS
Chapter 1
General Description ........................................................................................................... 13
Chapter 2
Pin Layouts ......................................................................................................................... 14
2.1
LPC Mode ......................................................................................................................................... 14
2.2
ISA Mode........................................................................................................................................... 15
Chapter 3
Pin Configurations for SIO10N268 .................................................................................. 16
Chapter 4
Description of Pin Functions ............................................................................................. 18
4.1
Buffer Type Description..................................................................................................................... 28
4.2
Design Guidelines for Implemented Buffer Types ............................................................................ 28
Chapter 5
Block Diagram.................................................................................................................... 29
Chapter 6
3.3 Volt Operation / 5 Volt Tolerance .............................................................................. 30
Chapter 7
Power Functionality ........................................................................................................... 31
7.1
VCC Power........................................................................................................................................ 31
7.2
VTR Support...................................................................................................................................... 31
7.3
32.768 kHz Trickle Clock Input ......................................................................................................... 31
7.4
Internal PWRGOOD .......................................................................................................................... 32
7.5
Trickle Power Functionality ............................................................................................................... 32
7.6
Maximum Current Values.................................................................................................................. 33
7.7
Power Management Events (PME/SCI)............................................................................................ 33
Chapter 8
Functional Description....................................................................................................... 34
8.1
Super I/O Registers........................................................................................................................... 34
8.2
Host Processor Interface (LPC or ISA) ............................................................................................. 34
8.3
LPC Interface (LPC Mode only) ........................................................................................................ 35
8.3.1
LPC Interface Signal Definition ...............................................................................................................35
8.3.2
LPC Cycles .............................................................................................................................................35
8.3.3
LFRAME# Usage....................................................................................................................................36
8.3.4
Field Definitions ......................................................................................................................................36
8.3.4.1
I/O Read and Write Cycles ..............................................................................................................36
8.3.4.2
DMA Read and Write Cycles ...........................................................................................................36
8.3.4.3
Memory Read and Write Cycles ......................................................................................................37
8.3.5
Power Management................................................................................................................................37
8.3.5.1
CLOCKRUN Protocol ......................................................................................................................37
8.3.5.2
LPCPD Protocol ..............................................................................................................................37
8.3.5.3
SYNC Protocol ................................................................................................................................38
8.3.5.4
SYNC Timeout.................................................................................................................................38
8.3.5.5
SYNC Patterns and Maximum Number of SYNCS ..........................................................................38
8.3.5.6
SYNC Error Indication .....................................................................................................................38
8.3.5.7
Reset Policy.....................................................................................................................................39
8.3.6
LPC Transfers ........................................................................................................................................39
8.3.6.1
Wait State Requirements.................................................................................................................39
8.4
FWH Interface (LPC Mode Only) ...................................................................................................... 40
8.4.1
Enabling the FWH Interface....................................................................................................................40
8.4.1.1
MEMEN ...........................................................................................................................................40
8.4.1.2
FWHSEL .........................................................................................................................................40
8.4.2
FWH and LPC Memory Addressing........................................................................................................41
8.4.3
FWH Cycle Types...................................................................................................................................41
8.4.4
Field Definitions ......................................................................................................................................42
8.4.4.1
START.............................................................................................................................................42
8.4.4.2
IDSEL ..............................................................................................................................................42
8.4.4.3
MSIZE .............................................................................................................................................42
8.4.4.4
MADDR ...........................................................................................................................................42
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 4
SMSC SIO10N268
DATASHEET
8.4.4.5
SYNC ..............................................................................................................................................42
8.4.4.6
TAR .................................................................................................................................................42
8.4.4.7
Data.................................................................................................................................................42
8.4.5
Protocol ..................................................................................................................................................43
8.4.5.1
Preamble .........................................................................................................................................43
8.4.6
Read Cycle .............................................................................................................................................43
8.4.6.1
Single Byte ......................................................................................................................................43
8.4.7
Write Cycles............................................................................................................................................44
8.4.7.1
Single Byte ......................................................................................................................................44
8.4.8
Error Reporting .......................................................................................................................................44
8.4.9
FWH Cycle Examples.............................................................................................................................44
8.4.9.1
EXAMPLE 1: FWH 1-Byte Read......................................................................................................44
8.4.9.2
EXAMPLE 2: FWH 1-Byte Write......................................................................................................45
8.5
X-Bus Interface (LPC Mode Only)..................................................................................................... 45
8.5.1
I/O Cycles ...............................................................................................................................................46
8.5.1.1
Conceptual Diagrams of X-Bus I/O interface ...................................................................................47
8.5.2
Memory Cycles .......................................................................................................................................49
8.6
ISA Interface (ISA Mode Only).......................................................................................................... 50
8.6.1
AEN signal..............................................................................................................................................51
8.7
Floppy Disk Controller....................................................................................................................... 51
8.7.1
FDC Internal Registers ...........................................................................................................................52
8.7.1.1
Status Register A (SRA)..................................................................................................................52
8.7.1.2
Status Register B (SRB)..................................................................................................................54
8.7.1.3
Digital Output Register (DOR) .........................................................................................................56
8.7.1.4
Tape Drive Register (TDR) ..............................................................................................................57
8.7.1.5
Data Rate Select Register (DSR) ....................................................................................................58
8.7.1.6
Main Status Register (MSR) ............................................................................................................60
8.7.1.7
Data Register (FIFO) .......................................................................................................................61
8.7.1.8
Digital Input Register (DIR)..............................................................................................................62
8.7.1.9
Configuration Control Register (CCR) .............................................................................................63
8.7.2
Status Register Encoding .......................................................................................................................64
8.7.2.1
Reset ...............................................................................................................................................66
8.7.2.2
Modes Of Operation ........................................................................................................................66
8.7.3
DMA Transfers .......................................................................................................................................67
8.7.4
Controller Phases ...................................................................................................................................67
8.7.4.1
Command Phase.............................................................................................................................67
8.7.4.2
Execution Phase..............................................................................................................................67
8.7.4.3
Data Transfer Termination...............................................................................................................68
8.7.4.4
Result Phase ...................................................................................................................................68
8.7.5
Command Set/Descriptions ....................................................................................................................69
8.7.6
Instruction Set.........................................................................................................................................71
8.7.7
Data Transfer Commands ......................................................................................................................79
8.7.7.1
Read Data .......................................................................................................................................79
8.7.7.2
Read Deleted Data ..........................................................................................................................80
8.7.7.3
Read A Track...................................................................................................................................81
8.7.7.4
Write Data........................................................................................................................................82
8.7.7.5
Write Deleted Data ..........................................................................................................................82
8.7.7.6
Verify ...............................................................................................................................................82
8.7.7.7
Format A Track................................................................................................................................83
8.7.8
Control Commands.................................................................................................................................85
8.7.8.1
Read ID ...........................................................................................................................................85
8.7.8.2
Recalibrate ......................................................................................................................................85
8.7.8.3
Seek ................................................................................................................................................85
8.7.8.4
Sense Interrupt Status.....................................................................................................................86
8.7.8.5
Sense Drive Status..........................................................................................................................87
8.7.8.6
Specify.............................................................................................................................................87
8.7.8.7
Configure .........................................................................................................................................87
8.7.8.8
Version ............................................................................................................................................88
8.7.8.9
Relative Seek ..................................................................................................................................88
8.7.8.10
Perpendicular Mode.........................................................................................................................89
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268 Page
5
Rev. 0.5 (03-24-05)
DATASHEET
8.7.8.11
Lock.................................................................................................................................................90
8.7.8.12
Enhanced DUMPREG .....................................................................................................................91
8.7.8.13
Compatibility ....................................................................................................................................91
8.8
Serial Port (UART) ............................................................................................................................ 91
8.8.1
Register Description ...............................................................................................................................91
8.8.1.1
Receive Buffer Register (RB) ..........................................................................................................92
8.8.1.2
Transmit Buffer Register (TB)..........................................................................................................92
8.8.1.3
Interrupt Enable Register (IER) .......................................................................................................92
8.8.1.4
FIFO Control Register (FCR)...........................................................................................................93
8.8.1.5
Interrupt Identification Register (IIR)................................................................................................94
8.8.1.6
Line Control Register (LCR) ............................................................................................................95
8.8.1.7
Modem Control Register (MCR) ......................................................................................................97
8.8.1.8
Line Status Register (LSR) ..............................................................................................................98
8.8.1.9
Modem Status Register (MSR)........................................................................................................99
8.8.1.10
Scratchpad Register (SCR) ...........................................................................................................100
8.8.2
Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ..............................................100
8.8.3
Effect Of The Reset on Register File ....................................................................................................100
8.8.4
FIFO Interrupt Mode Operation.............................................................................................................100
8.8.5
FIFO Polled Mode Operation................................................................................................................101
8.8.6
Notes On Serial Port Operation ............................................................................................................108
8.8.6.1
FIFO Mode Operation....................................................................................................................108
8.8.6.2
TX and RX FIFO Operation ...........................................................................................................108
8.9
Infrared Interface .............................................................................................................................108
8.9.1
IrDA SIR/FIR and ASKIR ......................................................................................................................109
8.9.2
Consumer IR.........................................................................................................................................109
8.9.3
Hardware Interface ...............................................................................................................................109
8.9.4
IR Half Duplex Turnaround Delay Time ................................................................................................110
8.9.5
IR Transmit Pins ...................................................................................................................................111
8.10
Parallel Port..................................................................................................................................111
8.10.1
IBM XT/AT Compatible, Bi-Directional And EPP Modes ...................................................................113
8.10.1.1
Data Port .......................................................................................................................................113
8.10.1.2
Status Port.....................................................................................................................................113
8.10.1.3
Control Port ...................................................................................................................................114
8.10.1.4
EPP Address Port..........................................................................................................................115
8.10.1.5
EPP Data Port 0 ............................................................................................................................115
8.10.1.6
EPP Data Port 1 ............................................................................................................................115
8.10.1.7
EPP Data Port 2 ............................................................................................................................115
8.10.1.8
EPP Data Port 3 ............................................................................................................................115
8.10.2
EPP 1.9 Operation ............................................................................................................................116
8.10.2.1
Software Constraints .....................................................................................................................116
8.10.2.2
EPP 1.9 Write ................................................................................................................................116
8.10.2.3
EPP 1.9 Read................................................................................................................................117
8.10.3
EPP 1.7 Operation ............................................................................................................................117
8.10.3.1
Software Constraints .....................................................................................................................118
8.10.3.2
EPP 1.7 Write ................................................................................................................................118
8.10.3.3
EPP 1.7 Read................................................................................................................................118
8.10.4
Extended Capabilities Parallel Port ...................................................................................................119
8.10.5
Vocabulary ........................................................................................................................................120
8.10.6
ECP Implementation Standard..........................................................................................................121
8.10.6.1
Description.....................................................................................................................................121
8.10.6.2
Register Definitions .......................................................................................................................122
8.10.7
Operation ..........................................................................................................................................128
8.10.7.1
Mode Switching/Software Control..................................................................................................128
8.10.7.2
ECP Operation ..............................................................................................................................128
8.10.7.3
Termination from ECP Mode .........................................................................................................129
8.10.7.4
Command/Data .............................................................................................................................129
8.10.7.5
Data Compression.........................................................................................................................129
8.10.7.6
Pin Definition .................................................................................................................................130
8.10.7.7
LPC Connections...........................................................................................................................130
8.10.7.8
Interrupts .......................................................................................................................................130
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