SMSC DS SP37E760

Rev. 04/13/2001

SP37E760

PRELIMINARY

3.3V I/O Controller

for Embedded Applications

FEATURES

3.3 Volt Operation
Intelligent Auto Power Management
16 Bit Address Qualification (Optional)
Serial

Ports

- Two High Speed NS16C550 Compatible

UARTs with Send/Receive 16 Byte FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

- Modem Control Circuitry

ISA Host Interface
General Purpose Address Decoder

- 16-Byte Block Decode

Multi-Mode Parallel Port with ChiProtect

- Standard

Mode

- IBM PC/XT, PC/AT, and PS/2 Compatible

Bi-directional Parallel Port

- Enhanced Parallel Port (EPP) Compatible

- EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- Enhanced Capabilities Port (ECP) Compatible

(IEEE 1284 Compliant)

- Incorporates ChiProtect Circuitry for Protection

Against Damage Due to Printer Power-On

- 192 Base I/O Address, 7 IRQ and 3 DMA Options

100 Pin QFP and TQFP Packages

GENERAL DESCRIPTION

The SMSC SP37E760 is a 3.3v PC 97-compliant I/O Controller. The SP37E760 utilizes SMSC's proven SuperCell
technology and is optimized for embedded applications. The SP37E760 incorporates a 16-byte data FIFO, two
16C550 compatible UARTs and one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support.
Both on-chip UARTs are compatible with the NS16C550.

The parallel port is compatible with IBM PC/AT architectures. The parallel port ChiProtect circuitry prevents damage
caused by an attached powered printer when the SP37E760 is not powered.

The SP37E760 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down
modes. The SP37E760 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable
system configuration of key functions such as the parallel port, and UARTs.

ORDERING INFORMATION

Order Numbers:

SP37E760-MC for 100 Pin QFP Package

SP37E760-MD for 100 Pin TQFP Package

SMSC DS SP37E760

Page 2

Rev. 04/13/2001

80 Arkay Drive

Hauppauge, NY 11788

(631)

435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT
ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES.

SMSC DS SP37E760

Page 3

Rev. 04/13/2001

TABLE OF CONTENTS

1 PIN

CONFIGURATIONS ....................................................................................................................... 6

2 PIN

DESCRIPTION ............................................................................................................................... 8

2.1 B

UFFER

YPE

...................................................................................................................... 8

2.2 B

UFFER

YPE

UMMARY

................................................................................................................. 12

2.3 O

UTPUT

RIVERS

........................................................................................................................... 12

3 FUNCTIONAL

DESCRIPTION............................................................................................................ 14

3.1 H

OST

ROCESSOR

NTERFACE

........................................................................................................ 14

4 SERIAL

PORT (UART) ....................................................................................................................... 15

4.1 R

EGISTER

ESCRIPTION

................................................................................................................. 15

4.1.1 RECEIVE

BUFFER

REGISTER (RB) ................................................................................... 15

4.1.2 TRANSMIT

BUFFER REGISTER (TB) ................................................................................. 15

4.1.3 INTERRUPT

ENABLE

REGISTER (IER).............................................................................. 15

4.1.4 INTERRUPT

IDENTIFICATION REGISTER (IIR) ................................................................ 16

4.1.5 FIFO

CONTROL

REGISTER (FCR) ..................................................................................... 17

4.1.6 LINE

CONTROL

REGISTER (LCR)...................................................................................... 18

4.1.7 MODEM

CONTROL

REGISTER (MCR)............................................................................... 19

4.1.8 LINE

STATUS

REGISTER (LSR) ......................................................................................... 20

4.1.9 MODEM

STATUS

REGISTER (MSR) .................................................................................. 21

4.1.10 SCRATCHPAD

REGISTER (SCR) ....................................................................................... 21

4.1.11

PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ................................ 21

4.1.12

The Affects of RESET on the UART Registers..................................................................... 22

4.2 FIFO

NTERRUPT

ODE

PERATION

................................................................................................ 23

4.3 FIFO

OLLED

ODE

PERATION

.................................................................................................... 23

4.4 N

OTES

ERIAL

ORT

FIFO

ODE

PERATION

........................................................................... 25

4.4.1 GENERAL ............................................................................................................................. 25
4.4.2

TX AND RX FIFO OPERATION............................................................................................ 25

5 PARALLEL PORT............................................................................................................................... 27

5.1 IBM

XT/AT

COMPATIBLE,

BI-DIRECTIONAL

AND

EPP

MODES .............................................. 28

5.1.1 DATA PORT .......................................................................................................................... 28
5.1.2 STATUS PORT ..................................................................................................................... 28
5.1.3 CONTROL PORT.................................................................................................................. 29
5.1.4 EPP

ADDRESS PORT.......................................................................................................... 29

5.1.5 EPP

DATA PORT 0............................................................................................................... 29

5.1.6 EPP

DATA PORT 1............................................................................................................... 29

5.1.7 EPP

DATA PORT 2............................................................................................................... 30

5.1.8 EPP

DATA PORT 3............................................................................................................... 30

5.2 EPP

1.9

OPERATION................................................................................................................... 30

5.2.1 Software

Constraints ............................................................................................................. 30

5.2.2 EPP

1.9 Write ........................................................................................................................ 30

5.2.3 EPP

1.9 Read........................................................................................................................ 31

5.3 EPP

1.7

OPERATION................................................................................................................... 31

5.3.1 Software

Constraints ............................................................................................................. 31

5.3.2 EPP

1.7 Write ........................................................................................................................ 31

5.3.3 EPP

1.7 Read........................................................................................................................ 32

5.4 EXTENDED

CAPABILITIES

PARALLEL

PORT ........................................................................... 33

5.4.1 Vocabulary ............................................................................................................................ 33
5.4.2 ISA

IMPLEMENTATION STANDARD................................................................................... 34

5.4.3 Description ............................................................................................................................ 34
5.4.4 Register Definitions ............................................................................................................... 35
5.4.5 OPERATION ......................................................................................................................... 39

SMSC DS SP37E760

Page 4

Rev. 04/13/2001

6 AUTO

POWER

MANAGEMENT......................................................................................................... 43

6.1 P

EHAVIOR

................................................................................................................................ 43

6.1.1 System

Interface Pins ........................................................................................................... 43

6.2 UART

OWER

ANAGEMENT

.......................................................................................................... 43

6.3 P

ARALLEL

ORT

............................................................................................................................. 44

7 CONFIGURATION .............................................................................................................................. 45

7.1 C

ONFIGURATION

CCESS

ORTS

..................................................................................................... 45

7.2 C

ONFIGURATION

TATE

................................................................................................................... 45

7.2.1

Entering the Configuration State ........................................................................................... 45

7.2.2 Configuration

Register Programming.................................................................................... 45

7.2.3

Exiting the Configuration State.............................................................................................. 45

7.2.4 Programming Example.......................................................................................................... 46
7.2.5 Configuration

Select Register (CSR) .................................................................................... 46

7.3 C

ONFIGURATION

EGISTERS

ESCRIPTION

...................................................................................... 46

7.3.1

CR00 ..................................................................................................................................... 48

7.3.2

CR01 ..................................................................................................................................... 48

7.3.3

CR02 ..................................................................................................................................... 49

7.3.4

CR03 ..................................................................................................................................... 49

7.3.5

CR04 ..................................................................................................................................... 50

7.3.6

CR05 ..................................................................................................................................... 50

7.3.7

CR06 ..................................................................................................................................... 50

7.3.8

CR07 ..................................................................................................................................... 51

7.3.9

CR08 ..................................................................................................................................... 51

7.3.10

CR09 ..................................................................................................................................... 51

7.3.11

CR0A ..................................................................................................................................... 52

7.3.12

CR0B ..................................................................................................................................... 52

7.3.13

CR0C..................................................................................................................................... 52

7.3.14

CR0D..................................................................................................................................... 53

7.3.15

CR0E ..................................................................................................................................... 53

7.3.16

CR0F ..................................................................................................................................... 53

7.3.17

CR10 ..................................................................................................................................... 53

7.3.18

CR11 ..................................................................................................................................... 53

7.3.19 CR12

- CR13......................................................................................................................... 54

7.3.20

CR14 ..................................................................................................................................... 54

7.3.21

CR15 ..................................................................................................................................... 54

7.3.22

CR16 ..................................................................................................................................... 54

7.3.23

CR17 ..................................................................................................................................... 54

7.3.24 CR18

- CR1D ........................................................................................................................ 54

7.3.25

CR1E ..................................................................................................................................... 55

7.3.26

CR1F ..................................................................................................................................... 55

7.3.27

CR20 ..................................................................................................................................... 55

7.3.28 CR21

- CR22......................................................................................................................... 55

7.3.29

CR23 ..................................................................................................................................... 55

7.3.30

CR24 ..................................................................................................................................... 55

7.3.31

CR25 ..................................................................................................................................... 55

7.3.32

CR26 ..................................................................................................................................... 56

7.3.33

CR27 ..................................................................................................................................... 56

7.3.34

CR28 ..................................................................................................................................... 56

7.3.35

CR29 ..................................................................................................................................... 57

7.3.36

CR2A ..................................................................................................................................... 57

7.3.37

CR2B ..................................................................................................................................... 57

7.3.38

CR2C..................................................................................................................................... 57

7.3.39

CR2D..................................................................................................................................... 58

7.3.40

CR2E ..................................................................................................................................... 58

7.3.41

CR2F ..................................................................................................................................... 58

8 OPERATIONAL

DESCRIPTION ......................................................................................................... 59

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