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Электронный компонент: USB97C201-MC

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SMSC DS USB97C201
Page 1
Rev. 03/25/2002
PRELIMINARY
USB97C201
Rev 1.5
USB 2.0 ATA/ ATAPI Controller
FEATURES
2.5 Volt, Low Power Core Operation
3.3 Volt I/O with 5V input tolerance
Complete USB Specification 2.0 Compatibility
-
Includes USB 2.0 Transceiver
- A Bi-directional Control, a Bi-directional
Interrupt, and a Bi-directional Bulk Endpoint
are provided.
Complete System Solution for interfacing ATA or
ATAPI devices to USB 2.0 bus
- Supports USB Mass Storage Compliant
Bootable BIOS
-
Support for ATAPI Devices:
- CD-ROM
- CD-R
- CD-RW
- DVD
- DVD/R/W
8051 8 bit microprocessor
-
Provides low speed control functions
- 30 Mhz execution speed at 4 cycles per
instruction average
- 768 Bytes of internal SRAM for general
purpose scratchpad or program execution
while re-flashing external ROM
Double Buffered Bulk Endpoint
-
Bi-directional 512 Byte Buffer for Bulk
Endpoint
-
64 Byte RX Control Endpoint Buffer
-
64 Byte TX Control Endpoint Buffer
-
64 Byte TX Interrupt Endpoint Buffer
-
64 Byte RX Interrupt Endpoint Buffer
External Program Memory Interface
-
64K Byte Code Space
-
Flash, SRAM, or EPROM Memory
On Board 12Mhz Crystal Driver Circuit
Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz
MCU clock, and 60Mhz ATA clock
Supports firmware upgrade via USB bus if "boot
block" Flash program memory is used
8 GPIOs for special function use : LED indicators,
button inputs, etc.
- Inputs capable of generating interrupts with
either edge sensitivity
- One GPIO has automatic sec toggle
capability for flashing an LED indicator.
100 Pin TQFP Package (14.0 x 14.0 mm footprint)
- 25% smaller body size than other 100 pin
TQFP Packages
100 Pin QFP Package
ORDERING INFORMATION
Order Numbers:
USB97C201-MN
for 100 pin TQFP package
USB97C201-MC
for 100 pin QFP package
SMSC DS USB97C201
Page 2
Rev. 03/25/2002
PRELIMINARY
STANDARD MICROSYSTEMS CORPORATION (SMSC) 2002
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS USB97C201
Page 3
Rev. 03/25/2002
PRELIMINARY
TABLE OF CONTENTS
1.0
GENERAL DESCRIPTION .................................................................................................................................. 6
2.0
PIN TABLE .......................................................................................................................................................... 7
3.0
PIN CONFIGURATION........................................................................................................................................ 8
3.1
QFP/TQFP 100 Pin ..........................................................................................................................8
4.0
BLOCK DIAGRAM .............................................................................................................................................. 9
5.0
PIN DESCRIPTIONS ......................................................................................................................................... 10
5.1
BUFFER TYPE DESCRIPTIONS...................................................................................................13
6.0
FUNCTIONAL BLOCK DESCRIPTIONS .......................................................................................................... 14
6.1
MCU ...............................................................................................................................................14
6.1.1
MCU Memory Map: Code Space ...........................................................................................14
6.1.2
MCU Memory Map: XData Space..........................................................................................15
6.1.3
MCU Block Register Summary ..............................................................................................16
6.1.4
MCU Register Descriptions....................................................................................................19
6.2
SIE Block .......................................................................................................................................42
6.2.1
Autonomous USB Protocol ....................................................................................................42
6.2.2
USB Events............................................................................................................................43
6.2.3
Standard Device Requests ....................................................................................................44
6.2.4
SIE Configurations .................................................................................................................44
6.3
IDE Controller Description...........................................................................................................44
6.3.1
IDE Configurations.................................................................................................................45
6.3.2
PIO IDE Operations ...............................................................................................................45
6.3.3
PIO IDE Data Prefetching and Posting ..................................................................................45
6.3.4
DMA Transfers.......................................................................................................................46
6.3.5
Ultra ATA/66 Synchronous DMA Operation...........................................................................46
6.3.6
Ultra ATA/66 Operation..........................................................................................................47
6.4
SRAM Buffers................................................................................................................................48
6.5
8051 Options .................................................................................................................................48
6.6
Address Multiplexing ...................................................................................................................48
6.7
SRAM Time Multiplexer Operation .............................................................................................49
6.7.1
Phase 0 (0)..........................................................................................................................49
6.7.2
Phase 1 (1)..........................................................................................................................49
6.7.3
Phase 2 (2)..........................................................................................................................49
6.7.4
Phase 3 (3)..........................................................................................................................49
6.8
EP2 SRAM Buffer Operation........................................................................................................49
6.9
EP2 Automatic Buffer Operations...............................................................................................50
6.9.1
Receive Auto-Toggle .............................................................................................................50
6.9.2
Transmit Buffer Operation .....................................................................................................51
6.9.3
Automatic Transfer Operation................................................................................................52
7.0
DC PARAMETERS............................................................................................................................................ 54
8.0
AC SPECIFICATIONS....................................................................................................................................... 56
8.1
ATA/ATAPI.....................................................................................................................................56
8.2
USB2.0 Timing ..............................................................................................................................56
9.0
PACKAGING ..................................................................................................................................................... 57
10.0
USB97C201 REVISIONS.............................................................................................................................. 59
SMSC DS USB97C201
Page 4
Rev. 03/25/2002
PRELIMINARY
TABLES
Table 1 - USB97C201 Buffer Type Descriptions ......................................................................................................... 13
Table 2 - MCU Code Memory Map.............................................................................................................................. 14
Table 3 - MCU XData Memory Map ............................................................................................................................ 15
Table 4 - MCU Block Register Summary..................................................................................................................... 16
Table 5 - 8051 Core SFR Register Summary.............................................................................................................. 18
Table 6 - Interrupt 0 Source Register .......................................................................................................................... 19
Table 7 - Interrupt 0 Mask ........................................................................................................................................... 20
Table 8 - Interrupt 1 Source Register .......................................................................................................................... 20
Table 9 - Interrupt 1 Mask ........................................................................................................................................... 21
Table 10 - Device Revision Register ........................................................................................................................... 21
Table 11 - Device Identification Register..................................................................................................................... 21
Table 12 - GPIO Direction Register............................................................................................................................. 22
Table 13 - GPIO Output Register ................................................................................................................................ 24
Table 14 - GPIO Input Register................................................................................................................................... 24
Table 15 GPIO Interrupt Status Register (INT4) ...................................................................................................... 24
Table 16 GPIO Interrupt Mask Register ................................................................................................................... 25
Table 17 - Utility Configuration Register...................................................................................................................... 26
Table 18 SRAM Data Port Register.......................................................................................................................... 26
Table 19 SRAM Address Register 1......................................................................................................................... 26
Table 20 SRAM Address Register 2......................................................................................................................... 27
Table 21 - MCU Clock Source Select.......................................................................................................................... 27
Table 22 - Wakeup Source 1 Register (INT2) ............................................................................................................. 28
Table 23 - Wakeup Mask 1 Register........................................................................................................................... 28
Table 24 USB Address Register ............................................................................................................................... 29
Table 25 SIE Configuration Register........................................................................................................................ 29
Table 26 - USB Bus Status Register ........................................................................................................................... 30
Table 27 USB Bus Status Mask Register................................................................................................................. 30
Table 28 SIE Status Register ................................................................................................................................... 31
Table 29 SIE Status Mask Register.......................................................................................................................... 31
Table 30 USB Configuration Number Register......................................................................................................... 32
Table 31 Endpoint 0 Receive Control Register ........................................................................................................ 32
Table 32 Endpoint 0 Transmit Control Register ....................................................................................................... 32
Table 33 Endpoint 1 Receive Control Register ........................................................................................................ 32
Table 34 Endpoint 1 Transmit Control Register ....................................................................................................... 33
Table 35 Endpoint 2 Control Register ...................................................................................................................... 33
Table 36 Endpoint 0 Receive Byte Count Register .................................................................................................. 34
Table 37 Endpoint 0 Transmit Byte Count Register ................................................................................................. 35
Table 38 Endpoint 1 Receive Byte Count Register .................................................................................................. 35
Table 39 Endpoint 1 Transmit Byte Count Register ................................................................................................. 35
Table 40 RAM Buffer Write Byte Count Register A1................................................................................................ 35
Table 41 RAM BUFFER WRITE Byte Count Register A2 Register.......................................................................... 35
Table 42 RAM Buffer Write Byte Count Register B1................................................................................................ 35
Table 43 RAM Buffer Write Byte Count Register B2 Register.................................................................................. 36
Table 44 RAM Buffer Read Byte Count Register A1................................................................................................ 36
Table 45 RAM Buffer Read Byte Count Register A2 Register.................................................................................. 36
Table 46 RAM Buffer Read Byte Count Register B1................................................................................................ 36
Table 47 RAM Buffer Read Byte Count Register B2 Register.................................................................................. 36
Table 48 NAK Register (INT5).................................................................................................................................. 36
Table 49 NAK Mask Register ................................................................................................................................... 37
Table 50 USB Error Register.................................................................................................................................... 37
Table 51 MSB ATA Data Register............................................................................................................................ 38
Table 52 LSB ATA Data Register............................................................................................................................. 38
Table 53 ATA Transfer Count Register 0 ................................................................................................................. 38
Table 54 ATA Transfer Count Register 1 ................................................................................................................. 38
Table 55 ATA Transfer Count Register 2 ................................................................................................................. 38
Table 56 ATA Transfer Count Register 3 ................................................................................................................. 39
Table 57 ATA Control Register.................................................................................................................................. 39
Table 58 ATA Ultra DMA Timing Register................................................................................................................. 40
Table 59 IDE Timing Register .................................................................................................................................. 40
Table 60 ATA Slew Rate Control A Register............................................................................................................. 42
Table 61 ATA Slew Rate Control B Register............................................................................................................. 42
Table 62 IDE Transaction Timing............................................................................................................................. 45
Table 63 ULTRA ATA/66 Control Signal Assignments............................................................................................. 46
Table 64 Buffer SRAM Mapping................................................................................................................................ 48
Table 65 RAMWR_TOGGLE State Control.............................................................................................................. 51
SMSC DS USB97C201
Page 5
Rev. 03/25/2002
PRELIMINARY
FIGURES
Figure 1 - MCU to EXTERNAL CODE SPACE MAP ................................................................................................... 14
Figure 2 - GPIO MUXING BLOCK DIAGRAM ............................................................................................................. 23
Figure 3 - RECEIVE BUFFER OPERATION ............................................................................................................... 51
Figure 4 - TRANSMIT BUFFER OPERATION............................................................................................................. 52
Figure 5 - AUTOMATIC DATA TRANSFER OPERATION ......................................................................................... 53
Figure 6 - 100 PIN TQFP PACKAGE .......................................................................................................................... 57
Figure 7 100 PIN QFP PACKAGE............................................................................................................................ 58