i
TABLE OF CONTENTS
1.
GENERAL DESCRIPTION ................................................................................................................ 1
2.
FEATURES ........................................................................................................................................ 1
3.
ORDERING INFORMATION ............................................................................................................. 2
4.
BLOCK DIAGRAM ............................................................................................................................ 3
5.
DIE PAD COORDINATES ................................................................................................................. 4
6.
TAB PACKAGE PIN ASSIGNMENT................................................................................................. 9
SSD1702T1 TAB ..................................................................................................................................... 9
SSD1702T2 TAB ................................................................................................................................... 11
SSD1702T3 TAB ................................................................................................................................... 13
7.
PIN DESCRIPTION.......................................................................................................................... 15
VDD........................................................................................................................................................ 15
VSS ........................................................................................................................................................ 15
V0, V12, V43, V5 ................................................................................................................................... 15
S/C ......................................................................................................................................................... 15
MD.......................................................................................................................................................... 15
L/R ......................................................................................................................................................... 16
DISPOFF# ............................................................................................................................................. 16
D0 D7 .................................................................................................................................................. 16
XCK........................................................................................................................................................ 16
LP........................................................................................................................................................... 16
FR .......................................................................................................................................................... 17
EIO1, EIO2............................................................................................................................................. 17
Y1-Y240 ................................................................................................................................................. 17
8.
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 18
ii
Active control ....................................................................................................................................... 18
Data Control ......................................................................................................................................... 18
Data Latch............................................................................................................................................. 18
Data Latch Control............................................................................................................................... 18
Line Latch/Shift Register..................................................................................................................... 18
Level Shifter ......................................................................................................................................... 18
4-level Driver ........................................................................................................................................ 18
Control Logic........................................................................................................................................ 19
Power on reset ..................................................................................................................................... 19
9.
FUNCTIONAL OPERATIONS ......................................................................................................... 20
Output voltage level mapping ............................................................................................................ 20
10.
DISPLAY DATA AND DRIVER OUTPUT PINS MAPPING ............................................................ 22
11.
PRECAUTION.................................................................................................................................. 23
12.
MAXIMUM RATINGS....................................................................................................................... 24
13.
DC CHARACTERISTICS................................................................................................................. 25
14.
AC CHARACTERISTICS................................................................................................................. 27
15.
APPLICATION EXAMPLES OF COMMON DRIVERS ................................................................... 31
16.
APPLICATION EXAMPLES OF SEGMENT DRIVERS .................................................................. 33
17.
TIMING CHART OF CASCADE CONNECTION OF SEGMENT DRIVERS................................... 34
18.
APPLICATION EXAMPLES ............................................................................................................ 35
19.
TAB PACKAGE DETAIL DIMENSIONS ......................................................................................... 36
SSD1702T1 TAB ................................................................................................................................... 36
SSD1702T2 TAB ................................................................................................................................... 38
SSD1702T3 TAB ................................................................................................................................... 39
SSD1702T3 TAB ................................................................................................................................... 40
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a new product under definition stage. Solomon Systech Limited reserves
the right to change or discontinue this product without notice.
http://www.solomon-systech.com
SSD1702
Rev 1.0
P 1
Jun 2003
Copyright
2003 Solomon Systech Limited
SSD1702
Advance Information
240 Outputs Common / Segment Driver
CMOS
1. General Description
SSD1702 is a 240-outputs LCD driver capable of both COMMON or SEGMENT driving, selected by
hardware pin setting. It is designed for high resolution dot matrix type LCD panel for the use on PDA or
terminal.
SSD1702 can be used in cascade mode to support display system with more than 240 rows or columns.
In segment mode, 4-bit or 8-bit parallel input modes are available through pin selection.
2. FEATURES
BOTH SEGMENT AND COMMON MODE
Supply voltage for LC driver: +15.0 to +30.0 V
Supply voltage for logic system: +2.4 to +3.6 V
240 outputs for either common or segment driving
Pin selectable between common and segment mode
Low output impedance
Low power consumption
SEGMENT
MODE
Maximum XCK clock frequency: 20 MHz (VDD = +3.0 to +3.6V)
15 MHz (VDD = +2.4 to +3.0V)
Pin selectable 4-bit or 8-bit input modes
Automatic transfer function of enable signal
Automatically stop the internal clock after counting 240 bits of input data in chip select mode
Line latch circuit reset function when DISPOFF# active
COMMON MODE
Maximum LP clock frequency: 1 MHz (VDD = +2.4 to 3.6V)
Built-in 240 bits bi-directional shift register
Single (240 bits shift register) or Dual mode (two 120 bits shift register) operations
Shift register circuit reset function when DISPOFF# active
Solomon Systech
Jun 2003
P 2
Rev 1.0
SSD1702
3. ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number
Outerlead pitch (mm)
Package Form
SSD1702Z
N/A
Gold Bump Die
SSD1702T1R1 0.21
TAB
SSD1702T2R1 0.20
TAB
SSD1702T3R1 0.055
TAB
SSD1702
Rev 1.0
P 3
Jun 2003
Solomon Systech
4. BLOCK DIAGRAM
Figure 1 - Block Diagram of SSD1702
V
0
V
12
V
5
V
43
Y240 Y239.......................................................Y2 Y1
LEVEL
SHIFTER
240 BITS LEVEL SHIFTER
240 BITS 4-LEVEL DRIVER
ACTIVE
CONTROL
CONTROL
LOGIC
DATA CONTROL
240 BITS LINE LATCH / SHIFT REGISTER
DATA LATCH CONTROL
V
5
V
43
V
12
V
0
FR
DISPOFF#
EIO1
EIO2
LP
XCK
S/C
MD
L/R
4BITS*2
DATA
LATCH
240
8
240
8
8
8
8
8
D0
D2
D1
D3
D5
D4
D7
D6
VDD
VSS
...................................
POWER ON RESET
..............8 * 30...............
DATA LATCH
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