This document contains information on a new product under definition stage. Solomon Systech Ltd. reserves the
right to change or discontinue this product without notice.
http://www.solomon-systech.com
SSD1815B
Rev 1.6
Jul 2002
Copyright
2003
Solomon Systech Limited
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1815B
P 1/36
Advance Information
LCD Segment / Common Driver
with Controller
CMOS
SSD1815B is a single-chip CMOS LCD drivers with controllers for dot-matrix graphic liquid crystal display system.
SSD1815B is capable to drive 132 Segments, 64 Commons and 1 icon line by its 197 high voltage driving output.
SSD1815B display data directly from their internal 132 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands
are sent from common MCU through 8-bit Parallel or Serial Interface. The selection of whether 6800- or 8080-series compatible
Parallel Interface or Serial Peripheral Interface is done by hardware pins configuration.
SSD1815B embeds a DC-DC Converter, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of
external components. With the advanced design on minimizing power consumption and die/package layout, SSD1815B is suit-
able for any portable battery-driven applications requiring a long operation period with a compact size.
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 2/36
FEATURES
Dot-matrix Display with separated Icon Line, 132 x 64 + 1 Icon Line
Single Supply Operation, 2.4V ~ 3.5V
Minimum -12.0V LCD Driving Output Voltage
Low Current Sleep Mode
On-Chip Voltage Generator or External LCD Driving Power Supply Selectable
2X / 3X / 4X On-Chip DC-DC Converter
On-Chip Oscillator
Programmable Multiplex ratio in dot-matrix display area, 1Mux ~ 64Mux
On-Chip Bias Divider
Programmable bias ratio, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface
On-Chip 132 X 65 Graphic Display Data RAM
Re-mapping of Row and Column Drivers
Vertical Scrolling
Display Offset Control
64 Level Internal Contrast Control
External Contrast Control
Programmable LCD Driving Voltage Temperature Coefficients
Available in Gold Bump Die and TAB (Tape Automated Bonding) Package
ORDERING INFORMATION
Table 1 SSD1815B Ordering Information
Ordering Part
Number
Seg
Com
Default Bias
Package Form
Reference
SSD1815BZ
SSD1815BT
SSD1815BT2
132
64 + 1
1/9, 1/7
Gold Bump Die
70mm Folding TAB
48mm Folding TAB
Figure 2 on page 4
Figure 16 on page 31
Figure 18 on page 33
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 3/36
BLOCK DIAGRAM
Figure 1 SSD1815B Block Diagram
LCD Driving
Voltage Generator
2X / 3X / 4X
DC/DC Converter,
Voltage Regulator,
Bias Divider,
Contrast Control,
Temperature
Compensation
ROW0 ~
ROW63
SEG0~SEG131
M
CL
V
SS
V
D D
RES
D
7
V
L6
V
L2
C
1P
GDDRAM
132 X 65 Bits
Command Decoder
Parallel / Serial Interface
Command Interface
Display
Timing
Generator
Display Data Latch
HV Buffer Cell Level Shifter
Level
Selector
CS1
Oscillator
MSTAT
DOF
M/S
P/S
CS2 D/C
D
6
D
5
D
4
D
3
D
2
D
1
D
0
(SDA)(SCK)
V
DD
CLS
C68/80
E
(RD)
R/W
(WR)
ICONS
V
L5
V
L4
V
L3
C
1N
C
2N
C
2P
C
3N
IRS
HPM
V
FS
V
SS1
V
F
V
EE
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 4/36
PIN ARRANGEMENT
Figure 2 SSD1815B Gold Bump Die Pin Assignment
I
C
O
N
S
R
O
W
0
R
O
W
1
R
O
W
2
R
O
W
3
R
O
W
4
R
O
W
5
R
O
W
6
R
O
W
7
R
O
W
8
R
O
W
9
R
O
W
1
0
R
O
W
1
1
R
O
W
1
2
R
O
W
1
3
R
O
W
1
4
R
O
W
1
5
R
O
W
1
6
R
O
W
1
7
R
O
W
1
8
R
O
W
1
9
ROW20
ROW21
:
:
ROW30
ROW31
VDD
IRS
VSS
/HPM
VDD
P/S
C68/80
VSS
CLS
M/S
VDD
NC
NC
VDD
VDD
VF
VF
VL6
VL6
VL6
VL5
VL5
VL4
VL4
VL4
VL3
VL3
VL3
VL2
VL2
VDD
VDD
VFS
VFS
VSS
VSS
C2P
C2P
C2P
C2N
C2N
C2N
C2N
C1N
C1N
C1N
C1P
C1P
C1P
C3N
C3N
C3N
C3N
VEE
VEE
VEE
VEE
VSS1
VSS1
VSS1
VSS1
VSS
VSS
VSS
VDD
VDD
VDD
VDD
D7 (SDA)
D6 (SCK)
D5
D4
D3
D2
D1
D0
VDD
E(/RD)
R/W(/WR)
VSS
D/C
/RES
VDD
CS2
/CS1
VSS
/DOF
CL
M
MSTAT
NC
ICONS
ROW63
ROW62
ROW61
:
:
ROW54
ROW53
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
PIN #1
R
O
W
3
2
R
O
W
3
3
R
O
W
3
4
R
O
W
3
5
R
O
W
3
6
R
O
W
3
7
R
O
W
3
8
R
O
W
3
9
R
O
W
4
0
R
O
W
4
1
R
O
W
4
2
R
O
W
4
3
R
O
W
4
4
R
O
W
4
5
R
O
W
4
6
R
O
W
4
7
R
O
W
4
8
R
O
W
4
9
R
O
W
5
0
R
O
W
5
1
R
O
W
5
2
:
:
:
:
1
115
137
268
C
e
n
t
e
r
:
3
8
1
6
.
0
5
,
-
3
0
5
.
2
S
i
z
e
:
1
0
0
.
1
u
x
1
0
0
.
1
u
C
e
n
t
e
r
:
3
8
1
9
.
2
,
-
4
1
9
.
2
S
i
z
e
:
9
9
.
7
5
u
x
9
9
.
7
5
u
C
e
n
t
e
r
:
3
7
0
1
.
0
7
5
,
-
3
0
4
.
5
R
a
d
i
u
s
:
5
0
.
9
2
5
u
Gold Bump Alignment Mark
This alignment mark contains gold bump for IC
bumping process alignment and IC identifica-
tions. No conductive tracks should be laid under-
neath this mark to avoid short circuit.
C
e
n
t
e
r
:
-
3
8
8
0
.
6
2
5
,
2
0
5
.
6
2
5
S
i
z
e
:
9
9
.
7
5
u
x
9
9
.
7
5
u
Note:
1. This diagram showing Die Face Up view.
2. Coordinates and Size of all alignment marks
are in unit um and w.r.t. center of the chip.
x
Y
(
0
,
0
)
C
e
n
t
e
r
:
3
8
9
.
7
2
5
,
-
2
0
1
.
6
R
a
d
i
u
s
:
2
7
.
1
2
5
u
Die Size:
10.977mm X 1.912mm
Die Thickness:
550 +/-25um
Bump Pitch:
76.2 um [Min]
Bump Height:
Nominal 18um
Tolerance <4um within die
<8um within lot
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 5/36
Table 2 SSD1815B Gold Bump Die Pad Coordinates
PAD #
NAME
X
Y
PAD #
N A M E
X
Y
PAD #
N A M E
X
Y
1
ROW53
-4958.45
-751.98
61
C2N
266.70
-771.93
116
ROW19
5285.18
-768.78
2
ROW54
-4882.15
-751.98
62
C2N
355.60
-771.93
117
ROW18
5285.18
-692.48
3
ROW55
-4805.85
-751.98
63
C2N
444.50
-771.93
118
ROW17
5285.18
-616.18
4
ROW56
-4729.55
-751.98
64
C2N
533.40
-771.93
119
ROW16
5285.18
-539.88
5
ROW57
-4653.25
-751.98
65
C2P
622.30
-771.93
120
ROW15
5285.18
-463.58
6
ROW58
-4576.95
-751.98
66
C2P
711.20
-771.93
121
ROW14
5285.18
-387.28
7
ROW59
-4500.65
-751.98
67
C2P
800.10
-771.93
122
ROW13
5285.18
-310.98
8
ROW60
-4424.35
-751.98
68
V S S
889.00
-771.93
123
ROW12
5285.18
-234.68
9
ROW61
-4348.05
-751.98
69
V S S
977.90
-771.93
124
ROW11
5285.18
-158.38
10
ROW62
-4271.75
-751.98
70
V F S
1066.80
-771.93
125
ROW10
5285.18
-82.08
11
ROW63
-4195.45
-751.98
71
V F S
1155.70
-771.93
126
R O W 9
5285.18
-5.78
12
ICONS
-4119.15
-751.98
72
VDD
1244.60
-771.93
127
R O W 8
5285.18
70.53
13
N C
-4000.50
-771.93
73
VDD
1333.50
-771.93
128
R O W 7
5285.18
146.83
14
M S T A T
-3911.60
-771.93
74
VL2
1422.40
-771.93
129
R O W 6
5285.18
223.13
15
M
-3822.70
-771.93
75
VL2
1511.30
-771.93
130
R O W 5
5285.18
299.43
16
C L
-3733.80
-771.93
76
VL3
1600.20
-771.93
131
R O W 4
5285.18
375.73
17
/DOF
-3644.90
-771.93
77
VL3
1689.10
-771.93
132
R O W 3
5285.18
452.03
18
VSS
-3556.00
-771.93
78
VL3
1778.00
-771.93
133
R O W 2
5285.18
528.33
19
/CS1
-3467.10
-771.93
79
VL4
1866.90
-771.93
134
R O W 1
5285.18
604.63
20
CS2
-3378.20
-771.93
80
VL4
1955.80
-771.93
135
R O W 0
5285.18
680.93
21
VDD
-3289.30
-771.93
81
VL4
2044.70
-771.93
136
ICONS
5285.18
757.23
22
/RES
-3200.40
-771.93
82
VL5
2133.60
-771.93
23
D/C
-3111.50
-771.93
83
VL5
2222.50
-771.93
24
VSS
-3022.60
-771.93
84
VL6
2311.40
-771.93
25
R/W
-2933.70
-771.93
85
VL6
2400.30
-771.93
26
E/RD
-2844.80
-771.93
86
VL6
2489.20
-771.93
27
VDD
-2755.90
-771.93
87
V F
2578.10
-771.93
28
D 0
-2667.00
-771.93
88
VF
2667.00
-771.93
29
D 1
-2578.10
-771.93
89
VDD
2755.90
-771.93
30
D 2
-2489.20
-771.93
90
VDD
2844.80
-771.93
31
D 3
-2400.30
-771.93
91
NC
2933.70
-771.93
32
D 4
-2311.40
-771.93
92
NC
3022.60
-771.93
33
D 5
-2222.50
-771.93
93
VDD
3111.50
-771.93
34
D 6
-2133.60
-771.93
94
M/S
3200.40
-771.93
35
D 7
-2044.70
-771.93
95
CLS
3289.30
-771.93
36
VDD
-1955.80
-771.93
96
V S S
3378.20
-771.93
37
VDD
-1866.90
-771.93
97
C68/80
3467.10
-771.93
38
VDD
-1778.00
-771.93
98
P/S
3556.00
-771.93
39
VDD
-1689.10
-771.93
99
VDD
3644.90
-771.93
40
VSS
-1600.20
-771.93
100
/ H P M
3733.80
-771.93
41
VSS
-1511.30
-771.93
101
V S S
3822.70
-771.93
42
VSS
-1422.40
-771.93
102
IRS
3911.60
-771.93
43
V S S 1
-1333.50
-771.93
103
VDD
4000.50
-771.93
44
V S S 1
-1244.60
-771.93
104
ROW31
4119.15
-751.98
45
V S S 1
-1155.70
-771.93
105
ROW30
4195.45
-751.98
46
V S S 1
-1066.80
-771.93
106
ROW29
4271.75
-751.98
47
VEE
-977.90
-771.93
107
ROW28
4348.05
-751.98
48
VEE
-889.00
-771.93
108
ROW27
4424.35
-751.98
49
VEE
-800.10
-771.93
109
ROW26
4500.65
-751.98
50
VEE
-711.20
-771.93
110
ROW25
4576.95
-751.98
51
C 3 N
-622.30
-771.93
111
ROW24
4653.25
-751.98
52
C 3 N
-533.40
-771.93
112
ROW23
4729.55
-751.98
53
C 3 N
-444.50
-771.93
113
ROW22
4805.85
-751.98
54
C 3 N
-355.60
-771.93
114
ROW21
4882.15
-751.98
55
C1P
-266.70
-771.93
115
ROW20
4958.45
-751.98
56
C1P
-177.80
-771.93
57
C1P
-88.90
-771.93
58
C 1 N
0.00
-771.93
59
C 1 N
88.90
-771.93
60
C 1 N
177.80
-771.93
Die Size:
10.977mm
X
1.912mm
Bump Size:
Pad #
X [ u m ]
Y [um]
Pad #
X [um]
Y [um]
Pad #
X [ u m ]
Y [um]
Pad #
X [um]
Y [ u m ]
1 - 12
43.5
101.6
116 - 136
101.6
43.5
137 - 268
43.5
101.6
269 - 289
101.6
43.5
13 - 103
61.7
61.7
104 - 115
43.5
101.6
x
Y
(0,0)
PIN 1
PIN115
PIN137
PIN268
Gold bump width tolerance: +/- 3um.
Die Size: 10.977mm X 1.912mm
Bump Height:
- nominal: 18um
- tolerance:<4um (within die)
<6um (within wafer)
<8um (within lot)
Unit in um unless otherwise specified.
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 6/36
PAD #
NAME
X
Y
PAD #
NAME
X
Y
PAD #
NAME
X
Y
137
SEG0
4997.65
751.98
203
SEG66
-38.15
751.98
269
ROW32
-5285.18
757.23
138
SEG1
4921.35
751.98
204
SEG67
-114.45
751.98
270
ROW33
-5285.18
680.93
139
SEG2
4845.05
751.98
205
SEG68
-190.75
751.98
271
ROW34
-5285.18
604.63
140
SEG3
4768.75
751.98
206
SEG69
-267.05
751.98
272
ROW35
-5285.18
528.33
141
SEG4
4692.45
751.98
207
SEG70
-343.35
751.98
273
ROW36
-5285.18
452.03
142
SEG5
4616.15
751.98
208
SEG71
-419.65
751.98
274
ROW37
-5285.18
375.73
143
SEG6
4539.85
751.98
209
SEG72
-495.95
751.98
275
ROW38
-5285.18
299.43
144
SEG7
4463.55
751.98
210
SEG73
-572.25
751.98
276
ROW39
-5285.18
223.13
145
SEG8
4387.25
751.98
211
SEG74
-648.55
751.98
277
ROW40
-5285.18
146.83
146
SEG9
4310.95
751.98
212
SEG75
-724.85
751.98
278
ROW41
-5285.18
70.53
147
SEG10
4234.65
751.98
213
SEG76
-801.15
751.98
279
ROW42
-5285.18
-5.78
148
SEG11
4158.35
751.98
214
SEG77
-877.45
751.98
280
ROW43
-5285.18
-82.08
149
SEG12
4082.05
751.98
215
SEG78
-953.75
751.98
281
ROW44
-5285.18
-158.38
150
SEG13
4005.75
751.98
216
SEG79
-1030.05
751.98
282
ROW45
-5285.18
-234.68
151
SEG14
3929.45
751.98
217
SEG80
-1106.35
751.98
283
ROW46
-5285.18
-310.98
152
SEG15
3853.15
751.98
218
SEG81
-1182.65
751.98
284
ROW47
-5285.18
-387.28
153
SEG16
3776.85
751.98
219
SEG82
-1258.95
751.98
285
ROW48
-5285.18
-463.58
154
SEG17
3700.55
751.98
220
SEG83
-1335.25
751.98
286
ROW49
-5285.18
-539.88
155
SEG18
3624.25
751.98
221
SEG84
-1411.55
751.98
287
ROW50
-5285.18
-616.18
156
SEG19
3547.95
751.98
222
SEG85
-1487.85
751.98
288
ROW51
-5285.18
-692.48
157
SEG20
3471.65
751.98
223
SEG86
-1564.15
751.98
289
ROW52
-5285.18
-768.78
158
SEG21
3395.35
751.98
224
SEG87
-1640.45
751.98
159
SEG22
3319.05
751.98
225
SEG88
-1716.75
751.98
160
SEG23
3242.75
751.98
226
SEG89
-1793.05
751.98
161
SEG24
3166.45
751.98
227
SEG90
-1869.35
751.98
162
SEG25
3090.15
751.98
228
SEG91
-1945.65
751.98
163
SEG26
3013.85
751.98
229
SEG92
-2021.95
751.98
164
SEG27
2937.55
751.98
230
SEG93
-2098.25
751.98
165
SEG28
2861.25
751.98
231
SEG94
-2174.55
751.98
166
SEG29
2784.95
751.98
232
SEG95
-2250.85
751.98
167
SEG30
2708.65
751.98
233
SEG96
-2327.15
751.98
168
SEG31
2632.35
751.98
234
SEG97
-2403.45
751.98
169
SEG32
2556.05
751.98
235
SEG98
-2479.75
751.98
170
SEG33
2479.75
751.98
236
SEG99
-2556.05
751.98
171
SEG34
2403.45
751.98
237
SEG100 -2632.35
751.98
172
SEG35
2327.15
751.98
238
SEG101 -2708.65
751.98
173
SEG36
2250.85
751.98
239
SEG102 -2784.95
751.98
174
SEG37
2174.55
751.98
240
SEG103 -2861.25
751.98
175
SEG38
2098.25
751.98
241
SEG104 -2937.55
751.98
176
SEG39
2021.95
751.98
242
SEG105 -3013.85
751.98
177
SEG40
1945.65
751.98
243
SEG106 -3090.15
751.98
178
SEG41
1869.35
751.98
244
SEG107 -3166.45
751.98
179
SEG42
1793.05
751.98
245
SEG108 -3242.75
751.98
180
SEG43
1716.75
751.98
246
SEG109 -3319.05
751.98
181
SEG44
1640.45
751.98
247
SEG110 -3395.35
751.98
182
SEG45
1564.15
751.98
248
SEG111 -3471.65
751.98
183
SEG46
1487.85
751.98
249
SEG112 -3547.95
751.98
184
SEG47
1411.55
751.98
250
SEG113 -3624.25
751.98
185
SEG48
1335.25
751.98
251
SEG114 -3700.55
751.98
186
SEG49
1258.95
751.98
252
SEG115 -3776.85
751.98
187
SEG50
1182.65
751.98
253
SEG116 -3853.15
751.98
188
SEG51
1106.35
751.98
254
SEG117 -3929.45
751.98
189
SEG52
1030.05
751.98
255
SEG118 -4005.75
751.98
190
SEG53
953.75
751.98
256
SEG119 -4082.05
751.98
191
SEG54
877.45
751.98
257
SEG120 -4158.35
751.98
192
SEG55
801.15
751.98
258
SEG121 -4234.65
751.98
193
SEG56
724.85
751.98
259
SEG122 -4310.95
751.98
194
SEG57
648.55
751.98
260
SEG123 -4387.25
751.98
195
SEG58
572.25
751.98
261
SEG124 -4463.55
751.98
196
SEG59
495.95
751.98
262
SEG125 -4539.85
751.98
197
SEG60
419.65
751.98
263
SEG126 -4616.15
751.98
198
SEG61
343.35
751.98
264
SEG127 -4692.45
751.98
199
SEG62
267.05
751.98
265
SEG128 -4768.75
751.98
200
SEG63
190.75
751.98
266
SEG129 -4845.05
751.98
201
SEG64
114.45
751.98
267
SEG130 -4921.35
751.98
202
SEG65
38.15
751.98
268
SEG131 -4997.65
751.98
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 7/36
PIN DESCRIPTIONS
MSTAT
This pin is the static indicator driving output. It is only active
in master operation. The frame signal output pin, M, should be
used as the back plane signal for the static indicator.
The duration of overlapping could be programmable. See
Extended Command Table for details.
This pin becomes high impedance if the chip is operating in
slave mode.
M
This pin is the frame signal input/output. In master mode,
the pin supplies frame signal to slave devices while in slave
mode, the pin receives frame signal from the master device.
CL
This pin is the display clock input/output. In master mode
with internal oscillator enabled (CLS pin pulled high), this pin
supplies display clock signal to slave devices.
In slave mode or when internal oscillator is disabled, the pin
receives display clock signal from the master device or external
clock source.
DOF
This pin is display blanking control between master and
slave devices. In master mode, this pin supplies on/off signal to
slave devices. In slave mode, this pin receives on/off signal from
the master device.
CS1, CS2
These pins are the chip select inputs. The chip is enabled
for MCU communication only when both CS1 is pulled low and
CS2 is pulled high.
RES
This pin is reset signal input. Initialization of the chip is start-
ed once this pin is pulled low. Minimum pulse width for complet-
ing the reset procedure is 5us.
D/C
This pin is Data/Command control pin. When the pin is
pulled high, the data at D
7
-D
0
is treated as display data. When
the pin is pulled low, the data at D
7
-D
0
will be transferred to the
command register. Details relationship with other MCU interface
signals, please refer to the Timing Characteristics Diagrams.
R/W(WR)
This pin is MCU interface input. When interfacing to an
6800-series microprocessor, this pin will be used as Read/Write
(R/W) selection input. Read mode will be carried out when this
pin is pulled high and write mode when low.
When interfacing to an 8080-microprocessor, this pin will be
the Write (WR) input. Data write operation is initiated when this
pin is pulled low when the chip is selected.
E(RD)
This pin is MCU interface input. When interfacing to an
6800-series microprocessor, this pin will be used as the Enable
(E) signal. Read/write operation is initiated when this pin is
pulled high when the chip is selected.
When connecting to an 8080-microprocessor, this pin re-
ceives the Read (RD) signal. Data read operation is initiated
when this pin is pulled low when the chip is selected.
D
7
-D
0
These pins are the 8-bit bi-directional data bus to be con-
nected to the MCU in parallel interface mode. D
7
is the MSB
while D
0
is the LSB.
When serial mode is selected, D
7
is the serial data input
(SDA) and D
6
is the serial clock input (SCK).
V
DD
Chip's Power Supply pin. This is also the reference for the
DC-DC Converter output and LCD driving voltages.
V
SS
Ground. A reference for the logic pins.
V
SS1
Input for internal DC-DC converter. The voltage of generat-
ed, V
EE
, equals to the multiple factor times the potential different
between this pin, V
SS1
, and V
DD
. The multiple factor, 2X, 3X or
4X, is selected by different connections of the external capaci-
tors. All voltage levels are referenced to V
DD
.
Note: the potential at this input pin must lower than or equal
to V
SS
.
V
EE
This is the most negative voltage supply pin of the chip. It
can be supplied externally or generated by the internal DC-DC
converter, by turning on the internal voltage booster option in
the Set Power Control Register command.
When using internal DC-DC converter as generator, voltage
at this pin is for internal reference only. It CANNOT be used for
driving external circuitries.
C
3N
, C
1P
, C
1N
, C
2N
and C
2P
When internal DC-DC voltage converter is used, external
capacitor(s) is/are connected between these pins. Different con-
nection will result in different DC-DC converter multiple factor,
2X, 3X or 4X. Detail connections please refer to voltage convert-
er section in the functional block description.
V
FS
This is an input pin to provide an external voltage reference
for the internal voltage regulator. The function of this pin is only
enabled for the External Input chip models which are required
special ordering. For normal chip model, please leave this pin
NC (No connection).
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 8/36
V
L2
, V
L3
, V
L4
and V
L5
These are the LCD driving voltage levels. All these levels
are referenced to V
DD
.
They can be supplied externally or generated by the internal
bias divider, by turning on the output op-amp buffers option in
the Set Power Control Register command.
The potential relation of these pins are given as:
V
DD
> V
L2
> V
L3
> V
L4
> V
L5
> V
L6
and with bias factor, a,
V
L2
- V
DD
= 1/a * (V
L6
- V
DD
)
V
L3
- V
DD
= 2/a * (V
L6
- V
DD
)
V
L4
- V
DD
= (a-2)/a * (V
L6
- V
DD
)
V
L5
- V
DD
= (a-1)/a * (V
L6
- V
DD
)
V
L6
This pin is the most negative LCD driving voltage. It can be
supplied externally or generated by turning on the internal reg-
ulator option in the Set Power Control Register command.
V
F
This pin is the input of the built-in voltage regulator for gen-
erating V
L6
.
When external resistor network is selected (IRS pulled low)
to generate the LCD driving level, V
L6
, two external resistors, R
1
and R
2
, should be connected between V
DD
and V
F
, and V
F
and
V
L6
, respectively (see application circuit diagrams).
M/S
This pin is the master/slave mode selection input. When this
pin is pulled high, master mode is selected, which CL, M,
MSTAT and DOF signals will be output for slave devices.
When this pin is pulled low, slave mode is selected, which
CL, M, DOF are required to be input from master device and
MSTAT is high impedance.
CLS
This pin is the internal clock enable pin. When this pin is
pulled high, internal clock is enabled.
The internal clock will be disabled when it is pulled low, an
external clock source must be input to CL pin for normal opera-
tion.
C68/80
This pin is MCU parallel interface selection input. When the
pin is pulled high, 6800 series interface is selected and when the
pin is pulled low, 8080 series interface is selected.
If Serial Interface is selected (P/S pulled low), the setting of
this pin is ignored, but must be connected to a known logic (ei-
ther high or low).
P/S
This pin is serial/parallel interface selection input. When this
pin is pulled high, parallel interface mode is selected. When it is
pulled low, serial interface will be selected.
Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/W/
(WR), E/(RD) is recommended to be connected to Vss.
Note2: Read Back operation is only available in parallel
mode.
HPM
This pin is the control input of High Power Current Mode.
The function of this pin is only enabled for High Power model
which required special ordering.
For normal models, High Power Mode is disabled and the
LCD driving characteristics are the same no matter this pin is
pulled High or Low.
Note: This pin must be pulled to either High or Low. Leaving
this pin floating is prohibited.
IRS
This is the input pin to enable the internal resistors network
for the voltage regulator. When this pin is pulled high, the internal
feedback resistors of the internal regulator for generating V
L6
will
be enabled.
When it is pulled low, external resistors, R
1
and R
2
, should
be connected to V
DD
and V
F
, and V
F
and V
L6
, respectively (see
application circuit diagrams).
ROW0 - ROW63
These pins provide the Common driving signals to the LCD
panel. See Table 3 on page 9 for the COM signal mapping in
SSD1815B.
SEG0 - SEG131
These pins provide the LCD segment driving signals. The
output voltage level of these pins is V
DD
during sleep mode and
standby mode.
ICONS
There are two ICONS pins (pin12 and 136) on the chip. Both
pins output exactly the same signal. The reason for duplicating
the pin is to enhance the flexibility of the LCD layout.
NC
These are the No Connection pins. Nothing should be con-
nected to these pins, nor they are connected together. These
pins should be left open individually.
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 9/36
Table 3 ROW pin assignments for COM signals for SSD1815B .
Die Pad Name
SSD1815B
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
ROW9
ROW10
ROW11
ROW12
ROW13
ROW14
ROW15
ROW16
ROW17
ROW18
ROW19
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
ROW20
ROW21
ROW22
ROW23
ROW24
ROW25
ROW26
ROW27
ROW28
ROW29
ROW30
ROW31
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
ROW44
ROW45
ROW46
ROW47
ROW48
ROW49
ROW50
ROW51
ROW52
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
ROW53
ROW54
ROW55
ROW56
ROW57
ROW58
ROW59
ROW60
ROW61
ROW62
ROW63
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 10/36
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpret-
ed as data or command. Data is directed to this module based
upon the input of the D/C pin.
If D/C pin is high, data is written to Graphic Display Data
RAM (GDDRAM). If it low, the input at D
7
-D
0
is interpreted as a
Command and it will be decoded and be written to the corre-
sponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins
(D
7
-D
0
), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input
high indicates a read operation from the Graphic Display Data
RAM (GDDRAM) or the status register. R/W(WR) input Low in-
dicates a write operation to Display Data RAM or Internal Com-
mand Registers depending on the status of D/C input. The
E(RD) input serves as data latch signal (clock) when high provid-
ed that CS1 and CS2 are low and high respectively. Refer to Fig-
ure 11 on page 26 for Parallel Interface Timing Diagram of 6800-
series microprocessors.
In order to match the operating frequency of the GDDRAM
with that of the MCU, some pipeline processing is internally per-
formed which requires the insertion of a dummy read before the
first actual display data read. This is shown in Figure 3.
Figure 3 Display Data Read Back Procedure - Insertion of Dummy Read
R/W(WR)
E(RD)
N
n
n+1
n+2
data bus
write column address
dummy read
data read1
data read 2
data read 3
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins
(D
7
-D
0
), E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input
serves as data read latch signal (clock) when low provided that
CS1 and CS2 are low and high respectively. Whether it is display
data or status register read is controlled by D/C. R/W(WR) input
serves as data write latch signal(clock) when high provided that
CS1 and CS2 are low and high respectively. Whether it is display
data or command register write is controlled by D/C. Refer to
Figure 12 on page 27 for Parallel Interface Timing Diagram of
8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also re-
quired before the first actual display data read.
MPU Serial interface
The serial interface consists of serial clock SCK (D
6
), serial
data SDA (D
7
), D/C, CS1 and CS2. SDA is shifted into a 8-bit
shift register on every rising edge of SCK in the order of D
7
, D
6
,...
D
0
. D/C is sampled on every eighth clock to determine whether
the data byte in the shift register is written to the Display Data
RAM or command register at the same clock. Refer to Figure 13
on Page28 for Serial Interface Timing Diagram.
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 11/36
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC
voltage converter. This clock is also used in the Display Timing Generator.
Figure 4 Oscillator Circuitry
Oscillation Circuit
enable
OSC1
OSC2
Internal resistor
Oscillator enable
Buffer
enable
(CL)
(CLS)
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for
display driving output. With reference to V
DD
, it takes a sin-
gle supply input, V
SS
, and generate necessary voltage lev-
els. This block consists of:
1. 2X, 3X and 4X DC-DC voltage converter
The built-in DC-DC voltage converter is used to gener-
ate the large negative voltage supply with reference to VDD
from the voltage input (VSS1). SSD1815B is possible to
produce 2X, 3X or 4X boosting from the potential different
between V
SS1
- V
DD
.
Detail configurations of the DC-DC converter for differ-
ent boosting multiples are given in Figure 5.
2. Voltage Regulator (Voltages referenced to V
DD
)
The feedback gain control for LCD driving contrast
curves can be selected by IRS pin to either internal (IRS pin
= H) or external (IRS pin = L).
If internal resistor network is enabled, eight settings
can be selected through software command.
If external control is selected, external resistors are re-
quired to be connected between V
DD
and V
F
(R1), and be-
tween V
F
and V
L6
(R2). See application circuit diagrams for
detail connections.
Figure 5 DC-DC Converter Configurations
SSD1815B
C
3N
C
1P
C
1N
C
2P
C
2N
V
EE
Remarks:
1. C1 = 0.47 - 1.0uF
2. Boosting input from V
SS1
.
3. V
SS1
should be lower potential than or equal to V
SS
4. All voltages are referenced to V
DD
V
SS1
+
C1
C1
+
SSD1815B
C
3N
C
1P
C
1N
C
2P
C
2N
V
EE
V
SS1
+
C1
C1
+
C1
+
SSD1815B
C
3N
C
1P
C
1N
C
2P
C
2N
V
EE
V
SS1
+
C1
C1
+
C1
+
C1
+
2X Boosting Configuration
3X Boosting Configuration
4X Boosting Configuration
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 12/36
3. Contrast Control (Voltages referenced to V
DD
)
Software control of the 64 contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving
voltage is given as:
where
*Note: There may be a calculation error of max. 6% when comparing with measurement values.
Figure 6 Voltage Regulator Output for Different Gain/Contrast Settings
)
1
)
(
(
)
1
(
6
R
V
V
R
V
V
V
Contrast
Gain
V
V
SS
DD
ref
DD
L
BE
ref
+
-
+
=
+
=
-
Int. Reg.
Resistor
Ratio Setting
0
1
2
3
4
5
6
7
Ext.
Resistor
Gain
-3.37
-3.87
-4.43
-4.99
-5.58
-6.00
-6.67
-7.27 -(1+R
2
/R
1
)
Beta
96.79
96.53
96.33
96.06
95.78
95.54
95.26
95.02
97.62
TC
0
(-0.01%/C)
2
(-0.15%/C)
4
(-0.20%/C)
7
(-0.30%/C)
VBE
0.02
0.52
0.52
0.51
R
0.73
0.43
0.27
0.12
VL6 vs CONTRAST SETTINGS
-15.0000
-13.0000
-11.0000
-9.0000
-7.0000
-5.0000
-3.0000
0
10
20
30
40
50
60
Contrast level at VDD = 2.775V
VL6 [V]
IR=20H
IR=21H
IR=22H
IR=23H
IR=24H
IR=25H
IR=26H
IR=27H
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 13/36
given by:
Display is turned OFF
Default Display Display Mode, 132 x 64 + 1 Icon
Line
Normal segment and display data column address
mapping (Seg0 mapped to Row address 00h)
Read-modify-write mode is OFF
Power control register is set to 000b
Shift register data clear in serial interface
Bias ratio is set to default, 1/9
Static indicator is turned OFF
Display start line is set to GDDRAM column 0
Column address counter is set to 00h
Page address is set to 0
Normal scan direction of the COM outputs
Contrast control register is set to 20h
Test mode is turned OFF
Temperature Coefficient is set to TC0
Note: Please find more explanation in the Applications Note at-
tached at the back of the specification.
Display Data Latch
This block is a series of latches carrying the display signal
information. These latches hold the data, which will be fed to the
HV Buffer Cell and Level Selector to output the required voltage
level.
The numbers of latches are given by: 132 + 65 = 197
HV Buffer Cell (Level Shifter)
HV Buffer Cell work as a level shifter which translates the
low voltage output signal to the required driving voltage. The out-
put is shifted out with an internal FRM clock which comes from
the Display Timing Generator. The voltage levels are given by
the level selector which is synchronized with the internal M sig-
nal.
Level Selector
Level Selector is a control of the display synchronization.
Display voltage levels can be separated into two sets and used
with different cycles. Synchronization is important since it se-
lects the required LCD voltage level to the HV Buffer Cell, which
in turn outputs the COM or SEG LCD waveform.
LCD Panel Driving Waveform
Figure 9 on page 15 is an example of how the Common and
Segment drivers may be connected to a LCD panel. The wave-
forms provided illustrates the desired multiplex scheme.
4. Bias Divider
If the output op-amp buffer option in Set Power Control Reg-
ister command is enabled, this circuit block will divide the regu-
lator output (V
L6
) to give the LCD driving levels (V
L2
- V
L5
).
A low power consumption circuit design in this bias divider
saves most of the display current comparing to traditional de-
sign.
Stablizing Capacitors (0.01~0.47uF) are required to be con-
nected between these voltage level pins (V
L2
- V
L5
) and V
DD
. If
the LCD panel loading is heavy, four additional resistors are sug-
gested to add to the application circuit as follows:
5. Bias Ratio Selection circuitry
SSD1815B can be software selected one of the bias ratios
from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9.
Since there will be slightly different in command pattern for
different members, please refer to Command Descriptions sec-
tion of this data sheet.
6. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to sat-
isfy various liquid crystal temperature grades by software con-
trol. Default temperature coefficient (TC) setting is TC0.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit
pattern to be displayed. The size of the RAM is 132 x 65 = 8580
bits. Figure 8 on page 14 is a description of the GDDRAM ad-
dress map.
For mechanical flexibility, re-mapping on both Segment and
Common outputs can be selected by software.
For vertical scrolling of the display, an internal register stor-
ing display start line can be set to control the portion of the RAM
data to be mapped to the display. Figure 8 on page 14 shows the
case in which the display start line register is set to 38h.
For those GDDRAM out of the display common range, they
could still be accessed, for either preparation of vertical scrolling
data or even for the system usage.
Reset Circuit
This block includes Power On Reset circuitry and the hard-
ware reset pin, RES. Both of these having the same reset func-
tion. Once RES receives a negative reset pulse, all internal
circuitry will start to initialize. Minimum pulse width for complet-
ing the reset sequence is 5us. Status of the chip after reset is
Figure 7 Connections for heavy loading applications
SSD1815B
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
R3
R1
R2
R4
+
V
D D
C5
+ C4
+ C3
+ C2
+ C1
Remark: 1. C1 ~ C5 = 0.01 ~ 0.47uF
2. R1 ~ R4 = 100k~ 1M
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 14/36
Figure 8 Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h.
Normal
00h
01h
02h
03h
80h
81h
82h
83h
Remapped
83h
8 2 h
81h
80h
03h
02h
01h
00h
00h
D0 (LSB)
8
55
01h
D1
9
54
02h
D2
10
53
03h
D3
11
52
04h
D4
12
51
05h
D5
13
50
06h
D6
14
4 9
07h
D7 (MSB)
15
4 8
08h
D0 (LSB)
16
4 7
09h
D1
17
4 6
0Ah
D2
18
4 5
0Bh
D3
19
4 4
0Ch
D4
20
4 3
0Dh
D5
21
4 2
0Eh
D6
22
4 1
0Fh
D7 (MSB)
23
4 0
10h
D0 (LSB)
24
3 9
11h
D1
25
3 8
12h
D2
26
3 7
13h
D3
27
3 6
14h
D4
28
3 5
15h
D5
29
3 4
16h
D6
30
3 3
17h
D7 (MSB)
31
3 2
18h
D0 (LSB)
32
3 1
19h
D1
33
3 0
1Ah
D2
34
2 9
1Bh
D3
35
2 8
1Ch
D4
36
2 7
1Dh
D5
37
2 6
1Eh
D6
38
2 5
1Fh
D7 (MSB)
39
2 4
20h
D0 (LSB)
40
2 3
21h
D1
41
2 2
22h
D2
42
2 1
23h
D3
43
2 0
24h
D4
44
19
25h
D5
45
18
26h
D6
46
17
27h
D7 (MSB)
47
16
28h
D0 (LSB)
48
15
29h
D1
49
14
2Ah
D2
50
13
2Bh
D3
51
12
2Ch
D4
52
11
2Dh
D5
53
10
2Eh
D6
54
9
2Fh
D7 (MSB)
55
8
30h
D0 (LSB)
56
7
31h
D1
57
6
32h
D2
58
5
33h
D3
59
4
34h
D4
60
3
35h
D5
61
2
36h
D6
62
1
37h
D7 (MSB)
63
0
38h
D0 (LSB)
0
6 3
39h
D1
1
6 2
3Ah
D2
2
6 1
3Bh
D3
3
6 0
3Ch
D4
4
59
3Dh
D5
5
58
3Eh
D6
6
57
3Fh
D7 (MSB)
7
56
Page 8
D0 (LSB)
ICONS
ICONS
Segment Pins
0
1
2
3
128
129
130
131
RAM
Row
Normal
Remapped
SSD1815
Common Pins
RAM
Column
Page 6
Page 7
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 15/36
Figure 9 LCD Driving Waveform for Displaying "0"
COM1
COM2
COM3
COM4
COM5
COM6
COM7
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
COM0
S
E
G
0
TIME SLOT
COM0
COM1
SEG0
SEG1
M
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
* Note : N is the number of multiplex ratio not included Icon.
1 2 3 4 5 6 7 8 9
. . . N+1
*
1 2 3 4 5 6 7 8 9
. . . N+1
*
1 2 3 4 5 6 7 8 9
. . . N+1
*
1 2 3 4 5 6 7 8 9
. . . N+1
*
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 16/36
COMMAND TABLE
Table 4 Write Command Table (D/C=0, R/W(WR)=0, E(RD)=1)
Bit Pattern
Command
Description
0000X
3
X
2
X
1
X
0
Set Lower Column Address
Set the lower nibble of the column address register using X
3
X
2
X
1
X
0
as data
bits. The lower nibble of column address register is reset to 0000b after POR.
0001X
3
X
2
X
1
X
0
Set Higher Column Address
Set the higher nibble of the column address register using X
3
X
2
X
1
X
0
as data
bits. The higher nibble of column address is reset to 0000b after POR.
00100X
2
X
1
X
0
Set Internal Regulator Resistor Ratio
Feedback gain of the internal regulator generating V
L6
increases as X
2
X
1
X
0
increased from 000b to 111b.
After POR, X
2
X
1
X
0
= 100b.
00101X
2
X
1
X
0
Set Power Control Register
X
0
=0: turns off the output op-amp buffer (POR)
X
0
=1: turns on the output op-amp buffer
X
1
=0: turns off the internal regulator (POR)
X
1
=1: turns on the internal regulator
X
2
=0: turns off the internal voltage booster (POR)
X
2
=1: turns on the internal voltage booster
01X
5
X
4
X
3
X
2
X
1
X
0
Set Display Start Line
Set GDDRAM display start line register from 0-63 using X
5
X
4
X
3
X
2
X
1
X
0
.
Display start line register is reset to 000000 after POR.
10000001
* * X
5
X
4
X
3
X
2
X
1
X
0
Set Contrast Control Register
Select contrast level from 64 contrast steps. Contrast increases (V
L6
decreases) as X
5
X
4
X
3
X
2
X
1
X
0
is increased from 000000b to 111111b.
X
5
X
4
X
3
X
2
X
1
X
0
= 100000b after POR
1010000X
0
Set Segment Re-map
X
0
=0: column address 00h is mapped to SEG0 (POR)
X
0
=1: column address 83h is mapped to SEG0
Refer to Figure 8 on page 14 for example.
1010001X
0
Set LCD Bias
X
0
=0: POR default bias: 1/9
X
0
=1: alternate bias: 1/7
For other bias ratio settings, see "Set 1/4 Bias Ratio" and "Set Bias Ratio" in
Extended Command Set.
1010010X
0
Set Entire Display On/Off
X
0
=0: normal display (POR)
X
0
=1: entire display on
1010011X
0
Set Normal/Reverse Display
X
0
=0: normal display (POR)
X
0
=1: reverse display
1010111X
0
Set Display On/Off
X
0
=0: turns off LCD panel (POR)
X
0
=1: turns on LCD panel
1011X
3
X
2
X
1
X
0
Set Page Address
Set GDDRAM Page Address (0-8) for read/write using X
3
X
2
X
1
X
0
1100X
3
* * *
Set COM Output Scan Direction
X
3
=0: normal mode (POR)
X
3
=1: remapped mode, COM0 to COM[N-1] becomes COM[N-1] to COM0
when Multiplex ratio is equal to N.
See Figure 8 on page 14 for detail mapping.
11100000
Set Read-Modify-Write Mode
Read-Modify-Write mode will be entered in which the column address will not
be increased during display data read. After POR, Read-modify-write mode is
turned OFF.
11100010
Software Reset
Initialize internal status registers.
11101110
Set End of Read-Modify-Write Mode
Exit Read-Modify-Write mode. RAM Column address before entering the
mode will be restored. After POR, Read-modify-write mode is OFF.
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 17/36
1010110X
0
* * * * * * X
1
X
0
Set Indicator On/Off
Indicator Display Mode,
This second byte command is
required ONLY when "Set Indicator
On" command is sent.
X
0
= 0: indicator off (POR, second command byte is not required)
X
0
= 1: indicator on (second command byte required)
X
1
X
0
= 00: indicator off
X
1
X
0
= 01: indicator on and blinking at ~1 second interval
X
1
X
0
= 10: indicator on and blinking at ~1/2 second interval
X
1
X
0
= 11: indicator on constantly
11100011
NOP
Command result in No Operation
11110000
Test Mode Reset
Reserved for IC testing. Do NOT use.
1111 * * * *
Set Test Mode
Reserved for IC testing. Do NOT use.
* * * * * * * *
Set Power Save Mode
(Standby or Sleep)
Standby or sleep mode will be entered using compound commands.
Issue compound commands "Set Display Off" followed by "Set Entire Display
On".
Table 5 Extended Command Table
Bit Pattern
Command
Description
10101000
00X
5
X
4
X
3
X
2
X
1
X
0
Set Multiplex Ratio
To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value)
for each member (including icon line).
Max. mux ratio: 65
N = X
5
X
4
X
3
X
2
X
1
X
0
+ 2, eg. N = 001111b + 2 = 17
10101001
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
Set Bias Ratio (X
1
X
0
)
Set TC Value (X
4
X
3
X
2
)
Modify Osc. Freq. (X
7
X
6
X
5
)
X
1
X
0
=
00
01
10
11
1/8 or 1/6
1/6 or 1/5
1/9 or 1/7 (POR) Prohibited
X
4
X
3
X
2
= 000: -0.01%/C (TC0, POR)
X
4
X
3
X
2
= 010: -0.15%/C (TC2)
X
4
X
3
X
2
= 100: -0.20%/C (TC4)
X
4
X
3
X
2
= 111: -0.30%/C (TC7)
X
4
X
3
X
2
= 001, 011, 101, 110: Reserved
Increase the value of X
7
X
6
X
5
will increase the oscillator frequency and vice
versa.
Default Mode:
X
7
X
6
X
5
= 011 (POR for SSD1815B) : Typ. 19kHz
High Frequency Mode:
X
7
X
6
X
5
= 110 (For SSD1815B) : Typ. 23kHz
1010101X
0
Set 1/4 Bias Ratio
X
0
= 0: use normal setting (POR)
X
0
= 1: fixed at 1/4 bias
11010100
00X
5
X
4
0000
Set Total Frame Phases
The On/Off of the Static Icon is given by 3 phases/1 phase overlapping of the
M and MSTAT signals. This command set total phases of the M/MSTAT sig-
nals for each frame.
The more the total phases, the less the overlapping time and thus the lower
the effective driving voltage.
X
5
X
4
= 00: 3 phases
X
5
X
4
= 01: 5 phases
X
5
X
4
= 10: 7 phases (POR)
X
5
X
4
= 11: 16 phases
11010011
00X
5
X
4
X
3
X
2
X
1
X
0
Set Display Offset
After POR, X
5
X
4
X
3
X
2
X
1
X
0
= 0
After setting mux ratio less than default value, data will be displayed at Center
of matrix.
To move display towards Row 0 by L, X
5
X
4
X
3
X
2
X
1
X
0
= L
To move display away from Row 0 by L, X
5
X
4
X
3
X
2
X
1
X
0
= 64-L
Note: max. value of L = (POR default mux ratio - display mux)/2
Table 4 Write Command Table (D/C=0, R/W(WR)=0, E(RD)=1)
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 18/36
Note:
Patterns other than that given in Command Table and Extended Command Table are prohibited to enter to the chip as a command. Otherwise,
unexpected result will occurs.
Data Read / Write
To read data from the GDDRAM, input High to R/W(WR) pin and D/C pin for 6800-series parallel mode, Low to E(RD) pin and High
to D/C pin for 8080-series parallel mode. No data read is provided in serial interface mode.
In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. However,
no automatic increase will be performed in read-modify-write mode.
Also, a dummy read is required before first valid data is read. See Figure 3 on page 10 in Functional Block Descriptions section for
detail waveform diagram.
To write data to the GDDRAM, input Low to R/W(WR) pin and High to D/C pin for both 6800-series and 8080-series parallel mode.
For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each
data write.
It should be noted that, after the automatic column address increment, the pointer will NOT wrap round to 0 when overflow (>131).
The incrementation of the pointer stops at 131. Therefore there is a need to re-initialize the pointer when progress to another page ad-
dress.
*1. If read data is issued in read-modify-write mode, address will not be increased automatically.
Table 6 Read Command Table (D/C=0, R/W(WR)=1, E=1(RD=0))
Bit Pattern
Command
Description
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Status Register Read
D
7
=0: indicates the driver is ready for command.
D
7
=1: indicates the driver is Busy.
D
6
=0: indicates reverse segment mapping with column address.
D
6
=1: indicates normal segment mapping with column address.
D
5
=0: indicates the display is ON.
D
5
=1: indicates the display is OFF.
D
4
=0: initialization is completed.
D
4
=1: initialization process is in progress after RES or software reset.
D
3
D
2
D
1
D
0
= 0010, these 4-bit is fixed to 0010 which could be used to identify
as Solomon Systech Device.
Table 7 Automatic Address Increment
D/C
R/W(WR)
Action
Auto Address
Increment
0
0
Write Command
No
0
1
Read Status
No
1
0
Write Data
Yes
1
1
Read Data
Yes
*1
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 19/36
COMMAND DESCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column
address of the display data RAM. The column address will be in-
creased by each data access after it is pre-set by the MCU.
Set Higher Column Address
This command specifies the higher nibble of the 8-bit col-
umn address of the display data RAM. The column address will
be increased by each data access after it is pre-set by the MCU.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal re-
sistor sets for different regulator gain when using internal regu-
lator resistor network (IRS pin pulled high). In other words, this
command is used to select which contrast curve from the eight
possible selections. Please refer to Functional Block Descrip-
tions section for detail calculation of the LCD driving voltage.
Set Power Control Register
This command turns on/off the various power circuits asso-
ciated with the chip. There are three power relating sub-circuits
could be turned on/off by this command.
Internal voltage booster is used to generated the large neg-
ative voltage supply (V
EE
) from the voltage input (V
SS1
- V
DD
).
An external negative power supply is required if this option is
turned off.
Internal regulator is used to generate the LCD driving volt-
age. V
L6
, from the negative power supply, V
EE
.
Output op-amp buffer is the internal divider for dividing the
different voltage levels (V
L2
, V
L3
, V
L4
, V
L5
) from the internal reg-
ulator output, V
L6
. External voltage sources should be fed into
this driver if this circuit is turned off.
Set Display Start Line
This command is to set Display Start Line register to deter-
mine starting address of display RAM to be displayed by select-
ing a value from 0 to 63. With value equals to 0, D0 of Page 0 is
mapped to COM0. With value equals to 1, D1 of Page0 is
mapped to COM0 and so on. Display start line values of 0 to 63
are assigned to Page 0 to 7.
Please refer to Figure 8 on page 14 as an example for dis-
play start line set to 56 (38h).
Set Contrast Control Register
This command adjusts the contrast of the LCD panel by
changing the LCD drive voltage, V
L6
, provided by the On-Chip
power circuits. V
L6
is set with 64 steps (6-bit) in the contrast con-
trol register by a compound commands.
See Figure 10 for the contrast control flow.
Set Segment Re-map
This command changes the mapping between the display
data column addresses and segment drivers. It allows flexibility
in mechanical layout of LCD glass design. Please refer to Figure
8 on page 14 for example.
Set LCD Bias
This command is used to select a suitable bias ratio re-
quired for driving the particular LCD panel in use.
The selectable values of this command are 1/9 or 1/7.
For other bias ratio settings, extended commands should be
used.
Set Entire Display On/Off
This command forces the entire display, including the icon
row, to be illuminated regardless of the contents of the GD-
DRAM. In addition, this command has higher priority than the
normal/reverse display.
This command is used together with "Set Display Display
ON/OFF" command to form a compound command for entering
power save mode. See "Set Power Save Mode" later in this sec-
tion.
Set Normal/Reverse Display
This command turns the display to be either normal or re-
versed. In normal display, a RAM data of 1 indicates an illumina-
tion on the corresponding pixel, while in reversed display, a RAM
data of 0 will turn on the pixel.
It should be noted that the icon line will not affect, that is not
be reversed, by this command.
Set Display On/Off
This command is used to turn the display on or off. When
display off is issued with entire display is on, power save mode
will be entered. See "Set Power Save Mode" later in this section
for details.
Set Page Address
This command enters the page address from 0 to 8 to the
RAM pager register for read/write operations. Please refer to
Figure 8 on page 14 for detail mapping.
Set COM Output Scan Direction
This command sets the scan direction of the COM output al-
lowing layout flexibility in LCD module assembly. See Figure 8
on page 14 for the relationship between turning on or off of this
feature.
In addition, the display will have immediate effect once this
command is issued. That is, if this command is sent during nor-
mal display, the graphic display will have vertical flipping effect.
Figure 10 Contrast Control Flow
Set Contrast Control Register
Contrast Level Data
Changes
Complete?
No
Yes
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 20/36
Set Read-Modify-Write Mode
This command puts the chip in read-modify-write mode in
which:
1. column address is saved before entering the mode
2. column address is increased only after display data write
but not after display data read.
This Ready-Modify-Write mode is used to save the MCU's
loading when a very portion of display area is being updated fre-
quently.
As reading the data will not change the column address, it
could be get back from the chip and do some operation in the
MCU. Then the updated data could be write back to the GD-
DRAM with automatic address increment.
After updating the area, "Set End of Read-Modify-Write
Mode" is sent to restore the column address and ready for next
update sequence.
Software Reset
Issuing this command causes some of the chip's internal
status registers to be initialized:
Read-Modify-Write mode is exited
Static indicator is turned OFF
Display start line register is cleared to 0
Column address counter is cleared to 0
Page address is cleared to 0
Normal scan direction of the COM outputs
Internal regulator resistors Ratio is set to 4
Contrast control register is set to 20h
Set End of Read-Modify-Write Mode
This command relieves the chip from read-modify-write
mode. The column address before entering read-modify-write
mode will be restored no matter how much modification during
the read-modify-write mode.
Set Indicator On/Off
This command turns on or off the static indicator driven by
the M and MSTAT pins.
When the "Set Indicator On" command is sent, the second
command byte "Indicator Display Mode" must be followed. How-
ever, the "Set Indicator Off" command is a single byte command
and no second byte command is required.
The status of static indicator also controls whether standby
mode or sleep mode will be entered, after issuing the power
save compound command. See "Set Power Save Mode" later in
this section.
NOP
A command causing the chip takes No OPeration.
Set Test Mode
This command force the driver chip into its test mode for in-
ternal testing of the chip. Under normal operation, users should
NOT apply this command.
Set Power Save Mode
Entering Standby or Sleep Mode should be done by using a
compound command composed of "Set Display ON/OFF" and
"Set Entire Display ON/OFF" commands. When "Set Entire Dis-
play ON" is issued when display is OFF, either Standby Mode or
Sleep Mode will be entered.
The status of the Static Indicator will determine which power
save mode is entered. If static indicator is off, the Sleep Mode
will be entered:
Internal oscillator and LCD power supply circuits
are stopped
Segment and Common drivers output V
DD
level
The display data and operation mode before
sleep are held
Internal display RAM can still be accessed
If the static indicator is on, the chip enters Standby Mode
which is similar to sleep mode except addition with:
Internal oscillator is on
Static drive system is on
Please also be noted that during Standby Mode, if the soft-
ware reset command is issued, Sleep Mode will be entered. Both
power save modes can be exited by the issue of a new software
command or by pulling Low at hardware pin RES .
Status register Read
This command is issued by pulling D/C Low during a data
read (refer to Figure 11 on page 26 and Figure 12 on page 27 for
parallel interface waveforms). It allows the MCU to monitor the
internal status of the chip.
No status read is provided for serial mode.
EXTENDED COMMANDS
These commands are used, in addition to basic commands,
to trigger the enhanced features designed for the chip.
Set Multiplex Ratio
This command switches default multiplex ratio to any multi-
plex mode from 2 to the maximum multiplex ratio (POR value),
including the icon line. Max. mux ratio: 65
The chip pins ROW0-ROW63 will be switched to corre-
sponding COM signal output, see Table 8 on page 21 for exam-
ples of 18 multiplex (including icon line) settings without and with
7 lines display offset for SSD1815B.
It should be noted that after changing the display multiplex
ratio, the bias ratio may also need to be adjusted to make display
contrast consistent.
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 21/36
Note: X - Row pin will output non-selected COM signal.
Table 8 Row pin assignments for COM signals in 18 mux display (including icon line) with/without 7 line display offset towards
ROW0.
Die Pad
Name
SSD1815B
No Offset
7 lines
Offset
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
ROW9
ROW10
ROW11
ROW12
ROW13
ROW14
ROW15
ROW16
ROW17
ROW18
ROW19
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
COM0
COM1
COM2
COM3
ROW20
ROW21
ROW22
ROW23
ROW24
ROW25
ROW26
ROW27
ROW28
ROW29
ROW30
ROW31
X
X
X
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
ROW44
ROW45
ROW46
ROW47
ROW48
ROW49
ROW50
ROW51
ROW52
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
X
X
X
X
X
X
X
X
X
X
X
X
X
COM16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ROW53
ROW54
ROW55
ROW56
ROW57
ROW58
ROW59
ROW60
ROW61
ROW62
ROW63
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 22/36
Set Bias Ratio
Except the 1/4 bias, all other available bias ratios could be
selected using this command plus the "Set LCD Bias" command.
For detail setting values and POR default, please refer to
the extended command table, Table 5 on page 17.
Set Temperature Coefficient (TC) Value
4 different temperature coefficient settings is selected by
this command in order to match various liquid crystal tempera-
ture grades. Please refer to the extended command table, Table
5 on page 17, for detail TC values.
Modify Oscillator Frequency
The oscillator frequency can be fine tuned by applying this
command. Since the oscillator frequency will be affected by
some other factors, this command is not recommended for gen-
eral usage. Please contact SOLOMON Systech Limited applica-
tion engineers for more detail explanation on this command.
Set 1/4 Bias Ratio
This command sets the bias ratio directly to 1/4. This bias
ratio is especially designed for use in under 12 mux display.
In order to restore to other bias ratio, this command must be
executed, with LSB=0, before the "Set Multiplex ratio" or "Set
LCD Bias" command is sent.
Set Total Frame Phases
The total number of phases for one display frame is set by
this command.
The Static Icon is generated by the overlapping of the M and
MSTAT signals. These two pins output either V
SS
or V
DD
at
same frequency but with phase different.
To turn on the Static Icon, 3 phases overlapping is applied
to these signals, while 1 phase overlapping is given to the Off
status.
The more the total number of phases in one frame, the less
the overlapping time and thus the lower the effective driving volt-
age at the Static Icon on the LCD panel.
Set Display Offset
This command should be sent ONLY when the multiplex ra-
tio is set less than SSD1815B's default value.
When a lesser multiplex ratio is set, the display will be
mapped in the middle (y-direction) of the LCD, see the no offset
columns on Table 8 on page 21. Use this command could move
the display vertically within the 64 commons.
To make the Reduced-Mux Com 0 (Com 0 after reducing
the multiplex ratio) towards the Row 0 direction for L lines, the 6-
bit data in second command should be given by L. An example
for 7 line moving towards to Com0 direction is given on Table 8
on page 21.
To move in the other direction by L lines, the 6-bit data
should be given by 64-L.
Please note that the display confined within SSD1815B's
default multiplex value. That is the maximum value of L is given
by the half of the default value minus the reduced-multiplex ratio.
For an odd display mux after reduction, moving away from Row
0 direction will has 1 more step.
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 23/36
MAXIMUM RATINGS
* Maximum Ratings are those values beyond which damage to the device may occur. Func-
tional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Description section.
Table 9 Maximum Ratings* (Voltage Reference to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.3 to +4.0
V
V
EE
0 to -12.0
V
V
in
Input Voltage
V
SS
-0.3 to
V
DD
+0.3
V
I
Current Drain Per Pin Excluding V
DD
and V
SS
25
mA
T
A
Operating Temperature
-30 to +85
C
T
stg
Storage Temperature Range
-65 to +150
C
This device contains circuitry to protect the inputs
against damage due to high static voltages or elec-
tric fields; however, it is advised that normal precau-
tions to be taken to avoid application of any voltage
higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recom-
mended that V
in
a n d V
out
be constrained to the
range V
SS
< or = (V
in
or V
out
) < or = V
DD
. Reliability
of operation is enhanced if unused input are con-
nected to an appropriate logic voltage level (e.g.,
either V
SS
o r V
DD
). Unused outputs must be left
open. This device may be light sensitive. Caution
should be taken to avoid exposure of this device to
any light source during normal operation. This
device is not radiation protected.
DC CHARACTERISTICS
Table 10 DC Characteristics
(Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to 3.5V, T
A
= -30 to 85C.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
DD
Logic Circuit Supply Voltage Range
Recommend Operating Voltage
Possible Operating Voltage
2.4
1.8
2.7
-
3.5
3.5
V
V
I
AC
I
DP1
I
DP2
I
SB
I
SLEEP
Access Mode Supply Current Drain
(V
D D
Pins)
Display Mode Supply Current Drain
(V
D D
Pins)
Display Mode Supply Current Drain
(V
D D
Pins)
Standby Mode Supply Current Drain
(V
D D
Pins)
Sleep Mode Supply Current Drain (V
DD
Pins)
V
DD
= 2.7V, Voltage Generator On, 4X
DC-DC Converter Enabled, Write access-
ing, T
cyc
=3.3MHz, Typ. Osc. Freq., Dis-
play On, no panel attached.
V
DD
= 2.7V, V
EE
= -8.1V, Voltage Genera-
tor Disabled, R/W (WR) Halt, Typ. Osc.
Freq., Display On, V
L6
- V
DD
= -9V, no
panel attached.
V
DD
= 2.7V, V
EE
= -8.1V, Voltage Genera-
tor On, 4x DC-DC Converter Enabled, R/
W(WR) Halt, Typ. Osc. Freq., Display On,
V
L6
- V
DD
= -9V, no panel attached.
V
DD
= 2.7V, LCD Driving Waveform Off,
Typ. Osc. Freq., R/W(WR) halt.
V
DD
= 2.7V, LCD Driving Waveform Off,
Oscillator Off, R/W(WR) halt.
-
-
-
-
-
300
60
150
3.5
0.2
600
100
200
10
5
A
A
A
A
A
V
EE
V
LCD
LCD Driving Voltage Generator Output
(V
EE
Pin)
LCD Driving Voltage Input (V
EE
Pin)
Display On, Voltage Generator Enabled,
DC-DC Converter Enabled, Typ. Osc.
Freq., Regulator Enabled, Divider
Enabled.
Voltage Generator Disabled.
-12.0
-12.0
-
-
-1.8
-1.8
V
V
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 24/36
V
OH1
V
OL1
V
L6
V
L6
Logic High Output Voltage
Logic Low Output Voltage
LCD Driving Voltage Source (V
L6
Pin)
LCD Driving Voltage Source (V
L6
Pin)
I
out
=-100
A
I
out
=100
A
Regulator Enabled (V
L6
voltage depends
on Int/Ext Contrast Control)
Regulator Disable
0.9*V
DD
0
V
EE
-0.5
-
-
-
-
Floating
V
DD
0.1*V
DD
V
DD
-
V
V
V
V
V
IH1
V
IL1
Logic High Input voltage
Logic Low Input voltage
0.8*V
DD
0
-
-
V
DD
0.2*V
DD
V
V
V
L2
V
L3
V
L4
V
L5
V
L6
V
L2
V
L3
V
L4
V
L5
V
L6
LCD Display Voltage Output
(V
L2
, V
L3
, V
L4
, V
L5
, V
L6
Pins)
LCD Display Voltage Input
(V
L2
, V
L3
,V
L4
, V
L5
, V
L6
Pins)
Voltage reference to V
DD
, Bias Divider
Enabled, 1:a bias ratio
Voltage reference to V
DD
, External Volt-
age Generator, Bias Divider Disabled
-
-
-
-
-
V
L3
V
L4
V
L5
V
L6
-12V
1/a*V
L6
2/a*V
L6
(a-2)/a*V
L6
(a-1)/a*V
L6
V
L6
-
-
-
-
-
-
-
-
-
-
V
DD
V
L2
V
L3
V
L4
V
L5
V
V
V
V
V
V
V
V
V
V
I
OH
I
OL
I
O Z
Logic High Output Current Source
Logic Low Output Current Drain
Logic Output Tri-state Current Drain
Source
V
out
= V
DD
-0.4V
V
out
= 0.4V
50
-
-1
-
-
-
-
-50
1
A
A
A
I
IL
/I
I H
Logic Input Current
-1
-
1
A
C
I N
Logic Pins Input Capacitance
-
5
7.5
pF
V
L6
Variation of V
L6
Output (V
DD
is fixed)
Regulator Enabled, Internal Contrast Con-
trol Enabled, Set Contrast Control Regis-
ter = 0
-3
0
3
%
TC0
TC2
TC4
TC7
Temperature Coefficient Compensation
Flat Temperature Coefficient (POR)
Temperature Coefficient 2*
Temperature Coefficient 4*
Temperature Coefficient 7*
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
0
-0.12
-0.17
-0.25
-0.01
-0.15
-0.20
-0.30
-0.12
-0.17
-0.25
-
% /
C
% /
C
% /
C
% /
C
Table 10 DC Characteristics
(Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to 3.5V, T
A
= -30 to 85C.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
* The formula for the temperature coefficient is:
TC(%) =
V
ref
at 50C - V
ref
at 0C
50C - 0C
X
1
V
ref
at 25C
X 100%
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 25/36
AC CHARACTERISTICS
* The formula for Oscillation Frequency vs Temperature Change:
Test Condition : VDD = 2.775V, TA = 25C, default contrast and internal resistor gain are used.
Table 11 AC Characteristics
(Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to 3.5V, T
A
= 25C.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
F
OSC
Oscillation Frequency of Display Timing
Generator for:
SSD1815B
Internal Oscillator Enabled (default), V
DD
= 2.7V
Remark:
Oscillation Frequency vs Temperature
change (-20C to 70C): -0.5%/ C
*
17
19
21
kHz
F
FRM
Frame Frequency for:
SSD1815B
132 x 64 Graphic Display Mode, Display
ON, Internal Oscillator Enabled
132 x 64 Graphic Display Mode, Display
ON, Internal Oscillator Disabled, External
clock with freq., F
ext
, feeding to CL pin.
Hz
F
OSC
4 x 65
%change (F
osc
) =
F
osc
at 70C - F
osc
at -20C
70C - (-20C)
X
1
F
osc
at 25C
X 100%
Frame Frequency vs. Temperature
50
55
60
65
70
75
80
85
90
95
-40
-20
0
20
40
60
80
100
Temperature [
o
C]
Frame frequency [Hz]
Frame Frequency vs.
Temperature
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 26/36
Table 12 6800-Series MPU Parallel Interface Timing Characteristics (V
DD
- V
SS
= 2.4 to 3.5V, T
A
= -30 to 85C)
Symbol
Parameter
Min
Typ
Max
Unit
t
cycle
Clock Cycle Time
300
-
-
ns
t
AS
Address Setup Time
0
-
-
ns
t
AH
Address Hold Time
0
-
-
ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
15
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output Disable Time
-
-
70
ns
t
ACC
Access Time
-
-
140
ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
-
-
-
-
ns
ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
-
-
ns
ns
t
R
Rise Time
-
-
15
ns
t
F
Fall Time
-
-
15
ns
Figure 11 6800-series MPU Parallel Interface Characteristics
Valid Data
t
cycle
t
DSW
t
AS
t
AH
t
DHR
t
ACC
CS1
D/C
D
0
-D
7
E
Valid Data
D
0
-D
7
(Write data to driver)
(Read data from driver)
t
DHW
PW
CSL
P W
CSH
t
F
t
R
R/W
(CS2=1)
t
O H
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 27/36
Table 13 8080-Series MPU Parallel Interface Timing Characteristics (V
DD
- V
SS
= 2.4 to 3.5V, T
A
= -30 to 85C)
Symbol
Parameter
Min
Typ
Max
Unit
t
cycle
Clock Cycle Time
300
-
-
ns
t
AS
Address Setup Time
0
-
-
ns
t
AH
Address Hold Time
0
-
-
ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
15
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output Disable Time
-
-
70
ns
t
ACC
Access Time
-
-
140
ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
-
-
-
-
ns
ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
-
-
ns
ns
t
R
Rise Time
-
-
15
ns
t
F
Fall Time
-
-
15
ns
Figure 12 8080-series MPU Parallel Interface Characteristics
Valid Data
t
cycle
t
DSW
t
AS
t
AH
t
DHR
t
ACC
WR
D
0
-D
7
Valid Data
D
0
-D
7
(Write data to driver)
(Read data from driver)
t
DHW
PW
CSL
PW
CSH
t
F
t
R
(CS2=1)
t
OH
D/C
CS1
RD
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 28/36
Table 14 Serial Interface Timing Characteristics (V
DD
- V
SS
= 2.4 to 3.5V, T
A
= -30 to 85C)
Symbol
Parameter
Min
Typ
Max
Unit
t
cycle
Clock Cycle Time
250
-
-
ns
t
AS
Address Setup Time
150
-
-
ns
t
AH
Address Hold Time
150
-
-
ns
t
CSS
Chip Select Setup Time (for D
7
input)
120
-
-
ns
t
CSH
Chip Select Hold Time (for D
0
input)
60
-
-
ns
t
DSW
Write Data Setup Time
100
-
-
ns
t
DHW
Write Data Hold Time
100
-
-
ns
t
CLKL
Clock Low Time
100
-
-
ns
t
CLKH
Clock High Time
100
-
-
ns
t
R
Rise Time
-
-
15
ns
t
F
Fall Time
-
-
15
ns
Figure 13 Serial Interface Characteristics
Valid Data
t
cycle
t
DSW
t
AS
t
AH
SCK
D/C
SDA
CS1
t
DHW
t
CLKL
t
CLKH
t
F
t
R
(CS2=1)
t
CSS
t
CSH
D6
D7
D4
D5
D2
D3
D0
D1
SDA
D/C
SCK
CS1
(CS2=1)
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 29/36
APPLICATION EXAMPLES
Figure 14 Application Circuit of 132 x 64 plus 2 icon lines using SSD1815B, configured with: external V
EE
, internal regulator,
divider mode enabled (Command: 2B), 6800-series MPU parallel interface, internal oscillator and master mode.
SSD1815B IC
( DIE FACE UP)
SEG0 --------------------------------------------- SEG131
ICONS
COM0
:
COM10
COM11
:
COM30
COM31
COM32
COM33
:
:
:
COM63
ICONS
ICONS
COM0
COM6
COM7
:
:
COM32
COM33
COM34
:
:
:
:
:
SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0
DISPLAY PANEL SIZE
132 x 64 + 2 X ICON LINES
:
64 MUX
R
e
m
a
p
p
e
d
C
O
M
S
C
A
N
D
i
r
e
c
t
i
o
n
[
C
o
m
m
a
n
d
:
C
8
]
R
e
m
a
p
p
e
d
C
O
M
S
C
A
N
D
i
r
e
c
t
i
o
n
[
C
o
m
m
a
n
d
:
C
8
]
Segment Remapped
[Command: A1]
:
COM4
COM5
D
0
-
D
7
R
/
W
/
C
S
1
D
/
C
V
S
S
[
G
N
D
]
V
E
E
I
R
S
External Vneg=-9.5V
COM18
COM19
C
O
M
2
0
:
C
O
M
2
6
C
O
M
2
7
:
C
O
M
3
1
I
C
O
N
S
C
O
M
6
3
:
C
O
M
5
7
C
O
M
5
6
Remapped COM
SCAN Direction
[Command: C8]
:
C
O
M
5
3
:
:
:
COM51
COM52
Remapped COM
SCAN Direction
[Command: C8]
VDD VL2 VL3 VL4 VL5
VDD=2.75V
Optional for External
Resistors Gain Control
[IRS must be pulled to GND]
0.1~0.47uF x 5
R1
R2
VL6
VF
Logic pin connections not specified above:
Pins connected to V
DD
: CS2, RD, M/S, CLS, C68/80, P/S, HPM
Pins connected to V
SS
: V
SS1
R
E
S
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 30/36
Figure 15 Application Circuit of 132 x 64 plus 2 icon lines using SSD1815B, configured with all internal power control circuit
enabled, 6800-series MPU parallel interface, internal oscillator and master mode.
SSD1815B IC
( DIE FACE UP)
SEG0 --------------------------------------------- SEG131
ICONS
COM0
:
COM10
COM11
:
COM30
COM31
COM32
COM33
:
:
:
COM63
ICONS
ICONS
COM0
COM6
COM7
:
:
COM32
COM33
COM34
:
:
:
:
:
SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0
DISPLAY PANEL SIZE
132 x 64 + 2 X ICON LINES
:
64 MUX
R
e
m
a
p
p
e
d
C
O
M
S
C
A
N
D
i
r
e
c
t
i
o
n
[
C
o
m
m
a
n
d
:
C
8
]
R
e
m
a
p
p
e
d
C
O
M
S
C
A
N
D
i
r
e
c
t
i
o
n
[
C
o
m
m
a
n
d
:
C
8
]
Segment Remapped
[Command: A1]
:
COM4
COM5
COM18
COM19
C
O
M
2
0
:
C
O
M
2
5
C
O
M
2
6
:
C
O
M
3
1
I
C
O
N
S
C
O
M
6
3
:
C
O
M
5
9
C
O
M
5
8
Remapped COM
SCAN Direction
[Command: C8]
:
C
O
M
5
3
:
:
:
COM51
COM52
Remapped COM
SCAN Direction
[Command: C8]
C1N
C1P
C3N
VEE
VSS
VSS [GND]
C2P
C2N
Optional for External
Resistors Gain Control
[IRS must be pulled to GND]
VDD VL2 VL3 VL4 VL5
VDD=2.75V
0.1~0.47uF x 5
R 1
R2
VL6
VF
0.47~1uF x 4
Logic pin connections not specified above:
Pins connected to V
DD
: CS2, RD, M/S, CLS, C68/80, P/S, HPM
Pins connected to V
SS
: V
SS1
Pins floating: DOF, CL, V
FS
D
0
-
D
7
a
n
d
C
o
n
t
r
o
l
B
u
s
R
E
S
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 31/36
Figure 16 SSD1815BT TAB Drawing 1/2
APPENDIX A - TAB INFORMATION
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 32/36
Figure 17 SSD1815BT TAB Drawing 2/2
Copper View Pin Assignment
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 33/36
Figure 18 SSD1815BT2 TAB Drawing 1/2
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
P 34/36
Figure 19 SSD1815BT2 TAB Drawing 2/2
Internal Connections:
V
DD
: CS2, M/S
V
SS
: V
SS1
SSD1815B
Rev 1.6
Jul 2002
Solomon Systech
P 35/36
APPENDIX B - TAB WHEEL INFORMATION
Figure 20 TAB Wheel Mechanical Drawing
SECTION AA
A
A
W2
330mm
3.5mm
CORE DIA. 25.8mm
KEYWAY = 4.2mm
MATERIAL: HIGH IMPACT POLYSTYRENE (HIPS)
SURFACE RESISTIVITY: 1 X 10 OHM MIN
5
1 X 10 OHM MAX
9
TAPE LENGTH = 20m
35mm TAB
48mm TAB
70mm TAB
500.2 mm
370.2 mm
700.2 mm
W2
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guaran-
tee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do
vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Sys-
tech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affili-
ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design
or manufacture of the part.
Solomon Systech
Jul 2002
Rev 1.6
SSD1815B
http://www.solomon-systech.com
P 36/36
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